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path: root/gcc/config/aarch64/aarch64-builtins.c
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* [AArch64]Improve error message for non-constant immediatesalalaw012014-12-091-2/+2
* [AArch64] Fix ICE on non-constant indices to __builtin_aarch64_im_lane_boundsialalaw012014-12-091-8/+28
* gcc/testsuite/:alalaw012014-12-091-4/+2
* * config/sparc/sparc.c (sparc_atomic_assign_expand_fenv):jakub2014-12-021-3/+3
* * config/alpha/alpha.c (alpha_gimple_fold_builtin): Usejakub2014-12-021-15/+6
* [AArch64]Tidy up aarch64_simd_expand_argsalalaw012014-11-241-74/+52
* [AArch64] Add vector pattern for __builtin_ctzjiwang2014-11-211-0/+8
* PR target/63870cbaylis2014-11-201-1/+1
* gcc/:alalaw012014-11-171-1/+0
* Add bounds checking to vqdm*_lane intrinsics via a qualifier that also flips ...alalaw012014-11-121-12/+34
* 2014-11-11 Andrew Pinski <apinski@cavium.com>pinskia2014-11-111-0/+1
* [AArch64] Restructure arm_neon.h vector types.belagod2014-11-051-215/+296
* 2014-11-01 Andrew MacLeod <amacleod@redhat,com>amacleod2014-11-011-0/+1
* gcc/ada/rsandifo2014-10-291-16/+16
* [AArch64] Restore gimple_folding of reduction intrinsicsalalaw012014-10-271-21/+9
* 2014-10-27 Andrew MacLeod <amacleod@redhat.com>amacleod2014-10-271-0/+14
* [AArch64] Temporarily remove aarch64_gimple_fold_builtin code for reduction o...alalaw012014-10-271-0/+4
* [PATCH 1/2] [AARCH64,NEON] Add patterns + builtins for vld[234](q?)_lane_* in...cbaylis2014-10-241-0/+5
* [AArch64] Auto-generate the "BUILTIN_" macros for aarch64-builtins.cjgreenhalgh2014-09-221-119/+1
* [AArch64] Simplify vreinterpret for float64x1_t using casts.alalaw012014-09-111-38/+0
* [AArch64] PR 61749: Do not ICE in lane intrinsics when passed non-constant la...ktkachov2014-09-091-7/+11
* [Obvious] Remove unused aarch64_types_cmtst_qualifiers, was breaking bootstrap.alalaw012014-09-081-5/+0
* [PATCH AArch64 2/2] Remove vector compare/tst __builtinsalalaw012014-09-051-16/+0
* [PATCH AArch64 1/2] Improve codegen of vector compares inc. tst instructionalalaw012014-09-051-1/+6
* [PATCH][AArch64] Tidy: remove unused qualifier_const_pointeralalaw012014-09-051-3/+1
* [PATCH AArch64] Remove varargs from aarch64_simd_expand_argsalalaw012014-09-051-13/+3
* remove pointer-set.[ch]tbsaunde2014-08-071-1/+0
* [AArch64] Some aarch64-builtins.c cleanup.jgreenhalgh2014-08-051-70/+29
* [AArch64_be] Don't fold reduction intrinsics.jgreenhalgh2014-07-311-0/+14
* PR/60825 Make {int,uint}64x1_t in arm_neon.h a proper vector typealalaw012014-06-231-1/+3
* PR/60825 Make float64x1_t in arm_neon.h a proper vector typealalaw012014-06-231-23/+24
* [AArch64] Implement CRC32 ACLE intrinsics.ktkachov2014-06-111-1/+93
* [PATCH AArch64 2/2] Correct signedness of builtins, remove casts from arm_neon.halalaw012014-06-031-0/+4
* [PATCH AArch64 1/2] Correct signedness of builtins, remove casts from arm_neon.halalaw012014-06-031-0/+16
* Detect EXT patterns to vec_perm_const, use for EXT intrinsicsalalaw012014-05-291-0/+4
* 2014-05-23 Kugan Vivekanandarajah <kuganv@linaro.org>kugan2014-05-221-0/+154
* [AArch64] Improve vst4_lane intrinsicsjgreenhalgh2014-04-281-0/+5
* [AArch64] Vectorise bswap[16,32,64]ktkachov2014-04-241-1/+23
* [AArch64] 64-bit float vreinterpret implementionmshawcroft2014-04-221-0/+36
* [AArch64] Vreinterpret re-implemention.mshawcroft2014-04-221-1/+0
* [AArch64] vrnd<*>_f64 patchmshawcroft2014-04-221-0/+2
* [AArch64] Logical vector shift right conformancejgreenhalgh2014-03-241-0/+4
* gcc/yufeng2014-03-121-0/+4
* Update copyright years in gcc/rsandifo2014-01-021-1/+1
* Implement support for AArch64 Crypto PMULL.64.belagod2013-12-191-0/+11
* Implement support for AArch64 Crypto SHA1.belagod2013-12-191-0/+6
* Implement support for AArch64 Crypto AES.belagod2013-12-191-0/+8
* [AArch64] [3/4 Fix vtbx1]Implement bsl intrinsics using builtinsjgreenhalgh2013-11-261-0/+21
* [AArch64] [2/4 Fix vtbx1] Handle poly types in the new Simd types infrastructurejgreenhalgh2013-11-261-35/+78
* [AArch64] [1/4 Fix vtbx1] Allow signed and unsigned versions of intrinsicsjgreenhalgh2013-11-261-30/+30
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