| Commit message (Collapse) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | 2016-06-23 Jakub Sejdak <jakub.sejdak@phoesys.com> | ksejdak | 2016-06-23 | 1 | -0/+11 |
| | | | | | | | | | | | * config.gcc: Add support for arm*-*-phoenix* targets. * config/arm/t-phoenix: New. * config/phoenix.h: New. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@237728 138bc75d-0d04-0410-961f-82ee72b054a4 | ||||
| * | remove mep-* support | tbsaunde | 2016-06-21 | 1 | -12/+1 |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | libgcc/ChangeLog: 2016-06-21 Trevor Saunders <tbsaunde+gcc@tbsaunde.org> * config.host: Remove support for mep-*. * config/mep/lib1funcs.S: Remove. * config/mep/lib2funcs.c: Remove. * config/mep/t-mep: Remove. * config/mep/tramp.c: Remove. gcc/ChangeLog: 2016-06-21 Trevor Saunders <tbsaunde+gcc@tbsaunde.org> * common/config/mep/mep-common.c: Remove. * config.gcc: Remove mep-* support. * config/mep/constraints.md: Remove. * config/mep/default.h: Remove. * config/mep/intrinsics.h: Remove. * config/mep/intrinsics.md: Remove. * config/mep/ivc2-template.h: Remove. * config/mep/mep-c5.cpu: Remove. * config/mep/mep-core.cpu: Remove. * config/mep/mep-default.cpu: Remove. * config/mep/mep-ext-cop.cpu: Remove. * config/mep/mep-intrin.h: Remove. * config/mep/mep-ivc2.cpu: Remove. * config/mep/mep-pragma.c: Remove. * config/mep/mep-protos.h: Remove. * config/mep/mep.c: Remove. * config/mep/mep.cpu: Remove. * config/mep/mep.h: Remove. * config/mep/mep.md: Remove. * config/mep/mep.opt: Remove. * config/mep/predicates.md: Remove. * config/mep/t-mep: Remove. * doc/install.texi: Remove mep-* documentation. * doc/md.texi: Likewise. gcc/testsuite/ChangeLog: 2016-06-21 Trevor Saunders <tbsaunde+gcc@tbsaunde.org> * gcc.dg/tree-ssa/forwprop-28.c: Remove mep-* support. * gcc.dg/tree-ssa/reassoc-32.c: Likewise. * gcc.dg/tree-ssa/reassoc-33.c: Likewise. * gcc.dg/tree-ssa/reassoc-34.c: Likewise. * gcc.dg/tree-ssa/reassoc-35.c: Likewise. * gcc.dg/tree-ssa/reassoc-36.c: Likewise. * gcc.dg/tree-ssa/ssa-ifcombine-ccmp-1.c: Likewise. * gcc.dg/tree-ssa/ssa-ifcombine-ccmp-2.c: Likewise. * gcc.dg/tree-ssa/ssa-ifcombine-ccmp-3.c: Likewise. * gcc.dg/tree-ssa/ssa-ifcombine-ccmp-4.c: Likewise. * gcc.dg/tree-ssa/ssa-ifcombine-ccmp-5.c: Likewise. * gcc.dg/tree-ssa/ssa-ifcombine-ccmp-6.c: Likewise. * gcc.dg/tree-ssa/ssa-thread-11.c: Likewise. * gcc.dg/tree-ssa/vrp87.c: Likewise. * lib/target-supports.exp: Likewise. contrib/ChangeLog: 2016-06-21 Trevor Saunders <tbsaunde+gcc@tbsaunde.org> * config-list.mk: Stop testing mep-elf. libstdc++-v3/ChangeLog: 2016-06-21 Trevor Saunders <tbsaunde+gcc@tbsaunde.org> * configure.host: Remove mep-* support. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@237666 138bc75d-0d04-0410-961f-82ee72b054a4 | ||||
| * | remove avr-rtems support | tbsaunde | 2016-06-21 | 1 | -9/+1 |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | contrib/ChangeLog: 2016-06-21 Trevor Saunders <tbsaunde+gcc@tbsaunde.org> * config-list.mk: Stop testing avr-rtems. libgcc/ChangeLog: 2016-06-21 Trevor Saunders <tbsaunde+gcc@tbsaunde.org> * config.host: Remove support for avr-rtems. * config/avr/t-rtems: Remove. ChangeLog: 2016-06-21 Trevor Saunders <tbsaunde+gcc@tbsaunde.org> * configure: Regenerate. * configure.ac: Remove support for avr-rtems. gcc/ChangeLog: 2016-06-21 Trevor Saunders <tbsaunde+gcc@tbsaunde.org> * config.gcc: Remove support for avr-rtems. * config/avr/gen-avr-mmcu-specs.c: Likewise. * config/avr/rtems.h: Remove. * config/avr/t-rtems: Remove. contrib/header-tools/ChangeLog: 2016-06-21 Trevor Saunders <tbsaunde+gcc@tbsaunde.org> * README: Remove references to avr-rtems. * reduce-headers: Likewise. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@237665 138bc75d-0d04-0410-961f-82ee72b054a4 | ||||
| * | remove m32-rtems support | tbsaunde | 2016-06-21 | 1 | -5/+0 |
| | | | | | | | | | | | | | | | | | | | | | | | | libgcc/ChangeLog: 2016-06-21 Trevor Saunders <tbsaunde+gcc@tbsaunde.org> * config.host: Remove m32r-rtems support. gcc/ChangeLog: 2016-06-21 Trevor Saunders <tbsaunde+gcc@tbsaunde.org> * config.gcc: Remove m32r-rtems support. * config/m32r/rtems.h: Remove. contrib/ChangeLog: 2016-06-21 Trevor Saunders <tbsaunde+gcc@tbsaunde.org> * config-list.mk: Stop testing m32r-rtems. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@237664 138bc75d-0d04-0410-961f-82ee72b054a4 | ||||
| * | remove h8300-rtems support | tbsaunde | 2016-06-21 | 1 | -5/+0 |
| | | | | | | | | | | | | | | | | | | | | | | | | | contrib/ChangeLog: 2016-06-21 Trevor Saunders <tbsaunde+gcc@tbsaunde.org> * config-list.mk: Remove h8300-rtems support. libgcc/ChangeLog: 2016-06-21 Trevor Saunders <tbsaunde+gcc@tbsaunde.org> * config.host: Remove h8300-rtems support. gcc/ChangeLog: 2016-06-21 Trevor Saunders <tbsaunde+gcc@tbsaunde.org> * config.gcc: Remove h8300-rtems support. * config/h8300/rtems.h: Remove. * config/h8300/t-rtems: Remove. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@237663 138bc75d-0d04-0410-961f-82ee72b054a4 | ||||
| * | remove knetbsd support | tbsaunde | 2016-06-21 | 1 | -12/+5 |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | gcc/ChangeLog: 2016-06-21 Trevor Saunders <tbsaunde+gcc@tbsaunde.org> * config.gcc: Remove support for knetbsd. * configure.ac: Likewise. * config/i386/knetbsd-gnu.h: Remove. * config/i386/knetbsd-gnu64.h: Remove. * config/knetbsd-gnu.h: Remove. * configure: Regenerate. libgcc/ChangeLog: 2016-06-21 Trevor Saunders <tbsaunde+gcc@tbsaunde.org> * config.host: Remove support for knetbsd. libstdc++-v3/ChangeLog: 2016-06-21 Trevor Saunders <tbsaunde+gcc@tbsaunde.org> * configure: Regenerate. * configure.host: Remove support for knetbsd. * crossconfig.m4: Likewise. contrib/ChangeLog: 2016-06-21 Trevor Saunders <tbsaunde+gcc@tbsaunde.org> * config-list.mk: stop testing knetbsd. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@237662 138bc75d-0d04-0410-961f-82ee72b054a4 | ||||
| * | remove support for targeting openbsd 2 or 3 | tbsaunde | 2016-06-21 | 1 | -14/+0 |
| | | | | | | | | | | | | | | | | | | | | | | | | contrib/ChangeLog: 2016-06-21 Trevor Saunders <tbsaunde+gcc@tbsaunde.org> * config-list.mk: Stop testing openbsd3.0. libgcc/ChangeLog: 2016-06-21 Trevor Saunders <tbsaunde+gcc@tbsaunde.org> * config.host: Remove support for openbsd 2 and 3. gcc/ChangeLog: 2016-06-21 Trevor Saunders <tbsaunde+gcc@tbsaunde.org> * config.gcc: Remove support for openbsd 2 and 3. * config/openbsd-oldgas.h: Remove. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@237661 138bc75d-0d04-0410-961f-82ee72b054a4 | ||||
| * | remove support for the interix target | tbsaunde | 2016-06-21 | 1 | -15/+1 |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | contrib/ChangeLog: 2016-06-21 Trevor Saunders <tbsaunde+gcc@tbsaunde.org> * config-list.mk: Remove interix target. libgcc/ChangeLog: 2016-06-21 Trevor Saunders <tbsaunde+gcc@tbsaunde.org> * config.host: Remove interix support. * config/i386/t-interix: Remove. config/ChangeLog: 2016-06-21 Trevor Saunders <tbsaunde+gcc@tbsaunde.org> * elf.m4: Remove interix support. * picflag.m4: Likewise. fixincludes/ChangeLog: 2016-06-21 Trevor Saunders <tbsaunde+gcc@tbsaunde.org> * mkfixinc.sh: Remove interix support. gcc/ChangeLog: 2016-06-21 Trevor Saunders <tbsaunde+gcc@tbsaunde.org> * config.gcc: Remove interix support. * config/i386/i386-interix.h: Remove. * config/i386/interix.opt: Remove. * config/i386/t-interix: Remove. * configure: Regenerate. * configure.ac: Remove interix support. * doc/install.texi: Remove interix documentation. gcc/testsuite/ChangeLog: 2016-06-21 Trevor Saunders <tbsaunde+gcc@tbsaunde.org> * gcc.dg/attr-ms_struct-1.c: Stop testing interix. * gcc.dg/attr-ms_struct-2.c: Likewise. * gcc.dg/attr-ms_struct-packed1.c: Likewise. * gcc.dg/bf-ms-attrib.c: Likewise. * gcc.dg/bf-ms-layout-2.c: Likewise. * gcc.dg/bf-ms-layout-3.c: Likewise. * gcc.dg/bf-ms-layout.c: Likewise. * gcc.dg/bf-no-ms-layout.c: Likewise. * gcc.target/i386/bitfield1.c: Likewise. * gcc.target/i386/bitfield2.c: Likewise. * gcc.target/i386/bitfield3.c: Likewise. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@237660 138bc75d-0d04-0410-961f-82ee72b054a4 | ||||
| * | sparc: support for the SPARC M7 and VIS 4.0 | jemarch | 2016-06-06 | 1 | -1/+1 |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | gcc/ChangeLog: 2016-06-06 Jose E. Marchesi <jose.marchesi@oracle.com> * config/sparc/sparc.md (cpu): Add niagara7 cpu type. Include the M7 SPARC DFA scheduler. New attribute v3pipe. Annotate insns with v3pipe where appropriate. Define cpu_feature vis4. Add lzd instruction type and set it on clzdi_sp64 and clzsi_sp64. Add (V8QI "8") to vbits. Add insns {add,sub}v8qi3 Add insns ss{add,sub}v8qi3 Add insns us{add,sub}{v8qi,v4hi}3 Add insns {min,max}{v8qi,v4hi,v2si}3 Add insns {minu,maxu}{v8qi,v4hi,v2si}3 Add insns fpcmp{le,gt,ule,ug,ule,ugt}{8,16,32}_vis. * config/sparc/niagara4.md: Add a comment explaining the discrepancy between the documented latenty numbers and the implemented ones. * config/sparc/niagara7.md: New file. * configure.ac (HAVE_AS_SPARC5_VIS4): Define if the assembler supports SPARC5 and VIS 4.0 instructions. * configure: Regenerate. * config.in: Likewise. * config.gcc: niagara7 is a supported cpu in sparc*-*-* targets. * config/sparc/sol2.h (ASM_CPU32_DEFAUILT_SPEC): Set for TARGET_CPU_niagara7. (ASM_CPU64_DEFAULT_SPEC): Likewise. (CPP_CPU_SPEC): Handle niagara7. (ASM_CPU_SPEC): Likewise. * config/sparc/sparc-opts.h (processor_type): Add PROCESSOR_NIAGARA7. (mvis4): New option. * config/sparc/sparc.h (TARGET_CPU_niagara7): Define. (AS_NIAGARA7_FLAG): Define. (ASM_CPU64_DEFAULT_SPEC): Set for niagara7. (CPP_CPU64_DEFAULT_SPEC): Likewise. (CPP_CPU_SPEC): Handle niagara7. (ASM_CPU_SPEC): Likewise. * config/sparc/sparc.c (niagara7_costs): Define. (sparc_option_override): Handle niagara7 and adjust cache-related parameters with better values for niagara cpus. Also support VIS4. (sparc32_initialize_trampoline): Likewise. (sparc_use_sched_lookahead): Likewise. (sparc_issue_rate): Likewise. (sparc_register_move_cost): Likewise. (dump_target_flag_bits): Support VIS4. (sparc_vis_init_builtins): Likewise. (sparc_builtins): Likewise. * config/sparc/sparc-c.c (sparc_target_macros): Define __VIS__ for VIS4 4.0. * config/sparc/driver-sparc.c (cpu_names): Add SPARC-M7 and UltraSparc M7. * config/sparc/sparc.opt (sparc_processor_type): New value niagara7. * config/sparc/visintrin.h (__attribute__): Prototypes for the VIS4 builtins. * doc/invoke.texi (SPARC Options): Document -mcpu=niagara7 and -mvis4. * doc/extend.texi (SPARC VIS Built-in Functions): Document the VIS4 builtins. gcc/testsuite/ChangeLog: 2016-06-06 Jose E. Marchesi <jose.marchesi@oracle.com> * gcc.target/sparc/vis4misc.c: New file. * gcc.target/sparc/fpcmp.c: Likewise. * gcc.target/sparc/fpcmpu.c: Likewise. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@237132 138bc75d-0d04-0410-961f-82ee72b054a4 | ||||
| * | 2016-05-30 Andreas Tobler <andreast@gcc.gnu.org> | andreast | 2016-05-30 | 1 | -5/+3 |
| | | | | | | | | | | * config.gcc: Move hard float support for arm*hf*-*-freebsd* into armv6*-*-freebsd* for FreeBSD 11. Eliminate the arm*hf*-*-freebsd* target. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@236898 138bc75d-0d04-0410-961f-82ee72b054a4 | ||||
| * | 2016-05-30 Jose E. Marchesi <jose.marchesi@oracle.com> | paolo | 2016-05-30 | 1 | -2/+2 |
| | | | | | | | | | | | | | | * config.gcc (sparc*-*-*): Support cpu_32, cpu_64, tune_32 and tune_64. * doc/install.texi (--with-cpu-32, --with-cpu-64): Document support on SPARC. * config/sparc/linux64.h (OPTION_DEFAULT_SPECS): Add entries for cpu_32, cpu_64, tune_32 and tune_64. * config/sparc/sol2.h (OPTION_DEFAULT_SPECS): Likewise. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@236897 138bc75d-0d04-0410-961f-82ee72b054a4 | ||||
| * | Add support for MIPS SIMD Architecture (MSA). | rts | 2016-05-09 | 1 | -1/+1 |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | gcc/ * config.gcc: Add MSA header file for mips*-*-* target. * config/mips/constraints.md (YI, YC, YZ, Unv5, Uuv5, Usv5, Uuv6) (Ubv8i, Urv8): New constraints. * config/mips/mips-ftypes.def: Add function types for MSA builtins. * config/mips/mips-modes.def (V16QI, V8HI, V4SI, V2DI, V4SF) (V2DF, V32QI, V16HI, V8SI, V4DI, V8SF, V4DF): New modes. * config/mips/mips-msa.md: New file. * config/mips/mips-protos.h (mips_split_128bit_const_insns): New prototype. (mips_msa_idiv_insns): Likewise. (mips_split_128bit_move): Likewise. (mips_split_128bit_move_p): Likewise. (mips_split_msa_copy_d): Likewise. (mips_split_msa_insert_d): Likewise. (mips_split_msa_fill_d): Likewise. (mips_expand_msa_branch): Likewise. (mips_const_vector_same_val_p): Likewise. (mips_const_vector_same_bytes_p): Likewise. (mips_const_vector_same_int_p): Likewise. (mips_const_vector_shuffle_set_p): Likewise. (mips_const_vector_bitimm_set_p): Likewise. (mips_const_vector_bitimm_clr_p): Likewise. (mips_msa_vec_parallel_const_half): Likewise. (mips_msa_output_division): Likewise. (mips_ldst_scaled_shift): Likewise. (mips_expand_vec_cond_expr): Likewise. * config/mips/mips.c (enum mips_builtin_type): Add MIPS_BUILTIN_MSA_TEST_BRANCH. (mips_gen_const_int_vector_shuffle): New prototype. (mips_const_vector_bitimm_set_p): New function. (mips_const_vector_bitimm_clr_p): Likewise. (mips_const_vector_same_val_p): Likewise. (mips_const_vector_same_bytes_p): Likewise. (mips_const_vector_same_int_p): Likewise. (mips_const_vector_shuffle_set_p): Likewise. (mips_symbol_insns): Forbid loading symbols via immediate for MSA. (mips_valid_offset_p): Limit offset to 10-bit for MSA loads and stores. (mips_valid_lo_sum_p): Forbid loadings symbols via %lo(base) for MSA. (mips_lx_address_p): Add support load indexed address for MSA. (mips_address_insns): Add calculation of instructions needed for stores and loads for MSA. (mips_const_insns): Move CONST_DOUBLE below CONST_VECTOR. Handle CONST_VECTOR for MSA and let it fall through. (mips_ldst_scaled_shift): New function. (mips_subword_at_byte): Likewise. (mips_msa_idiv_insns): Likewise. (mips_legitimize_move): Validate MSA moves. (mips_rtx_costs): Add UNGE, UNGT, UNLE, UNLT cases. Add calculation of costs for MSA division. (mips_split_move_p): Check if MSA moves need splitting. (mips_split_move): Split MSA moves if necessary. (mips_split_128bit_move_p): New function. (mips_split_128bit_move): Likewise. (mips_split_msa_copy_d): Likewise. (mips_split_msa_insert_d): Likewise. (mips_split_msa_fill_d): Likewise. (mips_output_move): Handle MSA moves. (mips_expand_msa_branch): New function. (mips_print_operand): Add 'E', 'B', 'w', 'v' and 'V' modifiers. Reinstate 'y' modifier. (mips_file_start): Add MSA .gnu_attribute. (mips_hard_regno_mode_ok_p): Allow TImode and 128-bit vectors in FPRs. (mips_hard_regno_nregs): Always return 1 for MSA supported mode. (mips_class_max_nregs): Add register size for MSA supported mode. (mips_cannot_change_mode_class): Allow conversion between MSA vector modes and TImode. (mips_mode_ok_for_mov_fmt_p): Allow MSA to use move.v instruction. (mips_secondary_reload_class): Force MSA loads/stores via memory. (mips_preferred_simd_mode): Add preffered modes for MSA. (mips_vector_mode_supported_p): Add MSA supported modes. (mips_autovectorize_vector_sizes): New function. (mips_msa_output_division): Likewise. (MSA_BUILTIN, MIPS_BUILTIN_DIRECT_NO_TARGET) (MSA_NO_TARGET_BUILTIN, MSA_BUILTIN_TEST_BRANCH): New macros. (CODE_FOR_msa_adds_s_b, CODE_FOR_msa_adds_s_h) (CODE_FOR_msa_adds_s_w, CODE_FOR_msa_adds_s_d) (CODE_FOR_msa_adds_u_b, CODE_FOR_msa_adds_u_h) (CODE_FOR_msa_adds_u_w, CODE_FOR_msa_adds_u_du (CODE_FOR_msa_addv_b, CODE_FOR_msa_addv_h, CODE_FOR_msa_addv_w) (CODE_FOR_msa_addv_d, CODE_FOR_msa_and_v, CODE_FOR_msa_bmnz_v) (CODE_FOR_msa_bmnzi_b, CODE_FOR_msa_bmz_v, CODE_FOR_msa_bmzi_b) (CODE_FOR_msa_bnz_v, CODE_FOR_msa_bz_v, CODE_FOR_msa_bsel_v) (CODE_FOR_msa_bseli_b, CODE_FOR_msa_ceqi_h, CODE_FOR_msa_ceqi_w) (CODE_FOR_msa_ceqi_d, CODE_FOR_msa_clti_s_b) (CODE_FOR_msa_clti_s_h, CODE_FOR_msa_clti_s_w) (CODE_FOR_msa_clti_s_d, CODE_FOR_msa_clti_u_b) (CODE_FOR_msa_clti_u_h, CODE_FOR_msa_clti_u_w) (CODE_FOR_msa_clti_u_d, CODE_FOR_msa_clei_s_b) (CODE_FOR_msa_clei_s_h, CODE_FOR_msa_clei_s_w) (CODE_FOR_msa_clei_s_d, CODE_FOR_msa_clei_u_b) (CODE_FOR_msa_clei_u_h, CODE_FOR_msa_clei_u_w) (CODE_FOR_msa_clei_u_d, CODE_FOR_msa_div_s_b) (CODE_FOR_msa_div_s_h, CODE_FOR_msa_div_s_w) (CODE_FOR_msa_div_s_d, CODE_FOR_msa_div_u_b) (CODE_FOR_msa_div_u_h, CODE_FOR_msa_div_u_w) (CODE_FOR_msa_div_u_d, CODE_FOR_msa_fadd_w, CODE_FOR_msa_fadd_d) (CODE_FOR_msa_fexdo_w, CODE_FOR_msa_ftrunc_s_w) (CODE_FOR_msa_ftrunc_s_d, CODE_FOR_msa_ftrunc_u_w) (CODE_FOR_msa_ftrunc_u_d, CODE_FOR_msa_ffint_s_w) (CODE_FOR_msa_ffint_s_d, CODE_FOR_msa_ffint_u_w) (CODE_FOR_msa_ffint_u_d, CODE_FOR_msa_fsub_w) (CODE_FOR_msa_fsub_d, CODE_FOR_msa_fmsub_d, CODE_FOR_msa_fmadd_w) (CODE_FOR_msa_fmadd_d, CODE_FOR_msa_fmsub_w, CODE_FOR_msa_fmul_w) (CODE_FOR_msa_fmul_d, CODE_FOR_msa_fdiv_w, CODE_FOR_msa_fdiv_d) (CODE_FOR_msa_fmax_w, CODE_FOR_msa_fmax_d, CODE_FOR_msa_fmax_a_w) (CODE_FOR_msa_fmax_a_d, CODE_FOR_msa_fmin_w, CODE_FOR_msa_fmin_d) (CODE_FOR_msa_fmin_a_w, CODE_FOR_msa_fmin_a_d) (CODE_FOR_msa_fsqrt_w, CODE_FOR_msa_fsqrt_d) (CODE_FOR_msa_max_s_b, CODE_FOR_msa_max_s_h) (CODE_FOR_msa_max_s_w, CODE_FOR_msa_max_s_d) (CODE_FOR_msa_max_u_b, CODE_FOR_msa_max_u_h) (CODE_FOR_msa_max_u_w, CODE_FOR_msa_max_u_d) (CODE_FOR_msa_min_s_b, CODE_FOR_msa_min_s_h) (CODE_FOR_msa_min_s_w, CODE_FOR_msa_min_s_d) (CODE_FOR_msa_min_u_b, CODE_FOR_msa_min_u_h) (CODE_FOR_msa_min_u_w, CODE_FOR_msa_min_u_d) (CODE_FOR_msa_mod_s_b, CODE_FOR_msa_mod_s_h) (CODE_FOR_msa_mod_s_w, CODE_FOR_msa_mod_s_d) (CODE_FOR_msa_mod_u_b, CODE_FOR_msa_mod_u_h) (CODE_FOR_msa_mod_u_w, CODE_FOR_msa_mod_u_d) (CODE_FOR_msa_mod_s_b, CODE_FOR_msa_mod_s_h) (CODE_FOR_msa_mod_s_w, CODE_FOR_msa_mod_s_d) (CODE_FOR_msa_mod_u_b, CODE_FOR_msa_mod_u_h) (CODE_FOR_msa_mod_u_w, CODE_FOR_msa_mod_u_d) (CODE_FOR_msa_mulv_b, CODE_FOR_msa_mulv_h, CODE_FOR_msa_mulv_w) (CODE_FOR_msa_mulv_d, CODE_FOR_msa_nlzc_b, CODE_FOR_msa_nlzc_h) (CODE_FOR_msa_nlzc_w, CODE_FOR_msa_nlzc_d, CODE_FOR_msa_nor_v) (CODE_FOR_msa_or_v, CODE_FOR_msa_ori_b, CODE_FOR_msa_nori_b) (CODE_FOR_msa_pcnt_b, CODE_FOR_msa_pcnt_h, CODE_FOR_msa_pcnt_w) (CODE_FOR_msa_pcnt_d, CODE_FOR_msa_xor_v, CODE_FOR_msa_xori_b) (CODE_FOR_msa_sll_b, CODE_FOR_msa_sll_h, CODE_FOR_msa_sll_w) (CODE_FOR_msa_sll_d, CODE_FOR_msa_slli_b, CODE_FOR_msa_slli_h) (CODE_FOR_msa_slli_w, CODE_FOR_msa_slli_d, CODE_FOR_msa_sra_b) (CODE_FOR_msa_sra_h, CODE_FOR_msa_sra_w, CODE_FOR_msa_sra_d) (CODE_FOR_msa_srai_b, CODE_FOR_msa_srai_h, CODE_FOR_msa_srai_w) (CODE_FOR_msa_srai_d, CODE_FOR_msa_srl_b, CODE_FOR_msa_srl_h) (CODE_FOR_msa_srl_w, CODE_FOR_msa_srl_d, CODE_FOR_msa_srli_b) (CODE_FOR_msa_srli_h, CODE_FOR_msa_srli_w, CODE_FOR_msa_srli_d) (CODE_FOR_msa_subv_b, CODE_FOR_msa_subv_h, CODE_FOR_msa_subv_w) (CODE_FOR_msa_subv_d, CODE_FOR_msa_subvi_b, CODE_FOR_msa_subvi_h) (CODE_FOR_msa_subvi_w, CODE_FOR_msa_subvi_d, CODE_FOR_msa_move_v) (CODE_FOR_msa_vshf_b, CODE_FOR_msa_vshf_h, CODE_FOR_msa_vshf_w) (CODE_FOR_msa_vshf_d, CODE_FOR_msa_ilvod_d, CODE_FOR_msa_ilvev_d) (CODE_FOR_msa_pckod_d, CODE_FOR_msa_pckdev_d, CODE_FOR_msa_ldi_b) (CODE_FOR_msa_ldi_hi, CODE_FOR_msa_ldi_w) (CODE_FOR_msa_ldi_d): New code_aliasing macros. (mips_builtins): Add MSA sll_b, sll_h, sll_w, sll_d, slli_b, slli_h, slli_w, slli_d, sra_b, sra_h, sra_w, sra_d, srai_b, srai_h, srai_w, srai_d, srar_b, srar_h, srar_w, srar_d, srari_b, srari_h, srari_w, srari_d, srl_b, srl_h, srl_w, srl_d, srli_b, srli_h, srli_w, srli_d, srlr_b, srlr_h, srlr_w, srlr_d, srlri_b, srlri_h, srlri_w, srlri_d, bclr_b, bclr_h, bclr_w, bclr_d, bclri_b, bclri_h, bclri_w, bclri_d, bset_b, bset_h, bset_w, bset_d, bseti_b, bseti_h, bseti_w, bseti_d, bneg_b, bneg_h, bneg_w, bneg_d, bnegi_b, bnegi_h, bnegi_w, bnegi_d, binsl_b, binsl_h, binsl_w, binsl_d, binsli_b, binsli_h, binsli_w, binsli_d, binsr_b, binsr_h, binsr_w, binsr_d, binsri_b, binsri_h, binsri_w, binsri_d, addv_b, addv_h, addv_w, addv_d, addvi_b, addvi_h, addvi_w, addvi_d, subv_b, subv_h, subv_w, subv_d, subvi_b, subvi_h, subvi_w, subvi_d, max_s_b, max_s_h, max_s_w, max_s_d, maxi_s_b, maxi_s_h, maxi_s_w, maxi_s_d, max_u_b, max_u_h, max_u_w, max_u_d, maxi_u_b, maxi_u_h, maxi_u_w, maxi_u_d, min_s_b, min_s_h, min_s_w, min_s_d, mini_s_b, mini_s_h, mini_s_w, mini_s_d, min_u_b, min_u_h, min_u_w, min_u_d, mini_u_b, mini_u_h, mini_u_w, mini_u_d, max_a_b, max_a_h, max_a_w, max_a_d, min_a_b, min_a_h, min_a_w, min_a_d, ceq_b, ceq_h, ceq_w, ceq_d, ceqi_b, ceqi_h, ceqi_w, ceqi_d, clt_s_b, clt_s_h, clt_s_w, clt_s_d, clti_s_b, clti_s_h, clti_s_w, clti_s_d, clt_u_b, clt_u_h, clt_u_w, clt_u_d, clti_u_b, clti_u_h, clti_u_w, clti_u_d, cle_s_b, cle_s_h, cle_s_w, cle_s_d, clei_s_b, clei_s_h, clei_s_w, clei_s_d, cle_u_b, cle_u_h, cle_u_w, cle_u_d, clei_u_b, clei_u_h, clei_u_w, clei_u_d, ld_b, ld_h, ld_w, ld_d, st_b, st_h, st_w, st_d, sat_s_b, sat_s_h, sat_s_w, sat_s_d, sat_u_b, sat_u_h, sat_u_w, sat_u_d, add_a_b, add_a_h, add_a_w, add_a_d, adds_a_b, adds_a_h, adds_a_w, adds_a_d, adds_s_b, adds_s_h, adds_s_w, adds_s_d, adds_u_b, adds_u_h, adds_u_w, adds_u_d, ave_s_b, ave_s_h, ave_s_w, ave_s_d, ave_u_b, ave_u_h, ave_u_w, ave_u_d, aver_s_b, aver_s_h, aver_s_w, aver_s_d, aver_u_b, aver_u_h, aver_u_w, aver_u_d, subs_s_b, subs_s_h, subs_s_w, subs_s_d, subs_u_b, subs_u_h, subs_u_w, subs_u_d, subsuu_s_b, subsuu_s_h, subsuu_s_w, subsuu_s_d, subsus_u_b, subsus_u_h, subsus_u_w, subsus_u_d, asub_s_b, asub_s_h, asub_s_w, asub_s_d, asub_u_b, asub_u_h, asub_u_w, asub_u_d, mulv_b, mulv_h, mulv_w, mulv_d, maddv_b, maddv_h, maddv_w, maddv_d, msubv_b, msubv_h, msubv_w, msubv_d, div_s_b, div_s_h, div_s_w, div_s_d, div_u_b, div_u_h, div_u_w, div_u_d, hadd_s_h, hadd_s_w, hadd_s_d, hadd_u_h, hadd_u_w, hadd_u_d, hsub_s_h, hsub_s_w, hsub_s_d, hsub_u_h, hsub_u_w, hsub_u_d, mod_s_b, mod_s_h, mod_s_w, mod_s_d, mod_u_b, mod_u_h, mod_u_w, mod_u_d, dotp_s_h, dotp_s_w, dotp_s_d, dotp_u_h, dotp_u_w, dotp_u_d, dpadd_s_h, dpadd_s_w, dpadd_s_d, dpadd_u_h, dpadd_u_w, dpadd_u_d, dpsub_s_h, dpsub_s_w, dpsub_s_d, dpsub_u_h, dpsub_u_w, dpsub_u_d, sld_b, sld_h, sld_w, sld_d, sldi_b, sldi_h, sldi_w, sldi_d, splat_b, splat_h, splat_w, splat_d, splati_b, splati_h, splati_w, splati_d, pckev_b, pckev_h, pckev_w, pckev_d, pckod_b, pckod_h, pckod_w, pckod_d, ilvl_b, ilvl_h, ilvl_w, ilvl_d, ilvr_b, ilvr_h, ilvr_w, ilvr_d, ilvev_b, ilvev_h, ilvev_w, ilvev_d, ilvod_b, ilvod_h, ilvod_w, ilvod_d, vshf_b, vshf_h, vshf_w, vshf_d, and_v, andi_b, or_v, ori_b, nor_v, nori_b, xor_v, xori_b, bmnz_v, bmnzi_b, bmz_v, bmzi_b, bsel_v, bseli_b, shf_b, shf_h, shf_w, bnz_v, bz_v, fill_b, fill_h, fill_w, fill_d, pcnt_b, pcnt_h, pcnt_w, pcnt_d, nloc_b, nloc_h, nloc_w, nloc_d, nlzc_b, nlzc_h, nlzc_w, nlzc_d, copy_s_b, copy_s_h, copy_s_w, copy_s_d, copy_u_b, copy_u_h, copy_u_w, copy_u_d, insert_b, insert_h, insert_w, insert_d, insve_b, insve_h, insve_w, insve_d, bnz_b, bnz_h, bnz_w, bnz_d, bz_b, bz_h, bz_w, bz_d, ldi_b, ldi_h, ldi_w, ldi_d, fcaf_w, fcaf_d, fcor_w, fcor_d, fcun_w, fcun_d, fcune_w, fcune_d, fcueq_w, fcueq_d, fceq_w, fceq_d, fcne_w, fcne_d, fclt_w, fclt_d, fcult_w, fcult_d, fcle_w, fcle_d, fcule_w, fcule_d, fsaf_w, fsaf_d, fsor_w, fsor_d, fsun_w, fsun_d, fsune_w, fsune_d, fsueq_w, fsueq_d, fseq_w, fseq_d, fsne_w, fsne_d, fslt_w, fslt_d, fsult_w, fsult_d, fsle_w, fsle_d, fsule_w, fsule_d, fadd_w, fadd_d, fsub_w, fsub_d, fmul_w, fmul_d, fdiv_w, fdiv_d, fmadd_w, fmadd_d, fmsub_w, fmsub_d, fexp2_w, fexp2_d, fexdo_h, fexdo_w, ftq_h, ftq_w, fmin_w, fmin_d, fmin_a_w, fmin_a_d, fmax_w, fmax_d, fmax_a_w, fmax_a_d, mul_q_h, mul_q_w, mulr_q_h, mulr_q_w, madd_q_h, madd_q_w, maddr_q_h, maddr_q_w, msub_q_h, msub_q_w, msubr_q_h, msubr_q_w, fclass_w, fclass_d, fsqrt_w, fsqrt_d, frcp_w, frcp_d, frint_w, frint_d, frsqrt_w, frsqrt_d, flog2_w, flog2_d, fexupl_w, fexupl_d, fexupr_w, fexupr_d, ffql_w, ffql_d, ffqr_w, ffqr_d, ftint_s_w, ftint_s_d, ftint_u_w, ftint_u_d, ftrunc_s_w, ftrunc_s_d, ftrunc_u_w, ftrunc_u_d, ffint_s_w, ffint_s_d, ffint_u_w, ffint_u_d, ctcmsa, cfcmsa, move_v builtins. (mips_get_builtin_decl_index): New array. (MIPS_ATYPE_QI, MIPS_ATYPE_HI, MIPS_ATYPE_V2DI, MIPS_ATYPE_V4SI) (MIPS_ATYPE_V8HI, MIPS_ATYPE_V16QI, MIPS_ATYPE_V2DF) (MIPS_ATYPE_V4SF, MIPS_ATYPE_UV2DI, MIPS_ATYPE_UV4SI) (MIPS_ATYPE_UV8HI, MIPS_ATYPE_UV16QI): New. (mips_init_builtins): Initialize mips_get_builtin_decl_index array. (TARGET_VECTORIZE_BUILTIN_VECTORIZED_FUNCTION): Define target hook. (mips_expand_builtin_insn): Prepare operands for CODE_FOR_msa_addvi_b, CODE_FOR_msa_addvi_h, CODE_FOR_msa_addvi_w, CODE_FOR_msa_addvi_d, CODE_FOR_msa_clti_u_b, CODE_FOR_msa_clti_u_h, CODE_FOR_msa_clti_u_w, CODE_FOR_msa_clti_u_d, CODE_FOR_msa_clei_u_b, CODE_FOR_msa_clei_u_h, CODE_FOR_msa_clei_u_w, CODE_FOR_msa_clei_u_d, CODE_FOR_msa_maxi_u_b, CODE_FOR_msa_maxi_u_h, CODE_FOR_msa_maxi_u_w, CODE_FOR_msa_maxi_u_d, CODE_FOR_msa_mini_u_b, CODE_FOR_msa_mini_u_h, CODE_FOR_msa_mini_u_w, CODE_FOR_msa_mini_u_d, CODE_FOR_msa_subvi_b, CODE_FOR_msa_subvi_h, CODE_FOR_msa_subvi_w, CODE_FOR_msa_subvi_d, CODE_FOR_msa_ceqi_b, CODE_FOR_msa_ceqi_h, CODE_FOR_msa_ceqi_w, CODE_FOR_msa_ceqi_d, CODE_FOR_msa_clti_s_b, CODE_FOR_msa_clti_s_h, CODE_FOR_msa_clti_s_w, CODE_FOR_msa_clti_s_d, CODE_FOR_msa_clei_s_b, CODE_FOR_msa_clei_s_h, CODE_FOR_msa_clei_s_w, CODE_FOR_msa_clei_s_d, CODE_FOR_msa_maxi_s_b, CODE_FOR_msa_maxi_s_h, CODE_FOR_msa_maxi_s_w, CODE_FOR_msa_maxi_s_d, CODE_FOR_msa_mini_s_b, CODE_FOR_msa_mini_s_h, CODE_FOR_msa_mini_s_w, CODE_FOR_msa_mini_s_d, CODE_FOR_msa_andi_b, CODE_FOR_msa_ori_b, CODE_FOR_msa_nori_b, CODE_FOR_msa_xori_b, CODE_FOR_msa_bmzi_b, CODE_FOR_msa_bmnzi_b, CODE_FOR_msa_bseli_b, CODE_FOR_msa_fill_b, CODE_FOR_msa_fill_h, CODE_FOR_msa_fill_w, CODE_FOR_msa_fill_d, CODE_FOR_msa_ilvl_b, CODE_FOR_msa_ilvl_h, CODE_FOR_msa_ilvl_w, CODE_FOR_msa_ilvl_d, CODE_FOR_msa_ilvr_b, CODE_FOR_msa_ilvr_h, CODE_FOR_msa_ilvr_w, CODE_FOR_msa_ilvr_d, CODE_FOR_msa_ilvev_b, CODE_FOR_msa_ilvev_h, CODE_FOR_msa_ilvev_w, CODE_FOR_msa_ilvod_b, CODE_FOR_msa_ilvod_h, CODE_FOR_msa_ilvod_w, CODE_FOR_msa_pckev_b, CODE_FOR_msa_pckev_h, CODE_FOR_msa_pckev_w, CODE_FOR_msa_pckod_b, CODE_FOR_msa_pckod_h, CODE_FOR_msa_pckod_w, CODE_FOR_msa_slli_b, CODE_FOR_msa_slli_h, CODE_FOR_msa_slli_w, CODE_FOR_msa_slli_d, CODE_FOR_msa_srai_b, CODE_FOR_msa_srai_h, CODE_FOR_msa_srai_w, CODE_FOR_msa_srai_d, CODE_FOR_msa_srli_b, CODE_FOR_msa_srli_h, CODE_FOR_msa_srli_w, CODE_FOR_msa_srli_d, CODE_FOR_msa_insert_b, CODE_FOR_msa_insert_h, CODE_FOR_msa_insert_w, CODE_FOR_msa_insert_d, CODE_FOR_msa_insve_b, CODE_FOR_msa_insve_h, CODE_FOR_msa_insve_w, CODE_FOR_msa_insve_d, CODE_FOR_msa_shf_b, CODE_FOR_msa_shf_h, CODE_FOR_msa_shf_w, CODE_FOR_msa_shf_w_f, CODE_FOR_msa_vshf_b, CODE_FOR_msa_vshf_h, CODE_FOR_msa_vshf_w, CODE_FOR_msa_vshf_d. (mips_expand_builtin): Add case for MIPS_BULTIN_MSA_TEST_BRANCH. (mips_set_compression_mode): Disallow MSA with MIPS16 code. (mips_option_override): -mmsa requires -mfp64 and -mhard-float. These are set implicitly and an error is reported if overridden. (mips_expand_builtin_msa_test_branch): New function. (mips_expand_msa_shuffle): Likewise. (MAX_VECT_LEN): Increase maximum length of a vector to 16 bytes. (TARGET_SCHED_REASSOCIATION_WIDTH): Define target hook. (TARGET_VECTORIZE_AUTOVECTORIZE_VECTOR_SIZES): Likewise. (mips_expand_vec_unpack): Add support for MSA. (mips_expand_vector_init): Likewise. (mips_expand_vi_constant): Use CONST0_RTX (element_mode) instead of const0_rtx. (mips_msa_vec_parallel_const_half): New function. (mips_gen_const_int_vector): Likewise. (mips_gen_const_int_vector_shuffle): Likewise. (mips_expand_msa_cmp): Likewise. (mips_expand_vec_cond_expr): Likewise. * config/mips/mips.h (TARGET_CPU_CPP_BUILTINS): Add __mips_msa and __mips_msa_width. (OPTION_DEFAULT_SPECS): Ignore --with-fp-32 if -mmsa is specified. (ASM_SPEC): Pass mmsa and mno-msa to the assembler. (ISA_HAS_MSA): New macro. (UNITS_PER_MSA_REG): Likewise. (BITS_PER_MSA_REG): Likewise. (BIGGEST_ALIGNMENT): Redefine using ISA_HAS_MSA. (MSA_REG_FIRST): New macro. (MSA_REG_LAST): Likewise. (MSA_REG_NUM): Likewise. (MSA_REG_P): Likewise. (MSA_REG_RTX_P): Likewise. (MSA_SUPPORTED_MODE_P): Likewise. (HARD_REGNO_CALL_PART_CLOBBERED): Redefine using TARGET_MSA. (ADDITIONAL_REGISTER_NAMES): Add named registers $w0-$w31. * config/mips/mips.md: Include mips-msa.md. (alu_type): Add simd_add. (mode): Add V2DI, V4SI, V8HI, V16QI, V2DF, V4SF. (type): Add simd_div, simd_fclass, simd_flog2, simd_fadd, simd_fcvt, simd_fmul, simd_fmadd, simd_fdiv, simd_bitins, simd_bitmov, simd_insert, simd_sld, simd_mul, simd_fcmp, simd_fexp2, simd_int_arith, simd_bit, simd_shift, simd_splat, simd_fill, simd_permute, simd_shf, simd_sat, simd_pcnt, simd_copy, simd_branch, simd_cmsa, simd_fminmax, simd_logic, simd_move, simd_load, simd_store. Choose "multi" for moves for "qword_mode". (qword_mode): New attribute. (insn_count): Add instruction count for quad moves. Increase the count for MIPS SIMD division. (UNITMODE): Add UNITMODEs for vector types. (addsub): New code iterator. * config/mips/mips.opt (mmsa): New option. * config/mips/msa.h: New file. * config/mips/mti-elf.h: Don't infer -mfpxx if -mmsa is specified. * config/mips/mti-linux.h: Likewise. * config/mips/predicates.md (const_msa_branch_operand): New constraint. (const_uimm3_operand): Likewise. (const_uimm4_operand): Likewise. (const_uimm5_operand): Likewise. (const_uimm8_operand): Likewise. (const_imm5_operand): Likewise. (aq10b_operand): Likewise. (aq10h_operand): Likewise. (aq10w_operand): Likewise. (aq10d_operand): Likewise. (const_m1_operand): Likewise. (reg_or_m1_operand): Likewise. (const_exp_2_operand): Likewise. (const_exp_4_operand): Likewise. (const_exp_8_operand): Likewise. (const_exp_16_operand): Likewise. (const_vector_same_val_operand): Likewise. (const_vector_same_simm5_operand): Likewise. (const_vector_same_uimm5_operand): Likewise. (const_vector_same_uimm6_operand): Likewise. (const_vector_same_uimm8_operand): Likewise. (par_const_vector_shf_set_operand): Likewise. (reg_or_vector_same_val_operand): Likewise. (reg_or_vector_same_simm5_operand): Likewise. (reg_or_vector_same_uimm6_operand): Likewise. * doc/extend.texi (MIPS SIMD Architecture Functions): New section. * doc/invoke.texi (-mmsa): Document new option. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@236030 138bc75d-0d04-0410-961f-82ee72b054a4 | ||||
| * | 2016-05-04 Thomas Preud'homme <thomas.preudhomme@arm.com> | thopre01 | 2016-05-04 | 1 | -25/+27 |
| | | | | | | | | | gcc/ * config.gcc: Error out when conflicting multilib is detected. Do not loop over multilibs since no combination is legal. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@235877 138bc75d-0d04-0410-961f-82ee72b054a4 | ||||
| * | / | olegendo | 2016-04-30 | 1 | -37/+5 |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * config.guess: Remove SH5 support. * config.sub: Likewise. * configure: Likewise. * configure.ac: Likewise. config/ * picflag.m4: Remove SH5 support. gcc/ * config/sh/t-sh: Remove SH5 support. * config.gcc: Likewise. * configure: Likewise. contrib/ * compare-all-tests: Remove SH5 support. * config-list.mk: Likewise. libada/ * configure: Remove SH5 support. libgcc/ * config.host: Remove SH5 support. * configure: Likewise. libiberty/ * configure: Remove SH5 support. libjava/ * classpath/config.guess: Remove SH5 support. * classpath/config.sub: Likewise. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@235676 138bc75d-0d04-0410-961f-82ee72b054a4 | ||||
| * | [Patch AArch64 2/3] Rework the code to print extension strings (pr70133) | jgreenhalgh | 2016-04-11 | 1 | -4/+10 |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | gcc/ PR target/70133 * config/aarch64/aarch64-common.c (aarch64_option_extension): Keep track of a canonical flag name. (all_extensions): Likewise. (arch_to_arch_name): Also track extension flags enabled by the arch. (all_architectures): Likewise. (aarch64_parse_extension): Move to here. (aarch64_get_extension_string_for_isa_flags): Take a new argument, rework. (aarch64_rewrite_selected_cpu): Update for above change. * config/aarch64/aarch64-option-extensions.def: Rework the way flags are handled, such that the single explicit value enabled by an extension is kept seperate from the implicit values it also enables. * config/aarch64/aarch64-protos.h (aarch64_parse_opt_result): Move to here. (aarch64_parse_extension): New. * config/aarch64/aarch64.c (aarch64_parse_opt_result): Move from here to config/aarch64/aarch64-protos.h. (aarch64_parse_extension): Move from here to common/config/aarch64/aarch64-common.c. (aarch64_option_print): Update. (aarch64_declare_function_name): Likewise. (aarch64_start_file): Likewise. * config/aarch64/driver-aarch64.c (arch_extension): Keep track of the canonical flag for extensions. * config.gcc (aarch64*-*-*): Extend regex for capturing extension flags. gcc/testsuite/ PR target/70133 * gcc.target/aarch64/mgeneral-regs_4.c: Fix expected output. * gcc.target/aarch64/target_attr_15.c: Likewise. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@234876 138bc75d-0d04-0410-961f-82ee72b054a4 | ||||
| * | * config.gcc (mep-*-elf): Add newlib-stdint.h to tm_file. | nickc | 2016-03-02 | 1 | -1/+1 |
| | | | | | git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@233900 138bc75d-0d04-0410-961f-82ee72b054a4 | ||||
| * | * MAINTAINERS (mep): Remove myself as MeP maintainer. | dj | 2016-03-02 | 1 | -0/+1 |
| | | | | | | | | * config.gcc: Deprecate mep-*. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@233887 138bc75d-0d04-0410-961f-82ee72b054a4 | ||||
| * | * config.gcc (cr16-*-elf): Add newlib-stdint.h to tm_file. | nickc | 2016-03-01 | 1 | -1/+1 |
| | | | | | git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@233858 138bc75d-0d04-0410-961f-82ee72b054a4 | ||||
| * | 2016-02-26 Joel Sherrill <joel@rtems.org> | joel | 2016-02-26 | 1 | -0/+3 |
| | | | | | | | | | | * config.gcc: Add x86_64-*-rtems*. * gcc/config/i386/rtems-64.h: New file. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@233761 138bc75d-0d04-0410-961f-82ee72b054a4 | ||||
| * | 2016-02-26 Joel Sherrill <joel@rtems.org> | joel | 2016-02-26 | 1 | -2/+9 |
| | | | | | | | | | | * config.gcc: Add aarch64-*-rtems*. * gcc/config/aarch64/rtems.h: New file. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@233760 138bc75d-0d04-0410-961f-82ee72b054a4 | ||||
| * | obsolete the deprecated rtems targets | tbsaunde | 2016-02-05 | 1 | -0/+3 |
| | | | | | | | | | | | gcc/ChangeLog: 2016-02-03 Trevor Saunders <tbsaunde+gcc@tbsaunde.org> * config.gcc: Mark deprecated rtems targets as obsolete. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@233165 138bc75d-0d04-0410-961f-82ee72b054a4 | ||||
| * | [PATCH 5/6] [DJGPP] Update DJGPP configuration related files | andris | 2016-01-12 | 1 | -0/+3 |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * config/i386/djgpp.h (PREFERRED_DEBUGGING_TYPE): Define to DWARF2 (TARGET_ASM_OUTPUT_IDENT): Define to default_asm_output_ident_directive (MD_EXEC_PREFIX): Remove. (MD_STARTFILE_PREFIX) Removee. (FILE_NAME_ABSOLUTE_P): Remove. (CPP_SPEC): Do not read macros from sys/version.h. (LINK_COMMAND_SPEC): Remove. (LOCAL_INCLUDE_DIR): Remove. (TARGET_ASM_NAMED_SECTION): Define to i386_djgpp_asm_named_section (TARGET_OS_CPP_BUILTINS): Add DJGPP (non ISO only), __DJGPP, __DJGPP__, unix. (POST_LINK_SPEC): Define to invoke stubify after linker (LIBSTDCXX): Remove define (DBX_REGISTER_NUMBER): Define to svr4_dbx_register_map. (DEFAULT_PCC_STRUCT_RETURN): Define to 1. (SUBTARGET_OVERRIDE_OPTIONS): Remove warning about -mbnu2210. (SUBTARGET_OVERRIDE_OPTIONS): Ignore -fPIC and generate message. (SUBTARGET_OVERRIDE_OPTIONS): Default to DWARF2 debugging info. (IX86_MAYBE_NO_LIBGCC_TFMODE): Remove. (i386_djgpp_asm_named_section): Add propotype of new procedure * config/i386/xm-djgpp.h (NATIVE_SYSTEM_HEADER_DIR): Define. (MD_EXEC_PREFIX): Define (moved from config/i386/djgpp.h). (STANDARD_STARTFILE_PREFIX_1): Define (moved from MD_STARTFILE_PREFIX in config/i386/djgpp.h). (STANDARD_STARTFILE_PREFIX_2): Define identical to STANDARD_STARTFILE_PREFIX_1. (LOCAL_INCLUDE_DIR): Define (moved from config/i386/djgpp.h). (GCC_DRIVER_HOST_INITIALIZATION): Fix reporting fatal installation errors. (MAX_OFILE_ALIGNMENT): Define to 128. (HAVE_FTW_H): Undefine as DJGPP do not have nftw, but have ftw.h. * config/i386/djgpp.c: New file. Add implementation of i386_djgpp_asm_named_section. * config/i386/djgpp.opt: Remove obsolete option -mbnu210. * config/i386/t-djgpp: New file. Add djgpp.o to EXTRA_OBJS. Add rule for building djgpp.o. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@232258 138bc75d-0d04-0410-961f-82ee72b054a4 | ||||
| * | Update copyright years. | jakub | 2016-01-04 | 1 | -1/+1 |
| | | | | | git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@232055 138bc75d-0d04-0410-961f-82ee72b054a4 | ||||
| * | Introduce support for PKU instructions. | kyukhin | 2015-12-24 | 1 | -2/+4 |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | gcc/ * common/config/i386/i386-common.c (OPTION_MASK_ISA_PKU_SET): New. (OPTION_MASK_ISA_PKU_UNSET): Ditto. (ix86_handle_option): Handle OPT_mpku. * config.gcc: Add pkuintrin.h to i[34567]86-*-* and x86_64-*-* targets. * config/i386/cpuid.h (host_detect_local_cpu): Detect PKU feature. * config/i386/i386-c.c (ix86_target_macros_internal): Handle PKU ISA flag. * config/i386/i386.c (ix86_target_string): Add "-mpku" to ix86_target_opts. (ix86_option_override_internal): Define PTA_PKU, mention new key in skylake-avx512. Handle new ISA bits. (ix86_valid_target_attribute_inner_p): Add "pku". (enum ix86_builtins): Add IX86_BUILTIN_RDPKRU and IX86_BUILTIN_WRPKRU. (builtin_description bdesc_special_args[]): Add new built-ins. * config/i386/i386.h (define TARGET_PKU): New. (define TARGET_PKU_P): Ditto. * config/i386/i386.md (define_c_enum "unspecv"): Add UNSPEC_PKU. (define_expand "rdpkru"): New. (define_insn "*rdpkru"): Ditto. (define_expand "wrpkru"): Ditto. (define_insn "*wrpkru"): Ditto. * config/i386/i386.opt (mpku): Ditto. * config/i386/pkuintrin.h: New file. * config/i386/x86intrin.h: Include pkuintrin.h * doc/extend.texi: Describe new built-ins. * doc/invoke.texi: Describe new switches. gcc/testsuite/ * g++.dg/other/i386-2.C: Add -mpku. * g++.dg/other/i386-3.C: Ditto. * gcc.target/i386/rdpku-1.c: New test. * gcc.target/i386/sse-12.c: Add -mpku. * gcc.target/i386/sse-13.c: Ditto. * gcc.target/i386/sse-22.c: Ditto. * gcc.target/i386/sse-33.c: Ditto. * gcc.target/i386/wrpku-1.c: New test. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@231944 138bc75d-0d04-0410-961f-82ee72b054a4 | ||||
| * | obsolete the interix target | tbsaunde | 2015-12-17 | 1 | -1/+2 |
| | | | | | | | | | | | gcc/ChangeLog: 2015-12-17 Trevor Saunders <tbsaunde+gcc@tbsaunde.org> * config.gcc: mark *-interix* as obsolete. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@231774 138bc75d-0d04-0410-961f-82ee72b054a4 | ||||
| * | obsolete openbsd 2.0 and 3.X | tbsaunde | 2015-12-17 | 1 | -0/+2 |
| | | | | | | | | | | | gcc/ChangeLog: 2015-12-17 Trevor Saunders <tbsaunde+gcc@tbsaunde.org> * config.gcc: Mark openbsd 2.0 and 3.X as obsolete. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@231773 138bc75d-0d04-0410-961f-82ee72b054a4 | ||||
| * | mark *-knetbsd-* as obsolete | tbsaunde | 2015-12-17 | 1 | -2/+1 |
| | | | | | | | | | | | gcc/ChangeLog: 2015-12-17 Trevor Saunders <tbsaunde+gcc@tbsaunde.org> * config.gcc: Mark knetbsd targets as obsolete. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@231772 138bc75d-0d04-0410-961f-82ee72b054a4 | ||||
| * | support for AMD clzero isa. | vekumar | 2015-12-06 | 1 | -2/+2 |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | gcc/ChangeLog 2015-12-06 Victoria Stepanyan <victoria.stepanyan@amd.com> * common/config/i386/i386-common.c (OPTION_MASK_ISA_CLZERO_SET): New. (ix86_handle_option): Handle clzero. * config.gcc (i[34567]86-*-*): Add clzerointrin.h, (x86_64-*-*): Likewise. * config/i386/clzerointrin.h: New header. * config/i386/cpuid.h (bit_CLZERO): Define. * config/i386/driver-i386.c (host_detect_local_cpu): Detect CLZERO support. * config/i386/i386.opt (clzero): New. * config/i386/i386-c.c: Define __CLZERO__ if needed. * config/i386/i386.c (ix86_target_string): Define -mclzero option. (PTA_CLZERO): New. (ix86_option_override_internal): Handle new option. (processor_alias_table): Added PTA_CLZERO. (ix86_valid_target_attribute_inner_p): Add OPT_mclzero. (ix86_builtins): Add IX86_BUILTIN_CLZERO, IX86_BUILTIN_CLZERO. (ix86_expand_builtin): Handle IX86_BUILTIN_CLZERO and IX86_BUILTIN_CLZERO built-ins. * config/i386/i386.h (TARGET_CLZERO): New. * config/i386/i386.md (unspecv): Add UNSPEC_CLZERO. (clzero): New pattern. (clzero_<mode>): New pattern. * config/i386/x86intrin.h: Include clzerointrin.h. * doc/extend.texi: Document clzero builtins. * doc/invoke.texi: Document -mclzero option. gcc/testsuite/ChangeLog 2015-12-06 Victoria Stepanyan <victoria.stepanyan@amd.com> * gcc.target/i386/clzero.c: New. * gcc.target/i386/sse-12.c: Add -mclzero. * gcc.target/i386/sse-13.c: Ditto. * gcc.target/i386/sse-14.c: Ditto. * gcc.target/i386/sse-22.c: Ditto. * gcc.target/i386/sse-23.c: Ditto. * g++.dg/other/i386-2.C: Ditto. * g++.dg/other/i386-3.C: Ditto. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@231340 138bc75d-0d04-0410-961f-82ee72b054a4 | ||||
| * | gcc * config.gcc (extra_gcc_objs): Define for MSP430. | nickc | 2015-12-04 | 1 | -0/+1 |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * common/config/msp430/msp430-common.c (msp430_handle_option): Pass both -mmcu and -mcpu on to the back end if they are both defined. * config/msp430/msp430.c (hwmult_name): New function. (msp430_option_override): If an unrecognised MCU name is detected only warn if the user has not provided suitable -mhwmult and -mcpu options. Use msp430_warn_mcu to control warning messages. Generate warnings about conflicts between -mmcu and -mcpu and -mhwmult options. If neither -mcpu nor -mmcu have been specified but -mhwmult= f5series has the select the 430X isa. (msp430_no_hwmult): If -mmcu has not been specified and msp430_hwmult_type is AUTO then return true. * config/msp430/msp430.h (EXTRA_SPEC_FUNCTIONS): Define. (LIB_SPEC): Add hardware multiply library selection. * config/msp430/t-msp430: Delete hardware multiply multilibs. Add rule to build driver-msp430.o * config/msp430/driver-msp430.c: New file. * config/msp430/msp430.opt (warn-mcu): New option. * doc/invoke.texi: Update description of -mhwmult=auto. Document -mwarn-mcu option. tests * gcc.target/msp430/msp_abi_div_funcs.c: New test. * gcc.target/msp430/mul_main.h: New test support file. * gcc.target/msp430/mul_none.c: New test. * gcc.target/msp430/mul_16bit.c: New test. * gcc.target/msp430/mul_32bit.c: New test. * gcc.target/msp430/mul_f5.c: New test. libgcc * config/msp430/mpy.c (__mulhi3): Use a faster algorithm. Allow for the second argument being negative. * config.host (extra_parts): Define for MSP430. Create separate libraries for each of the hardware multiply formats. * config/msp430/lib2hw_mul.S: Build only the multiply routines that are needed. * config/msp430/lib2mul.c: Likewise. * config/msp430/t-msp430 (LIB2ADD): Remove lib2hw_mul.S. Add rules to build hardware multiply libraries. * config/msp430/lib2divSI.c: (__mspabi_divlu): Alias for __mspabi_divul function. (__mspabi_divllu): New stub function. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@231286 138bc75d-0d04-0410-961f-82ee72b054a4 | ||||
| * | 2015-11-10 Michael Meissner <meissner@linux.vnet.ibm.com> | meissner | 2015-11-10 | 1 | -2/+2 |
| | | | | | | | | | | * config.gcc (powerpc*-*-*, rs6000*-*-*): Add power9 to hosts that default to 64-bit. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@230123 138bc75d-0d04-0410-961f-82ee72b054a4 | ||||
| * | 2015-11-06 Arnout Vandecappelle <arnout@mind.be> | dje | 2015-11-06 | 1 | -1/+1 |
| | | | | | | | | * config.gcc (e6500): Fix cpu_is_64bit typo. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@229855 138bc75d-0d04-0410-961f-82ee72b054a4 | ||||
| * | gcc/ChangeLog | olegendo | 2015-10-27 | 1 | -0/+3 |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * config.gcc: Handle --enable-fdpic. * config/sh/constraints.md (Ccl): New constraint. * config/sh/linux.h (SUBTARGET_LINK_EMUL_SUFFIX): Handle -mfdpic. * config/sh/sh-c.c (sh_cpu_cpp_builtins): Add __FDPIC__ and __SH_FDPIC__. * config/sh/sh-mem.cc (expand_block_move): Support FDPIC for calls to library functions. * config/sh/sh-protos.h (function_symbol_result): New struct. (function_symbol): Return function_symbol_result. (sh_get_fdpic_reg_initial_val, sh_load_function_descriptor): New declarations. * config/sh/sh.c (TARGET_ASM_INTEGER, sh_assemble_integer): Implement target hook. (TARGET_CANNOT_FORCE_CONST_MEM, sh_cannot_force_const_mem_p): Likewise. (sh_option_override): Force -fPIC if FDPIC is in effect. (sh_asm_output_addr_const_extra): Add UNSPEC_GOTFUNCDESC and UNSPEC_GOTOFFFUNCDESC cases. (prepare_move_operands): Use FDPIC initial GOT register for TLS-related GOT access; inhibit cross-section address offset constants for FDPIC. (sh_assemble_integer): New function. (sh_cannot_copy_insn_p): Inhibit copying insns that are FDPIC PC-relative call sites. (expand_ashiftrt): Adapt invocation of function_symbol. (sh_expand_prologue): Inhibit PC-relative GOT address load for FDPIC. (nonpic_symbol_mentioned_p): Add cases for UNSPEC_GOTFUNCDESC and UNSPEC_GOTOFFFUNCDESC. (legitimize_pic_address): Resolve function symbols to function descriptors for FDPIC. Do not use GOT-relative addressing for local data that may be read-only on FDPIC. (sh_emit_storesi, sh_emit_storehi): New functions. (sh_trampoline_init): Generate FDPIC trampolines. (sh_function_ok_for_sibcall): Add TARGET_FDPIC check. (sh_expand_sym_label2reg): Don't assume sibcalls are local. (sh_output_mi_thunk): Generate FDPIC call. (function_symbol): Return function_symbol_result. For SFUNC_STATIC on FDPIC, generate call site labels to use PC-relative addressing rather than GOT-relative addressing. (sh_conditional_register_usage): Make PIC register fixed and call used when FDPIC is in effect. (sh_legitimate_constant_p): Impose FDPIC constant constraints. (sh_cannot_force_const_mem_p, sh_load_function_descriptor, sh_get_fdpic_reg_initial_val): New functions. * config/sh/sh.h (SUBTARGET_ASM_SPEC, SUBTARGET_LINK_EMUL_SUFFIX): Handle -mfdpic. (FDPIC_SELF_SPECS, SUBTARGET_DRIVER_SELF_SPECS, PIC_OFFSET_TABLE_REG_CALL_CLOBBERED, SH_OFFSETS_MUST_BE_WITHIN_SECTIONS_P): New macros. (DRIVER_SELF_SPECS): Add SUBTARGET_DRIVER_SELF_SPECS and FDPIC_SELF_SPECS. (TRAMPOLINE_SIZE): Select trampoline size for FDPIC. (ASM_PREFERRED_EH_DATA_FORMAT): Add EH format constraints for FDPIC. (ASM_MAYBE_OUTPUT_ENCODED_ADDR_RTX): Handle FDPIC case. * config/sh/sh.md (UNSPEC_GOTFUNCDESC, UNSPEC_GOTOFFFUNCDESC): New constants. (calli_fdpic, call_valuei_fdpic, sibcalli_fdpic, sibcalli_pcrel_fdpic, sibcall_pcrel_fdpic, sibcall_valuei_fdpic, sibcall_valuei_pcrel_fdpic, sibcall_value_pcrel_fdpic, sym2GOTFUNCDESC, symGOTFUNCDESC2reg, sym2GOTOFFFUNCDESC, symGOTOFFFUNCDESC2reg): New patterns. (udivsi3_i1, udivsi3_i4, udivsi3_i4_single, udivsi3, *divsi_inv_call_combine, divsi3_i4, divsi3_i4_single, divsi3, ashlsi3, ashlsi3_d_call, ashrsi3_n, lshrsi3, lshrsi3_d_call, calli, call_valuei, call, call_value, sibcalli, sibcalli_pcrel, sibcall_pcrel, sibcall, sibcall_valuei, sibcall_valuei_pcrel, sibcall_value_pcrel, sibcall_value, GOTaddr2picreg, symGOT_load, symGOTOFF2reg, block_move_real, block_lump_real, block_move_real_i4, block_lump_real_i4): Add support for FDPIC calls. (mulsi3, ic_invalidate_line, initialize_trampoline, call_pop, call_value_pop): Adjust for new function_symbol signature. * config/sh/sh.opt (-mfdpic): New option. * doc/install.texi (Options specification): Document --enable-fdpic. * doc/invoke.texi (SH Options): Document -mfdpic. include/ChangeLog: * longlong.h (udiv_qrnnd): Add FDPIC compatible version for SH. libitm/ChangeLog: * config/sh/sjlj.S (_ITM_beginTransaction): Bypass PLT calling GTM_begin_transaction for compatibility with FDPIC. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@229438 138bc75d-0d04-0410-961f-82ee72b054a4 | ||||
| * | * config.gcc (powerpc-ibm-aix[6789]) [default_use_cxa_atexit]: | dje | 2015-10-23 | 1 | -0/+2 |
| | | | | | | | | Define as yes. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@229276 138bc75d-0d04-0410-961f-82ee72b054a4 | ||||
| * | [rs6000] Enable secureplt by default on musl | nsz | 2015-10-23 | 1 | -0/+4 |
| | | | | | | | | | * config.gcc (enable_secureplt): Add *-linux*-musl*. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@229268 138bc75d-0d04-0410-961f-82ee72b054a4 | ||||
| * | [AArch64] --with-arch in config.gcc support "." | jiwang | 2015-10-15 | 1 | -1/+1 |
| | | | | | | | | | * config.gcc: Recognize "." in architecture base name for AArch64. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@228837 138bc75d-0d04-0410-961f-82ee72b054a4 | ||||
| * | 2015-10-05 Steve Ellcey <sellcey@imgtec.com> | sje | 2015-10-09 | 1 | -0/+1 |
| | | | | | | | | | | | | | | | | | | | | | | | * config.gcc (mips*-*-*): Add frame-header-opt.o to extra_objs. * frame-header-opt.c: New file. * config/mips/mips-proto.h (mips_register_frame_header_opt): Add prototype. * config/mips/mips.c (mips_compute_frame_info): Check optimize_call_stack flag. (mips_option_override): Register new frame_header_opt pass. (mips_frame_info, mips_int_mask, mips_shadow_set, machine_function): Move these types to... * config/mips/mips.h: here. (machine_function): Add does_not_use_frame_header and optimize_call_stack fields. * config/mips/t-mips (frame-header-opt.o): Add new make rule. * doc/invoke.texi (-mframe-header-opt, -mno-frame-header-opt): Document new flags. * config/mips/mips.opt (mframe-header-opt): Add new option. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@228666 138bc75d-0d04-0410-961f-82ee72b054a4 | ||||
| * | * config.gcc (lm32-elf): Add newlib-stdint.h to tm_file. | nickc | 2015-10-06 | 1 | -1/+1 |
| | | | | | git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@228533 138bc75d-0d04-0410-961f-82ee72b054a4 | ||||
| * | 2015-10-06 Venkataramanan Kumar <Venkataramanan.kumar@amd.com> | vekumar | 2015-10-06 | 1 | -1/+9 |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | AMD znver1 enablement. * config.gcc (i[34567]86-*-linux* | ...): Add znver1. (case ${target}): Add znver1. * config/i386/cpuid.h(bit_CLZERO): Define. * config/i386/driver-i386.c: (host_detect_local_cpu): Let -march=native recognize znver1 processors. * config/i386/i386-c.c (ix86_target_macros_internal): Add znver1, clzero def_and_undef. * config/i386/i386.c (struct processor_costs znver1_cost): New. (m_znver1): New definition. (m_AMD_MULTIPLE): Includes m_znver1. (processor_target_table): Add znver1 entry. (ix86_target_string) : Add clzero entry. (static const char *const cpu_names): Add znver1 entry. (ix86_option_override_internal): Add znver1 instruction sets. (PTA_CLZERO) : New definition. (ix86_option_override_internal): Handle new clzerooption. (ix86_issue_rate): Add znver1. (ix86_adjust_cost): Add znver1. (ia32_multipass_dfa_lookahead): Add znver1. (has_dispatch): Add znver1. * config/i386/i386.h (TARGET_znver1): New definition. (TARGET_CLZERO): Define. (TARGET_CLZERO_P): Define. (struct ix86_size_cost): Add TARGET_ZNVER1. (enum processor_type): Add PROCESSOR_znver1. * config/i386/i386.md (define_attr "cpu"): Add znver1. (set_attr znver1_decode): New definitions for znver1. * config/i386/i386.opt (flag_dispatch_scheduler): Add znver1. (mclzero): New. * config/i386/mmx.md (set_attr znver1_decode): New definitions for znver1. * config/i386/sse.md (set_attr znver1_decode): Likewise. * config/i386/x86-tune.def: Add znver1 tunings. * config/i386/znver1.md: Introduce znver1 cpu and include new md file. * gcc/doc/invoke.texi: Add details about znver1 git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@228520 138bc75d-0d04-0410-961f-82ee72b054a4 | ||||
| * | xtensa: add uclinux support | jcmvbkbc | 2015-10-03 | 1 | -0/+5 |
| | | | | | | | | | | | | | | | | 2015-10-03 Max Filippov <jcmvbkbc@gmail.com> gcc/ * config.gcc (xtensa*-*-uclinux*): New configuration. * config/xtensa/uclinux.h: New file. * config/xtensa/uclinux.opt: New file. libgcc/ * config.host (xtensa*-*-uclinux*): New configuration. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@228450 138bc75d-0d04-0410-961f-82ee72b054a4 | ||||
| * | * dwarf2out.c (XCOFF_DEBUGGING_INFO): Default 0 definition. | dje | 2015-09-26 | 1 | -1/+10 |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | (HAVE_XCOFF_DWARF_EXTRAS): Default to 0 definition. (output_fde): Don't output length for debug_frame on AIX. (output_call_frame_info): Don't output length for debug_frame on AIX. (have_macinfo): Force to False for XCOFF_DEBUGGING_INFO and not HAVE_XCOFF_DWARF_EXTRAS. (add_AT_loc_list): Return early if XCOFF_DEBUGGING_INFO and not HAVE_XCOFF_DWARF_EXTRAS. (output_compilation_unit_header): Don't output length on AIX. (output_pubnames): Don't output length on AIX. (output_aranges): Delete argument. Compute length locally. Don't output length on AIX. (output_line_info): Don't output length on AIX. (dwarf2out_finish): Don't compute aranges_length. * dwarf2asm.c (XCOFF_DEBUGGING_INFO): Default 0 definition. (dw2_asm_output_nstring): Emit .byte not .ascii on AIX. * config/rs6000/rs6000.c (rs6000_output_dwarf_dtprel): Emit correct symbol decoration for AIX. (rs6000_xcoff_debug_unwind_info): New. (rs6000_xcoff_asm_named_section): Emit .dwsect pseudo-op for SECTION_DEBUG. (rs6000_xcoff_declare_function_name): Emit different .function pseudo-op when DWARF2_DEBUG. Don't call xcoffout_declare_function for DWARF2_DEBUG. * config/rs6000/xcoff.h (TARGET_DEBUG_UNWIND_INFO): Redefine. * config/rs6000/aix71.h: New. * configure.ac (gcc_cv_as_aix_dwloc): Check AIX as for DWARF locations support. * configure: Regenerate. * config.gcc (powerpc-ibm-aix[789]+): New stanza for AIX 7.1+ with DWARF support. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@228167 138bc75d-0d04-0410-961f-82ee72b054a4 | ||||
| * | Rename IA MCU processor lakemount to lakemont | hjl | 2015-09-25 | 1 | -3/+3 |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | IA MCU processor name is lakemont, not lakemount. gcc/ * config.gcc (x86_archs): Replace lakemount with lakemont. (with_cpu): Likewise. (with_arch): Likewise. * config/i386/i386-c.c (ix86_target_macros_internal): Replace PROCESSOR_LAKEMOUNT with PROCESSOR_LAKEMONT. Replace __tune_lakemount__ with __tune_lakemont__. * config/i386/i386.c (lakemount_cost): Renamed to ... (lakemont_cost): This. (m_LAKEMOUNT): Renamed to ... (m_LAKEMONT): This. (initial_ix86_arch_features): Replace m_LAKEMOUNT with m_LAKEMONT. (processor_target_table): Replace "lakemount" with "lakemont". (processor_alias_table): Likewise. (ix86_issue_rate): Replace PROCESSOR_LAKEMOUNT with PROCESSOR_LAKEMONT. (ix86_adjust_cost): Likewise. (ia32_multipass_dfa_lookahead): Likewise. * config/i386/i386.h (processor_type): Likewise. * config/i386/x86-tune.def: Replace m_LAKEMOUNT with m_LAKEMONT. * doc/invoke.texi: Replace lakemount with lakemont. Replace Lakemount with Lakemont. gcc/testsuite/ * gcc.target/i386/pr66749.c (dg-options): Replace -mtune=lakemount with -mtune=lakemont. * gcc.target/i386/pr66821.c (dg-options): Likewise. * gcc.target/i386/pr67329.c (dg-options): Likewise. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@228115 138bc75d-0d04-0410-961f-82ee72b054a4 | ||||
| * | Change IA MCU processor from iamcu to lakemount | hjl | 2015-09-25 | 1 | -3/+3 |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The first IA MCU processor will be Lakemount. This patch changes IA MCU processor name from iamcu to lakemount. gcc/ * config.gcc (x86_archs): Replace iamcu with lakemount. (with_cpu): Likewise. (with_arch): Likewise. * doc/invoke.texi: Likewise. * config/i386/i386-c.c (ix86_target_macros_internal): Replace PROCESSOR_IAMCU with PROCESSOR_LAKEMOUNT. Replace __tune_iamcu__ with __tune_lakemount__. * config/i386/i386.c (iamcu_cost): Renamed to ... (lakemount_cost): This. (m_IAMCU): Renamed to ... (m_LAKEMOUNT): This. (initial_ix86_arch_features): Replace m_IAMCU with m_LAKEMOUNT. (processor_target_table): Replace "iamcu" with "lakemount". (processor_alias_table): Likewise. (ix86_issue_rate): Replace PROCESSOR_IAMCU with PROCESSOR_LAKEMOUNT. (ix86_adjust_cost): Likewise. (ia32_multipass_dfa_lookahead): Likewise. * config/i386/i386.h (processor_type): Likewise. * config/i386/x86-tune.def: Replace m_IAMCU with m_LAKEMOUNT. gcc/testsuite/ * gcc.target/i386/pr66749.c (dg-options): Replace -mtune=iamcu with -mtune=lakemount. * gcc.target/i386/pr66821.c (dg-options): Likewise. * gcc.target/i386/pr67329.c (dg-options): Likewise. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@228109 138bc75d-0d04-0410-961f-82ee72b054a4 | ||||
| * | AVX-512. Introduce SKylake server CPU. | kyukhin | 2015-09-22 | 1 | -2/+2 |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | gcc/ * config.gcc: Support "skylake-avx512". * config/i386/i386-c.c (ix86_target_macros_internal): Handle PROCESSOR_SKYLAKE_AVX512. * config/i386/i386.c (m_SKYLAKE_AVX512): Define. (processor_target_table): Add "skylake-avx512". (PTA_SKYLAKE_AVX512): Define. (ix86_option_override_internal): Add "skylake_avx512". (fold_builtin_cpu): Handle "skylake_avx512", add F_AVX512VL F_AVX512BW, F_AVX512DQ, F_AVX512ER, F_AVX512PF, F_AVX512CD. * config/i386/i386.h (TARGET_SKYLAKE_AVX512): Define. (processor_type): Add PROCESSOR_SKYLAKE_AVX512. * doc/invoke.texi (skylake-avx512): New. libgcc/ * libgcc/config/i386/cpuinfo.c (enum processor_features): Add FEATURE_AVX512VL, FEATURE_AVX512BW, FEATURE_AVX512DQ, FEATURE_AVX512CD, FEATURE_AVX512ER, FEATURE_AVX512PF. (get_available_features): Habdle new features. gcc/testsuite/ * gcc.target/i386/funcspec-5.c: Test avx512vl, avx512bw, avx512dq, avx512cd, avx512er, avx512pf and skylake-avx512. * gcc.target/i386/builtin_target.c: Test avx512vl, avx512bw, avx512dq, avx512cd, avx512er and avx512pf. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@228009 138bc75d-0d04-0410-961f-82ee72b054a4 | ||||
| * | * config.gcc (visium-*-*): Enable --with-cpu option, accept gr5 and | ebotcazou | 2015-09-13 | 1 | -0/+16 |
| | | | | | | | | | | | | | | | gr6 as possible values, defaulting to gr5. Set target_cpu_default2. * config/visium/visium.h (OPTION_DEFAULT_SPECS): Define. (TARGET_CPU_gr5): Likewise. (TARGET_CPU_gr6): Likewise. (MULTILIB_DEFAULTS): Likewise. * config/visium/t-visium (MULTILIB_OPTIONS): Request distinct variants for mcpu=gr5 and mcpu=gr6. (MULTILIB_DIRNAMES): Adjust accordingly. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@227728 138bc75d-0d04-0410-961f-82ee72b054a4 | ||||
| * | * [SH] config.gcc (supported_defaults): Handle sh[123456ble]*-*-* instead of ↵ | kkojima | 2015-08-31 | 1 | -1/+1 |
| | | | | | | | sh[123456ble]-*-*. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@227330 138bc75d-0d04-0410-961f-82ee72b054a4 | ||||
| * | Use __cxa_atexit on Solaris 12+ | ro | 2015-08-27 | 1 | -0/+6 |
| | | | | | | | | * config.gcc (*-*-solaris2*): Enable default_use_cxa_atexit on Solaris 12+. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@227255 138bc75d-0d04-0410-961f-82ee72b054a4 | ||||
| * | [AArch64][10/14] Implement target pragmas | ktkachov | 2015-08-04 | 1 | -0/+2 |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * config.gcc (aarch64*-*-*): Specify c_target_objs and cxx_target_objs. * config/aarch64/aarch64.h (REGISTER_TARGET_PRAGMAS): Define. (TARGET_CPU_CPP_BUILTINS): Redefine to call aarch64_cpu_cpp_builtins. * config/aarch64/aarch64.c (aarch64_override_options_internal): Remove static keyword. (aarch64_reset_previous_fndecl): New function. (aarch64_handle_attr_isa_flags): Handle "+nothing" in the beginning of the string. * config/aarch64/aarch64-c.c: New file. * config/aarch64/arm_acle.h: Add pragma +crc+nofp at the top. Push and pop options at beginning and end. Remove ifdef __ARM_FEATURE_CRC32. * config/aarch64/arm_neon.h: Remove #ifdef check on __ARM_NEON. Add pragma +nothing+simd and +nothing+crypto where appropriate. * config/aarch64/t-aarch64 (aarch64-c.o): New rule. * config/aarch64/aarch64-protos.h (aarch64_cpu_cpp_builtins): Define prototype. (aarch64_register_pragmas): Likewise. (aarch64_reset_previous_fndecl): Likewise. (aarch64_process_target_attr): Likewise. (aarch64_override_options_internal): Likewise. * gcc.target/aarch64/arm_neon-nosimd-error.c: Delete. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@226563 138bc75d-0d04-0410-961f-82ee72b054a4 | ||||
| * | 2015-07-14 Sandra Loosemore <sandra@codesourcery.com> | sandra | 2015-07-14 | 1 | -0/+13 |
| | | | | | | | | | | | | | | | | | | | | | | | | Cesar Philippidis <cesar@codesourcery.com> Chung-Lin Tang <cltang@codesourcery.com> gcc/ * config/nios2/nios2.opt (march, mbmx, mcdx): New options. * config/nios2/nios2-opts.h (enum nios2_arch_type): New enum for Nios II architecture level. * config/nios2/nios2.h (TARGET_ARCH_R2): New define. (TARGET_CPU_CPP_BUILTINS): Add definition of __nios2_arch__ symbol. (OPTION_DEFAULT_SPECS): Define. (ASM_SPEC): Add -march= spec strings. * config/nios2/nios2.c (nios2_option_override): Check for conflicts involving new options. * config.gcc (nios2*-*-*): Support --with-arch=. * doc/invoke.texi (Option Summary, Nios II Options): Document -march=, -mbmx, and -mcdx. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@225791 138bc75d-0d04-0410-961f-82ee72b054a4 | ||||
| * | 2015-07-06 Steve Ellcey <sellcey@imgtec.com> | sje | 2015-07-06 | 1 | -1/+1 |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * config.gcc <mips*-*-*>: Add fused-madd.opt. * config/mips/mips.opt (mfused-madd): Remove. * config/mips/mips.c (mips_rtx_costs): Update cost calculations. * config/mips/mips.h (TARGET_MIPS8000): New. (ISA_HAS_FP_MADD4_MSUB4): Remove. (ISA_HAS_FP_MADDF_MSUBF): Remove. (ISA_HAS_FP_MADD3_MSUB3): Remove. (ISA_HAS_NMADD4_NMSUB4): Remove. (ISA_HAS_NMADD3_NMSUB3): Remove. (ISA_HAS_FUSED_MADD4): New. (ISA_HAS_UNFUSED_MADD4): New. (ISA_HAS_FUSED_MADDF): New. (ISA_HAS_FUSED_MADD3): New. * config/mips/mips.md: (fma<mode>4) Change from insn to expand. (*fma<mode>4_madd3) New. (*fma<mode>4_madd4) New. (*fma<mode>4_maddf) New. (fms<mode>4) New. (*fms<mode>4_msub3) New. (*fms<mode>4_msub4) New. (fnma<mode>4) New. (*fnma<mode>4_nmadd3) New. (*fnma<mode>4_nmadd4) New. (fnms<mode>4) New. (*fnms<mode>4_nmsub3) New. (*fnms<mode>4_nmsub4) New. (*madd4<mode>) Modify to be unfused only. (*msub4<mode>) Modify to be unfused only. (*nmadd4<mode>) Modify to be unfused only. (*nmsub4<mode>) Modify to be unfused only. (*madd3<mode>) Remove. (*msub3<mode>) Remove. (*nmadd3<mode>) Remove. (*nmsub3<mode>) Remove. (*nmadd3<mode>_fastmath) Remove. (*nmsub3<mode>_fastmath) Remove. (*nmadd4<mode>_fastmath) Update condition. (*nmsub4<mode>_fastmath) Update condition. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@225468 138bc75d-0d04-0410-961f-82ee72b054a4 | ||||
| * | Optimize i?86-*-elfiamcu for iamcu by default | hjl | 2015-07-06 | 1 | -1/+7 |
| | | | | | | | | | | | | | Default -mtune=/-march= to iamcu for i[34567]86-*-elfiamcu targets. * config.gcc (x86_archs): Add iamcu. (with_cpu): Default to iamcu for i[34567]86-*-elfiamcu. (with_arch): Likewise. * doc/invoke.texi: Add iamcu. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@225464 138bc75d-0d04-0410-961f-82ee72b054a4 | ||||
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index : delta/gcc.git | |
| gcc.gnu.org: git/gcc.git |
| summaryrefslogtreecommitdiff |