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* Support Intel AVX-NE-CONVERTkonglin12022-10-314-1/+25
* RISC-V: Minimal support of z*inx extension.Jiawei2022-10-271-0/+18
* i386: add reset_cpu_featureMartin Liska2022-10-261-5/+33
* RISC-V: Recognized Svinval and Svnapot extensionsMonk Chiang2022-10-261-0/+6
* RISC-V: Add h extension supportKito Cheng2022-10-261-15/+8
* Remove znver4 instruction reservationsTejas Joshi2022-10-251-1/+1
* riscv: fix cross compilerMartin Liska2022-10-251-4/+4
* i386: fix pedantic warningMartin Liska2022-10-251-1/+1
* x86: fix VENDOR_MAX enum valueMartin Liska2022-10-241-1/+3
* RISC-V: Support --target-help for -mcpu/-mtuneKito Cheng2022-10-241-0/+46
* Enable AMD znver4 support and add instruction reservationsTejas Joshi2022-10-213-28/+24
* Support Intel AVX-VNNI-INT8Kong Lingling2022-10-214-1/+26
* Support Intel AVX-IFMAHongyu Wang2022-10-214-1/+23
* Enable REE for H8Jeff Law2022-10-171-0/+2
* Initial Meteorlake SupportHu, Lin12022-10-172-0/+6
* Initial Raptorlake SupportHaochen Jiang2022-10-172-0/+4
* arc: Remove obsolete mRcq and mRcw options.Claudiu Zissulescu2022-10-101-2/+0
* aarch64: Tweak handling of -mgeneral-regs-onlyRichard Sandiford2022-09-291-0/+12
* aarch64: Tweak contents of flags_on/off fieldsRichard Sandiford2022-09-291-8/+6
* aarch64: Make more use of aarch64_feature_flagsRichard Sandiford2022-09-291-9/+10
* aarch64: Tweak constness of option-related dataRichard Sandiford2022-09-291-13/+13
* aarch64: Avoid std::string in static dataRichard Sandiford2022-09-291-2/+2
* aarch64: Simplify generation of .arch stringsRichard Sandiford2022-09-291-196/+47
* aarch64: Simplify feature definitionsRichard Sandiford2022-09-291-11/+18
* aarch64: Avoid redundancy in aarch64-cores.defRichard Sandiford2022-09-291-1/+1
* aarch64: Add "V" to aarch64-arches.def namesRichard Sandiford2022-09-291-1/+1
* aarch64: Rename AARCH64_FL_FOR_ARCH macrosRichard Sandiford2022-09-291-1/+1
* aarch64: Rename AARCH64_ISA architecture-level macrosRichard Sandiford2022-09-291-1/+1
* RISC-V: Support poly move manipulation and selftests.zhongjuzhe2022-09-231-1/+1
* RISC-V: Suppress build warningsKito Cheng2022-09-091-18/+18
* RISC-V: Support Zmmul extensionLiaoShihua2022-09-051-0/+4
* RISC-V: Implement TARGET_COMPUTE_MULTILIBKito Cheng2022-09-021-0/+377
* Add TARGET_COMPUTE_MULTILIB hook to override multi-lib result.Kito Cheng2022-09-023-0/+51
* s390: Add -munroll-only-small-loops.Robin Dapp2022-08-291-0/+5
* cr16: remove obsoleted portMartin Liska2022-08-261-27/+0
* RISC-V: Support zfh and zfhmin extensionKito Cheng2022-08-161-0/+8
* xtensa: Turn on -fsplit-wide-types-early by defaultTakayuki 'January June' Suwa2022-08-151-0/+2
* LoongArch: Support split symbol.Lulu Cheng2022-07-261-0/+1
* loongarch: use -mno-check-zero-division as the default for optimized codeXi Ruoyao2022-07-031-3/+0
* i386: Add AVX512BW to AVX512F in MASK_ISA2Haochen Jiang2022-07-011-3/+2
* Remove long deprecated tilegx and tilepro portsJeff Law2022-06-252-112/+0
* x86: Require AVX for F16C and VAESH.J. Lu2022-06-131-4/+4
* RISC-V: Add mininal support for Zicbo[mzp]ShiYulong2022-05-241-0/+8
* [x86_64]: Zhaoxin lujiazui enablementMayshao2022-05-233-1/+64
* RISC-V: Fix canonical extension order (K and J)Tsukasa OI2022-05-231-1/+1
* Use more ARRAY_SIZE.Martin Liska2022-05-161-2/+1
* i386: simplify cpu_feature handlingMartin Liska2022-05-111-22/+28
* IBM zSystems: Add support for z16 as CPU name.Andreas Krebbel2022-04-121-2/+2
* LoongArch Port: gcc buildchenglulu2022-03-291-0/+43
* x86: Disable SSE in ISA2 for -mgeneral-regs-onlyH.J. Lu2022-03-211-1/+1
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