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* Backported from mainlinejakub2017-12-151-3/+7
| | | | | | | | | | | | | | | 2017-11-25 Jakub Jelinek <jakub@redhat.com> PR rtl-optimization/81553 * combine.c (simplify_if_then_else): In (if_then_else COND (OP Z C1) Z) to (OP Z (mult COND (C1 * STORE_FLAG_VALUE))) optimization, if OP is a shift where C1 has different mode than the whole shift, use C1's mode for MULT rather than the shift's mode. * gcc.c-torture/compile/pr81553.c: New test. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/branches/gcc-7-branch@255717 138bc75d-0d04-0410-961f-82ee72b054a4
* combine: Don't split insns if half is unused (PR82621)segher2017-11-241-1/+2
| | | | | | | | | | | | | | | | | | | | | | | If we have a PARALLEL of two SETs, and one half is unused, we currently happily split that into two instructions (albeit the unused one is useless). Worse, as PR82621 shows, combine will happily merge this insn into I3 even if some intervening insn sets the same register again, which is wrong. This fixes it by not splitting PARALLELs with REG_UNUSED notes. It all is handled fine by combine in that case; just the "single set that is unused" case isn't handled properly. This also results in better code: combine will now actually throw away the unused SET. (It still won't do that in an I3). PR rtl-optimization/82621 * combine.c (try_combine): Do not split PARALLELs of two SETs if the dest of one of those SETs is unused. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/branches/gcc-7-branch@255142 138bc75d-0d04-0410-961f-82ee72b054a4
* Backport from mainlinesegher2017-11-091-5/+11
| | | | | | | | | | | | | | | 2017-11-01 Segher Boessenkool <segher@kernel.crashing.org> PR rtl-optimization/64682 PR rtl-optimization/69567 PR rtl-optimization/69737 PR rtl-optimization/82683 * combine.c (distribute_notes) <REG_DEAD>: If the new I2 sets the same register mentioned in the note, drop the note, unless it came from I3, in which case it should go to I3 again. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/branches/gcc-7-branch@254564 138bc75d-0d04-0410-961f-82ee72b054a4
* Backported from mainlinejakub2017-10-271-2/+14
| | | | | | | | | | | | | | 2017-09-15 Jakub Jelinek <jakub@redhat.com> PR rtl-optimization/82192 * combine.c (make_extraction): Don't look through non-paradoxical SUBREGs or TRUNCATE if pos + len is or might be bigger than inner's mode. * gcc.c-torture/execute/pr82192.c: New test. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/branches/gcc-7-branch@254177 138bc75d-0d04-0410-961f-82ee72b054a4
* PR rtl-optimization/80501jakub2017-04-251-2/+5
| | | | | | | | | | * combine.c (make_compound_operation_int): Set subreg_code to SET even for AND with mask of the sign bit of mode. * gcc.c-torture/execute/pr80501.c: New test. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/branches/gcc-7-branch@247129 138bc75d-0d04-0410-961f-82ee72b054a4
* combine: Fix PR80233segher2017-03-291-2/+2
| | | | | | | | | | | | | | | | | | | | | | If combine has added an unconditional trap there will be a new basic block as well. It will then end up considering the NOTE_INSN_BASIC_BLOCK as the last_combined_insn, but then it tries to take the DF_INSN_LUID of that and that dereferences a NULL pointer (since such a note is not an INSN_P). This fixes it by not taking non-insns as last_combined_insn. PR rtl-optimization/80233 * combine.c (combine_instructions): Only take NONDEBUG_INSN_P insns as last_combined_insn. Do not test for BARRIER_P separately. gcc/testsuite/ PR rtl-optimization/80233 * gcc.c-torture/compile/pr80233.c: New testcase. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@246575 138bc75d-0d04-0410-961f-82ee72b054a4
* PR target/80125jakub2017-03-211-5/+10
| | | | | | | | | | | | * combine.c (can_combine_p): Revert the 2017-03-20 change, only check reg_used_between_p between insn and one of succ or succ2 depending on if succ is artificial insn not inserted into insn stream. * gcc.target/powerpc/pr80125.c: New test. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@246323 138bc75d-0d04-0410-961f-82ee72b054a4
* combine: Fix 79910segher2017-03-201-0/+4
| | | | | | | | | | | | | | | | If the dest of an I0 or I1 is used in an insn before I2, as can happen in various uncommon cases, and we manage to do the combination, the set is moved to I2, which is wrong. Don't allow combining the insns in this case. PR rtl-optimization/79910 * combine.c (can_combine_p): Do not allow combining an I0 or I1 if its dest is used by an insn before I2 (other than the combined insns themselves, which are properly handled already). git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@246297 138bc75d-0d04-0410-961f-82ee72b054a4
* Revert:segher2017-03-201-137/+0
| | | | | | | | | | | | | | | | | | 2017-03-17 Bernd Schmidt <bschmidt@redhat.com> * combine.c (record_used_regs): New static function. (try_combine): Handle situations where there is an additional instruction between I2 and I3 which needs to have a LOG_LINK updated. Revert: 2017-03-17 Jim Wilson <jim.wilson@linaro.org> * combine.c (try_combine): Delete redundant i1 test. Call prev_nonnote_nondebug_insn instead of prev_nonnote_insn. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@246296 138bc75d-0d04-0410-961f-82ee72b054a4
* Fix aarch64 bootstrap compare failure.wilson2017-03-181-4/+3
| | | | | | | | | gcc/ * combine.c (try_combine): Delete redundant i1 test. Call prev_nonnote_nondebug_insn instead of prev_nonnote_insn. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@246253 138bc75d-0d04-0410-961f-82ee72b054a4
* PR rtl-optimization/79910law2017-03-171-0/+138
| | | | | | | | | | | | * combine.c (record_used_regs): New static function. (try_combine): Handle situations where there is an additional instruction between I2 and I3 which needs to have a LOG_LINK updated. PR rtl-optimization/79910 * gcc.dg/torture/pr79910.c: New test. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@246226 138bc75d-0d04-0410-961f-82ee72b054a4
* PR rtl-optimization/79909jakub2017-03-101-18/+17
| | | | | | | | | | | * combine.c (try_combine): Use simplify_replace_rtx on individual CALL_INSN_FUNCTION_USAGE elements instead of replace_rtx on copy_rtx of the whole CALL_INSN_FUNCTION_USAGE. * gcc.target/powerpc/pr79909.c: New test. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@246023 138bc75d-0d04-0410-961f-82ee72b054a4
* PR rtl-optimization/79388jakub2017-02-131-0/+5
| | | | | | | | | | | | | PR rtl-optimization/79450 * combine.c (distribute_notes): When removing TEM_INSN for which corresponding dest has last value recorded, invalidate that last value. * gcc.c-torture/execute/pr79388.c: New test. * gcc.c-torture/execute/pr79450.c: New test. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@245390 138bc75d-0d04-0410-961f-82ee72b054a4
* PR rtl-optimization/78559amker2017-01-271-1/+10
| | | | | | | | | | | | * combine.c (try_combine): Discard REG_EQUAL and REG_EQUIV for other_insn in combine. gcc/testsuite PR rtl-optimization/78559 * gcc.c-torture/execute/pr78559.c: New test. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@244979 138bc75d-0d04-0410-961f-82ee72b054a4
* PR rtl-optimization/71724bernds2017-01-231-3/+23
| | | | | | | | * combine.c (if_then_else_cond): Look for situations where it is beneficial to undo the work of one of the recursive calls. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@244817 138bc75d-0d04-0410-961f-82ee72b054a4
* Avoid PR72749 by not using unspecsamodra2017-01-141-0/+1
| | | | | | | | | | | | | | | | | | | Rather than using unspecs in doloop insns to stop combine creating these insns, use legitimate_combined_insn. PR target/72749 * combine.c (recog_for_combine_1): Set INSN_CODE before calling target legitimate_combined_insn. * config/rs6000/rs6000.c (TARGET_LEGITIMATE_COMBINED_INSN): Define. (rs6000_legitimate_combined_insn): New function. * config/rs6000/rs6000.md (UNSPEC_DOLOOP): Delete, and remove all uses. (ctr<mode>_internal3): Rename from *ctr<mode>_internal5. (ctr<mode>_internal4): Rename from *ctr<mode>_internal6. (ctr<mode>_internal1, ctr<mode>_internal2): Remove '*' from name. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@244465 138bc75d-0d04-0410-961f-82ee72b054a4
* * combine.c (try_combine): Don't ignore result of overlap checkingnathan2017-01-121-13/+15
| | | | | | | loop. Combine overlap & asm check into single loop. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@244361 138bc75d-0d04-0410-961f-82ee72b054a4
* Update copyright years.jakub2017-01-011-1/+1
| | | | git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@243994 138bc75d-0d04-0410-961f-82ee72b054a4
* combine: Omit redundant AND in change_zero_ext.krebbel2016-12-191-2/+7
| | | | | | | | | | | | | | | | | | | | | | | This is another micro-optimisation in change_zero_ext. If an (and (lshiftrt ... (N)) (M)) generated by change_zero_ext is equivalent to just (lshiftrt ... (N)) (because the AND constant selects the N rightmost bits of the result), strip off the AND. gcc/ChangeLog: 2016-12-19 Dominik Vogt <vogt@linux.vnet.ibm.com> * combine.c (change_zero_ext): Skip generation of redundant AND. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@243792 138bc75d-0d04-0410-961f-82ee72b054a4
* PR debug/77844jakub2016-12-141-8/+17
| | | | | | | | | | | | | | | | | | | * valtrack.c: Include rtl-iter.h. (struct rtx_subst_pair): Add insn field. (propagate_for_debug_subst): If pair->to contains at least 2 regs, create a DEBUG_INSN with a debug temp before pair->insn and replace from with the debug temp instead of pair->to. (propagate_for_debug): Initialize p.insn. * combine.c (insn_uid_check): New inline function. (INSN_COST, LOG_LINKS): Use it instead of INSN_UID. (find_single_use, combine_instructions, cant_combine_insn_p, try_combine): Use NONDEBUG_INSN_P instead of INSN_P. * g++.dg/opt/pr77844.C: New test. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@243662 138bc75d-0d04-0410-961f-82ee72b054a4
* combine: Handle mode expanding zero_extracts in change_zero_ext.segher2016-12-121-3/+9
| | | | | | | | | | | | | | | | | | | | | | Example: (zero_extract:DI (reg:SI) (const_int 24) (const_int 0)) --> (and:DI (subreg:DI (lshiftrt:SI (reg:SI) (const_int 8)) 0) (const_int 16777215)) 2016-12-12 Dominik Vogt <vogt@linux.vnet.ibm.com> * combine.c (change_zero_ext): Handle mode expanding zero_extracts. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@243578 138bc75d-0d04-0410-961f-82ee72b054a4
* Subject: [PATCH] Revert "Do not simplify "(and (reg) (const bit)" tosegher2016-12-051-12/+0
| | | | | | | | | | if_then_else." * combine.c: Revert r243162. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@243256 138bc75d-0d04-0410-961f-82ee72b054a4
* Do not simplify "(and (reg) (const bit)" to if_then_else.krebbel2016-12-021-0/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | combine_simplify_rtx() tries to replace rtx expressions with just two possible values with an experession that uses if_then_else: (if_then_else (condition) (value1) (value2)) If the original expression is e.g. (and (reg) (const_int 2)) where the constant is the mask for a single bit, the replacement results in a more complex expression than before: (if_then_else (ne (zero_extract (reg) (1) (31))) (2) (0)) Similar replacements are done for (signextend (and ...)) (zeroextend (and ...)) Suppress the replacement this special case in if_then_else_cond(). gcc/ChangeLog: 2016-12-02 Dominik Vogt <vogt@linux.vnet.ibm.com> * combine.c (combine_simplify_rtx): Suppress replacement of "(and (reg) (const_int bit))" with "if_then_else". git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@243162 138bc75d-0d04-0410-961f-82ee72b054a4
* Fix rtl-optimization/78596 - combine.c:12561:14: runtime error: left shift ↵trippels2016-12-011-1/+2
| | | | | | | | | | of negative value PR rtl-optimization/78596 * combine.c (simplify_comparison): Cast to unsigned to avoid left shifting of negative value. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@243111 138bc75d-0d04-0410-961f-82ee72b054a4
* combine: Emit a barrier after unconditional trap (PR78607)segher2016-12-011-0/+2
| | | | | | | | | | | | | | | | | After an unconditional trap there should be a barrier. In most cases one is automatically inserted, but not if the trap is the final insn in the instruction stream. We need to emit one explicitly. PR rtl-optimization/78607 * combine.c (try_combine): Emit a barrier after a unconditional trap. gcc/testsuite/ PR rtl-optimization/78607 * gcc.c-torture/compile/pr78607.c: New testcase. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@243092 138bc75d-0d04-0410-961f-82ee72b054a4
* combine: Don't mess with subregs of floating point (PR78590)segher2016-11-301-0/+1
| | | | | | | | | | | | | | | | PR78590 shows a problem in change_zero_ext, where we change a zero_extend of a subreg to a logical and. We should only do this if the thing we are taking the subreg of is a scalar integer, otherwise we will take a subreg of (e.g.) a float in a different size, which is nonsensical and hits an assert. PR rtl-optimization/78590 * combine.c (change_zero_ext): Transform zero_extend of subregs only if the subreg_reg is a scalar integer mode. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@242999 138bc75d-0d04-0410-961f-82ee72b054a4
* Fix PR78588 - rtlanal.c:5210:38: runtime error: shift exponent 4294967295 is ↵trippels2016-11-301-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | too large for 64-bit type Building gcc with -fsanitize=undefined shows: rtlanal.c:5210:38: runtime error: shift exponent 4294967295 is too large for 64-bit type 'long unsigned int' This happens because if_then_else_cond() in combine.c calls num_sign_bit_copies() in rtlanal.c with mode==BLKmode. 5205 bitwidth = GET_MODE_PRECISION (mode); 5206 if (bitwidth > HOST_BITS_PER_WIDE_INT) 5207 return 1; 5208 5209 nonzero = nonzero_bits (x, mode); 5210 return nonzero & (HOST_WIDE_INT_1U << (bitwidth - 1)) 5211 ? 1 : bitwidth - floor_log2 (nonzero) - 1; This causes (bitwidth - 1) to wrap around. PR rtl-optimization/78588 * combine.c (if_then_else_cond): Also guard against BLKmode. * rtlanal.c (num_sign_bit_copies1): Add assert. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@242997 138bc75d-0d04-0410-961f-82ee72b054a4
* combine: Tweak change_zero_extsegher2016-11-291-1/+3
| | | | | | | | | | | | | | change_zero_ext handles (zero_extend:M1 (subreg:M2 (reg:M1) ...)) already; this patch extends it to also deal with any (zero_extend:M1 (subreg:M2 (reg:M3) ...)) where the subreg is not paradoxical. * combine.c (change_zero_ext): Also handle extends from a subreg to a mode bigger than that of the operand of the subreg. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@242950 138bc75d-0d04-0410-961f-82ee72b054a4
* combine: Make code after a new trap unreachable (PR78342)segher2016-11-291-0/+20
| | | | | | | | | | | | | | | | | | | | Combine can turn a conditional trap into an unconditional trap. If it does that it should make the code after it unreachable (an unconditional trap should be the last insn in its bb, and that bb has no successors). This patch seems to work. It is hard to be sure, this is very hard to trigger. Quite a few other passes look like they need something similar as well, but I don't see anything else handling it yet either. PR rtl-optimization/78342 * combine.c: Include "cfghooks.h". (try_combine): If we create an unconditional trap, break the basic block in two just after it, and remove the edge between; also, set the *new_direct_jump_p flag so that cleanup_cfg is run. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@242947 138bc75d-0d04-0410-961f-82ee72b054a4
* gcc:bonzini2016-11-281-4/+12
| | | | | | | | | | * combine.c (simplify_if_then_else): Simplify IF_THEN_ELSE that isolates a single bit, even if the condition involves subregs. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@242917 138bc75d-0d04-0410-961f-82ee72b054a4
* PR rtl-optimization/78527jakub2016-11-251-0/+2
| | | | | | | | | | * combine.c (make_compound_operation_int): Ignore LSHIFTRT with out of bounds shift count. * gcc.c-torture/compile/pr78527.c: New test. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@242879 138bc75d-0d04-0410-961f-82ee72b054a4
* combine: Query can_change_dest_mode before changing dest modesegher2016-11-231-1/+2
| | | | | | | | | | | | | | As reported in https://gcc.gnu.org/ml/gcc-patches/2016-11/msg02388.html . Changing the mode of a hard register can lead to problems, or at least it can make worse code if the result will need reloads. * combine.c (change_zero_ext): Only change the mode of a hard register destination if can_change_dest_mode holds for that. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@242812 138bc75d-0d04-0410-961f-82ee72b054a4
* combine: Convert subreg-of-lshiftrt to zero_extract properly (PR78390)segher2016-11-231-1/+6
| | | | | | | | | | | | | | | | | | | | | r242414, for PR77881, introduces some bugs (PR78390, PR78438, PR78477). It all has the same root cause: that patch makes combine convert every lowpart subreg of a logical shift right to a zero_extract. This cannot work at all if it is not a constant shift, and it has to be a bit more careful exactly which bits it extracts. PR target/77881 PR bootstrap/78390 PR target/78438 PR bootstrap/78477 * combine.c (make_compound_operation_int): Do not convert a subreg of a non-constant logical shift right to a zero_extract. Handle the case where some zero bits have been shifted into the range covered by that subreg. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@242757 138bc75d-0d04-0410-961f-82ee72b054a4
* Use rtx_mode_t instead of std::make_pairrsandifo2016-11-181-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This change makes the code less sensitive to the exact type of the mode, i.e. it forces a conversion where necessary. This becomes important when wrappers like scalar_int_mode and scalar_mode can also be used instead of machine_mode. Using rtx_mode_t also abstracts away the representation. The fact that it's a std::pair rather than a custom class isn't important to users of the interface. gcc/ 2016-11-18 Richard Sandiford <richard.sandiford@arm.com> Alan Hayward <alan.hayward@arm.com> David Sherwood <david.sherwood@arm.com> * combine.c (try_combine): Use rtx_mode_t instead of std::make_pair. * dwarf2out.c (mem_loc_descriptor, loc_descriptor): Likewise. (add_const_value_attribute): Likewise. * explow.c (plus_constant): Likewise. * expmed.c (expand_mult, make_tree): Likewise. * expr.c (convert_modes): Likewise. * loop-doloop.c (doloop_optimize): Likewise. * postreload.c (reload_cse_simplify_set): Likewise. * simplify-rtx.c (simplify_const_unary_operation): Likewise. (simplify_binary_operation_1, simplify_const_binary_operation): (simplify_const_relational_operation, simplify_immed_subreg): Likewise. * wide-int.h: Update documentation to recommend rtx_mode_t instead of std::make_pair. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@242586 138bc75d-0d04-0410-961f-82ee72b054a4
* PR rtl-optimization/78378jakub2016-11-161-4/+4
| | | | | | | | | | * combine.c (make_extraction): Use force_to_mode for non-{REG,MEM} inner only if pos is 0. Fix up formatting. * gcc.c-torture/execute/pr78378.c: New test. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@242526 138bc75d-0d04-0410-961f-82ee72b054a4
* An alternative fix for PR70944rsandifo2016-11-161-74/+87
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The transformations made by make_compound_operation apply only to scalar integer modes. The fix for PR70944 had enforced that by returning early for vector modes at the top of the function. However, the function is supposed to be recursive, so we should continue to look at integer suboperands even if the outer operation is a vector one. This patch instead splits out the non-recursive parts of make_compound_operation into a subroutine and checks that the mode is a scalar integer before calling it. The patch was originally written to help with the later conversion to static type checking of mode classes, but it also happened to reenable optimisation of things like vec_duplicate operands. Note that the gen_lowparts in the PLUS and MINUS cases were redundant, since new_rtx already had mode "mode" at those points. gcc/ 2016-11-15 Richard Sandiford <richard.sandiford@arm.com> Alan Hayward <alan.hayward@arm.com> David Sherwood <david.sherwood@arm.com> * combine.c (maybe_swap_commutative_operands): New function. (combine_simplify_rtx): Use it. (change_zero_ext): Likewise. (make_compound_operation_int): New function, split out of... (make_compound_operation): ...here. Use maybe_swap_commutative_operands for both. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@242492 138bc75d-0d04-0410-961f-82ee72b054a4
* Add a load_extend_op wrapperrsandifo2016-11-151-9/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | LOAD_EXTEND_OP only applies to scalar integer modes that are narrower than a word. However, callers weren't consistent about which of these checks they made beforehand, and also weren't consistent about whether "smaller" was based on (bit)size or precision (IMO it's the latter). This patch adds a wrapper to try to make the macro easier to use. LOAD_EXTEND_OP is often used to disable transformations that aren't beneficial when extends from memory are free, so being stricter about the check accidentally exposed more optimisation opportunities. "SUBREG_BYTE (...) == 0" and subreg_lowpart_p are implied by paradoxical_subreg_p, so the patch also removes some redundant tests. The patch doesn't change reload, since different checks could have unforeseen consequences. gcc/ 2016-11-15 Richard Sandiford <richard.sandiford@arm.com> Alan Hayward <alan.hayward@arm.com> David Sherwood <david.sherwood@arm.com> * rtl.h (load_extend_op): Declare. * rtlanal.c (load_extend_op): New function. (nonzero_bits1): Use it. (num_sign_bit_copies1): Likewise. * cse.c (cse_insn): Likewise. * fold-const.c (fold_single_bit_test): Likewise. (fold_unary_loc): Likewise. * fwprop.c (free_load_extend): Likewise. * postreload.c (reload_cse_simplify_set): Likewise. (reload_cse_simplify_operands): Likewise. * combine.c (try_combine): Likewise. (simplify_set): Likewise. Remove redundant SUBREG_BYTE and subreg_lowpart_p checks. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@242444 138bc75d-0d04-0410-961f-82ee72b054a4
* Fix simplify_shift_const_1 handling of vector shiftsrsandifo2016-11-151-54/+89
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | simplify_shift_const_1 handles both shifts of scalars by scalars and shifts of vectors by scalars. For vectors this means that each element is shifted by the same amount. However: (a) the two cases weren't always distinguished, so we'd try things for vectors that only made sense for scalars. (b) a lot of the range and bitcount checks were based on the bitsize or precision of the full shifted operand, rather than the mode of each element. Fixing (b) accidentally exposed more optimisation opportunities, although that wasn't the point of the patch. gcc/ 2016-11-15 Richard Sandiford <richard.sandiford@arm.com> Alan Hayward <alan.hayward@arm.com> David Sherwood <david.sherwood@arm.com> * combine.c (simplify_shift_const_1): Use the number of bits in the inner mode to determine the range of the shift. When handling shifts of vectors, skip any rules that apply only to scalars. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@242442 138bc75d-0d04-0410-961f-82ee72b054a4
* PR missed-optimization/77881matz2016-11-151-0/+35
| | | | | | | | | | | | | * combine.c (simplify_comparison): Remove useless subregs also inside the loop, not just after it. (make_compound_operation): Recognize some subregs as being masking as well. testsuite/ * gcc.target/i386/pr77881.c: New test. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@242414 138bc75d-0d04-0410-961f-82ee72b054a4
* PR rtl-optimization/59461ebotcazou2016-11-111-9/+9
| | | | | | | | | | | | | | * doc/rtl.texi (paradoxical subregs): Add missing word. * combine.c (reg_nonzero_bits_for_combine): Do not discard results in modes with precision larger than that of last_set_mode. * rtlanal.c (nonzero_bits1) <SUBREG>: If WORD_REGISTER_OPERATIONS is set and LOAD_EXTEND_OP is appropriate, propagate results from inner REGs to paradoxical SUBREGs. (num_sign_bit_copies1) <SUBREG>: Likewise. Check that the mode is not larger than a word before invoking LOAD_EXTEND_OP on it. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@242326 138bc75d-0d04-0410-961f-82ee72b054a4
* combine: Do not call simplify from inside change_zero_ext (PR78232)segher2016-11-101-9/+22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | When combine splits a three-insn combination into two instructions it can reuse i2dest for the temporary result of the first new instruction. However all information it has in reg_stat about that register will be stale. This results in the simplify_gen_binary calls in change_zero_ext using out-of-date information, which makes it think one of the ANDs generated there always results in 0, and it doesn't get better from there. This can also happen if a splitter in the MD uses nonzero_bits (for example). I tried to make the splitting code in combine save and restore the i2dest reg_stat info, but that causes one of the acats tests to fail. This whole reg_stat thing needs an overhaul, and/or we shouldn't reuse i2dest for unrelated purposes when splitting. This patch changes change_zero_ext to do the expected simplifications itself and not call simplify_gen_*. PR rtl-optimization/78232 * combine.c (try_combine): Add a big comment about why reusing i2dest is undesirable. (change_zero_ext): Do not call simplify_gen_binary, do the simplifications manually. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@242059 138bc75d-0d04-0410-961f-82ee72b054a4
* PR rtl-optimization/77309bernds2016-11-071-6/+18
| | | | | | | | | | | | | | * combine.c (make_compound_operation): Allow EQ for IN_CODE, and don't assume an equality comparison for plain COMPARE. (simplify_comparison): Pass a more accurate code to make_compound_operation. testsuite/ PR rtl-optimization/77309 * gcc.dg/torture/pr77309.c: New test. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@241912 138bc75d-0d04-0410-961f-82ee72b054a4
* * defaults.h (LOAD_EXTEND_OP): Define if not already defined.ebotcazou2016-11-041-8/+4
| | | | | | | | | | | | | | | | | | * combine.c (LOAD_EXTEND_OP): Delete. (simplify_comparison): Fix comment about LOAD_EXTEND_OP. * cse.c (LOAD_EXTEND_OP): Delete. * fold-const.c (LOAD_EXTEND_OP): Likewise. * fwprop.c (free_load_extend): Remove #ifdef LOAD_EXTEND_OP/#endif. * postreload.c (LOAD_EXTEND_OP): Delete. * reload.c (push_reload): Remove #ifdef LOAD_EXTEND_OP/#endif. Convert conditional compilation based on WORD_REGISTER_OPERATIONS. (find_reloads): Likewise. * reload1.c (eliminate_regs_1): Likewise. * rtlanal.c (nonzero_bits1): Remove #ifdef LOAD_EXTEND_OP/#endif. (num_sign_bit_copies1): Likewise. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@241855 138bc75d-0d04-0410-961f-82ee72b054a4
* combine lhs zero_extract fix (PR78186)segher2016-11-031-0/+3
| | | | | | | | | PR rtl-optimization/78186 * combine.c (change_zero_ext): Mask the RHS of a zero_extract as well, when converting to IOR. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@241824 138bc75d-0d04-0410-961f-82ee72b054a4
* Mark fallthrough cases with gcc_fallthrough.foreese2016-11-011-0/+2
| | | | | | | | * gcc/combine.c (simplify_compare_const): Add gcc_fallthrough. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@241744 138bc75d-0d04-0410-961f-82ee72b054a4
* combine: Improve change_zero_ext (fixes PR71847)segher2016-10-281-4/+51
| | | | | | | | | | | | | | | | | | | | | | | | | | This improves a few things in change_zero_ext. Firstly, it should use the passed in pattern in recog_for_combine, not the pattern of the insn (they are not the same if the whole pattern was replaced). Secondly, it handled zero_ext of a subreg, but with hard registers we do not get a subreg, instead the mode of the reg is changed. So this handles that. Thirdly, after changing a zero_ext to an AND, the resulting RTL may become non-canonical, like (ior (ashift ..) (and ..)); the AND should be first, it is commutative. And lastly, zero_extract as a set_dest wasn't handled at all, but now it is. This fixes the testcase in PR71847, and improves code generation in some other edge cases too. PR target/71847 * combine.c (change_zero_ext): Handle zero_ext of hard registers. Swap commutative operands in new RTL if needed. Handle zero_ext in the set_dest. (recog_for_combine): Pass *pnewpat to change_zero_ext instead of PATTERN (insn). git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@241664 138bc75d-0d04-0410-961f-82ee72b054a4
* make LABEL_REF_LABEL a rtx_insn *tbsaunde2016-10-211-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | While changing LABEL_REF_LABEL it might as well become an inline function, so that its clearer what types are involved. Unfortunately because it is still possible to use XEXP and related macros on a LABEL_REF rtx you can still set the field to be a non insn rtx. The other unfortunate thing is that the generators actually create LABEL_REF rtx that refer to MATCH_x rtx, so there we actually need to use XEXP to bypass the checking this patch adds. gcc/ChangeLog: 2016-10-21 Trevor Saunders <tbsaunde+gcc@tbsaunde.org> * rtl.h (label_ref_label): New function. (set_label_ref_label): New function. (LABEL_REF_LABEL): Delete. * alias.c (rtx_equal_for_memref_p): Adjust. * cfgbuild.c (make_edges): Likewise. (purge_dead_tablejump_edges): Likewise. * cfgexpand.c (convert_debug_memory_address): Likewise. * cfgrtl.c (patch_jump_insn): Likewise. * combine.c (distribute_notes): Likewise. * cse.c (hash_rtx_cb): Likewise. (exp_equiv_p): Likewise. (fold_rtx): Likewise. (check_for_label_ref): Likewise. * cselib.c (rtx_equal_for_cselib_1): Likewise. (cselib_hash_rtx): Likewise. * emit-rtl.c (mark_label_nuses): Likewise. * explow.c (convert_memory_address_addr_space_1): Likewise. * final.c (output_asm_label): Likewise. (output_addr_const): Likewise. * gcse.c (add_label_notes): Likewise. * genconfig.c (walk_insn_part): Likewise. * genrecog.c (validate_pattern): Likewise. * ifcvt.c (cond_exec_get_condition): Likewise. (noce_emit_store_flag): Likewise. (noce_get_alt_condition): Likewise. (noce_get_condition): Likewise. * jump.c (maybe_propagate_label_ref): Likewise. (mark_jump_label_1): Likewise. (redirect_exp_1): Likewise. (rtx_renumbered_equal_p): Likewise. * lra-constraints.c (operands_match_p): Likewise. * print-rtl.c (print_value): Likewise. * reload.c (find_reloads): Likewise. * reload1.c (set_label_offsets): Likewise. * reorg.c (get_branch_condition): Likewise. * rtl-tests.c (test_uncond_jump): Likewise. * rtl.c (rtx_equal_p_cb): Likewise. (rtx_equal_p): Likewise. * rtlanal.c (reg_mentioned_p): Likewise. (rtx_referenced_p): Likewise. (get_condition): Likewise. * varasm.c (const_hash_1): Likewise. (compare_constant): Likewise. (const_rtx_hash_1): Likewise. (output_constant_pool_1): Likewise. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@241401 138bc75d-0d04-0410-961f-82ee72b054a4
* Move MEMMODEL_* from coretypes.h to memmodel.hthopre012016-10-131-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 2016-10-13 Thomas Preud'homme <thomas.preudhomme@arm.com> gcc/ * coretypes.h: Move MEMMODEL_* macros and enum memmodel definition into ... * memmodel.h: This file. * alias.c, asan.c, auto-inc-dec.c, bb-reorder.c, bt-load.c, caller-save.c, calls.c, ccmp.c, cfgbuild.c, cfgcleanup.c, cfgexpand.c, cfgloopanal.c, cfgrtl.c, cilk-common.c, combine.c, combine-stack-adj.c, common/config/aarch64/aarch64-common.c, common/config/arm/arm-common.c, common/config/bfin/bfin-common.c, common/config/c6x/c6x-common.c, common/config/i386/i386-common.c, common/config/ia64/ia64-common.c, common/config/nvptx/nvptx-common.c, compare-elim.c, config/aarch64/aarch64-builtins.c, config/aarch64/aarch64-c.c, config/aarch64/cortex-a57-fma-steering.c, config/arc/arc.c, config/arc/arc-c.c, config/arm/arm-builtins.c, config/arm/arm-c.c, config/avr/avr.c, config/avr/avr-c.c, config/avr/avr-log.c, config/bfin/bfin.c, config/c6x/c6x.c, config/cr16/cr16.c, config/cris/cris.c, config/darwin-c.c, config/darwin.c, config/epiphany/epiphany.c, config/epiphany/mode-switch-use.c, config/epiphany/resolve-sw-modes.c, config/fr30/fr30.c, config/frv/frv.c, config/ft32/ft32.c, config/h8300/h8300.c, config/i386/i386-c.c, config/i386/winnt.c, config/iq2000/iq2000.c, config/lm32/lm32.c, config/m32c/m32c.c, config/m32r/m32r.c, config/m68k/m68k.c, config/mcore/mcore.c, config/microblaze/microblaze.c, config/mmix/mmix.c, config/mn10300/mn10300.c, config/moxie/moxie.c, config/msp430/msp430.c, config/nds32/nds32-cost.c, config/nds32/nds32-intrinsic.c, config/nds32/nds32-md-auxiliary.c, config/nds32/nds32-memory-manipulation.c, config/nds32/nds32-predicates.c, config/nds32/nds32.c, config/nios2/nios2.c, config/nvptx/nvptx.c, config/pa/pa.c, config/pdp11/pdp11.c, config/rl78/rl78.c, config/rs6000/rs6000-c.c, config/rx/rx.c, config/s390/s390-c.c, config/s390/s390.c, config/sh/sh.c, config/sh/sh-c.c, config/sh/sh-mem.cc, config/sh/sh_treg_combine.cc, config/sol2.c, config/spu/spu.c, config/stormy16/stormy16.c, config/tilegx/tilegx.c, config/tilepro/tilepro.c, config/v850/v850.c, config/vax/vax.c, config/visium/visium.c, config/vms/vms-c.c, config/xtensa/xtensa.c, coverage.c, cppbuiltin.c, cprop.c, cse.c, cselib.c, dbxout.c, dce.c, df-core.c, df-problems.c, df-scan.c, dojump.c, dse.c, dwarf2asm.c, dwarf2cfi.c, dwarf2out.c, emit-rtl.c, except.c, explow.c, expmed.c, expr.c, final.c, fold-const.c, function.c, fwprop.c, gcse.c, ggc-page.c, haifa-sched.c, hsa-brig.c, hsa-gen.c, hw-doloop.c, ifcvt.c, init-regs.c, internal-fn.c, ira-build.c, ira-color.c, ira-conflicts.c, ira-costs.c, ira-emit.c, ira-lives.c, ira.c, jump.c, loop-doloop.c, loop-invariant.c, loop-iv.c, loop-unroll.c, lower-subreg.c, lra.c, lra-assigns.c, lra-coalesce.c, lra-constraints.c, lra-eliminations.c, lra-lives.c, lra-remat.c, lra-spills.c, mode-switching.c, modulo-sched.c, omp-low.c, passes.c, postreload-gcse.c, postreload.c, predict.c, print-rtl-function.c, recog.c, ree.c, reg-stack.c, regcprop.c, reginfo.c, regrename.c, reload.c, reload1.c, reorg.c, resource.c, rtl-chkp.c, rtl-tests.c, rtlanal.c, rtlhooks.c, sched-deps.c, sched-rgn.c, sdbout.c, sel-sched-ir.c, sel-sched.c, shrink-wrap.c, simplify-rtx.c, stack-ptr-mod.c, stmt.c, stor-layout.c, target-globals.c, targhooks.c, toplev.c, tree-nested.c, tree-outof-ssa.c, tree-profile.c, tree-ssa-coalesce.c, tree-ssa-ifcombine.c, tree-ssa-loop-ivopts.c, tree-ssa-loop.c, tree-ssa-reassoc.c, tree-ssa-sccvn.c, tree-vect-data-refs.c, ubsan.c, valtrack.c, var-tracking.c, varasm.c: Include memmodel.h. * genattrtab.c (write_header): Include memmodel.h in generated file. * genautomata.c (main): Likewise. * gengtype.c (open_base_files): Likewise. * genopinit.c (main): Likewise. * genconditions.c (write_header): Include memmodel.h earlier in generated file. * genemit.c (main): Likewise. * genoutput.c (output_prologue): Likewise. * genpeep.c (main): Likewise. * genpreds.c (write_insn_preds_c): Likewise. * genrecog.c (write_header): Likewise. * Makefile.in (PLUGIN_HEADERS): Include memmodel.h gcc/ada/ * gcc-interface/utils2.c: Include memmodel.h. gcc/c-family/ * c-cppbuiltin.c: Include memmodel.h. * c-opts.c: Likewise. * c-pragma.c: Likewise. * c-warn.c: Likewise. gcc/c/ * c-typeck.c: Include memmodel.h. gcc/cp/ * decl2.c: Include memmodel.h. * rtti.c: Likewise. gcc/fortran/ * trans-intrinsic.c: Include memmodel.h. gcc/go/ * go-backend.c: Include memmodel.h. libgcc/ * libgcov-profiler.c: Replace MEMMODEL_* macros by their __ATOMIC_* equivalent. * config/tilepro/atomic.c: Likewise and stop casting model to enum memmodel. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@241121 138bc75d-0d04-0410-961f-82ee72b054a4
* * combine.c (simplify_comparison): Add canonical FALLTHROUGH comments.jakub2016-09-271-3/+3
| | | | | | | | | | * config/i386/i386.c (ix86_dep_by_shift_count_body): Add FALLTHROUGH comments. Remove break after return. (ix86_fp_compare_code_to_integer, has_dispatch, ix86_simd_clone_usable): Remove break after return. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@240523 138bc75d-0d04-0410-961f-82ee72b054a4
* Add inline functions for various bitwise operations.jason2016-09-161-12/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * hwint.h (least_bit_hwi, pow2_or_zerop, pow2p_hwi, ctz_or_zero): New. * hwint.c (exact_log2): Use pow2p_hwi. (ctz_hwi, ffs_hwi): Use least_bit_hwi. * alias.c (memrefs_conflict_p): Use pow2_or_zerop. * builtins.c (get_object_alignment_2, get_object_alignment) (get_pointer_alignment, fold_builtin_atomic_always_lock_free): Use least_bit_hwi. * calls.c (compute_argument_addresses, store_one_arg): Use least_bit_hwi. * cfgexpand.c (expand_one_stack_var_at): Use least_bit_hwi. * combine.c (force_to_mode): Use least_bit_hwi. * emit-rtl.c (set_mem_attributes_minus_bitpos, adjust_address_1): Use least_bit_hwi. * expmed.c (synth_mult, expand_divmod): Use ctz_or_zero, ctz_hwi. (init_expmed_one_conv): Use pow2p_hwi. * fold-const.c (round_up_loc, round_down_loc): Use pow2_or_zerop. (fold_binary_loc): Use pow2p_hwi. * function.c (assign_parm_find_stack_rtl): Use least_bit_hwi. * gimple-fold.c (gimple_fold_builtin_memory_op): Use pow2p_hwi. * gimple-ssa-strength-reduction.c (replace_ref): Use least_bit_hwi. * hsa-gen.c (gen_hsa_addr_with_align, hsa_bitmemref_alignment): Use least_bit_hwi. * ipa-cp.c (ipcp_alignment_lattice::meet_with_1): Use least_bit_hwi. * ipa-prop.c (ipa_modify_call_arguments): Use least_bit_hwi. * omp-low.c (oacc_loop_fixed_partitions) (oacc_loop_auto_partitions): Use least_bit_hwi. * rtlanal.c (nonzero_bits1): Use ctz_or_zero. * stor-layout.c (place_field): Use least_bit_hwi. * tree-pretty-print.c (dump_generic_node): Use pow2p_hwi. * tree-sra.c (build_ref_for_offset): Use least_bit_hwi. * tree-ssa-ccp.c (ccp_finalize): Use least_bit_hwi. * tree-ssa-math-opts.c (bswap_replace): Use least_bit_hwi. * tree-ssa-strlen.c (handle_builtin_memcmp): Use pow2p_hwi. * tree-vect-data-refs.c (vect_analyze_group_access_1) (vect_grouped_store_supported, vect_grouped_load_supported) (vect_permute_load_chain, vect_shift_permute_load_chain) (vect_transform_grouped_load): Use pow2p_hwi. * tree-vect-generic.c (expand_vector_divmod): Use ctz_or_zero. * tree-vect-patterns.c (vect_recog_divmod_pattern): Use ctz_or_zero. * tree-vect-stmts.c (vectorizable_mask_load_store): Use least_bit_hwi. * tsan.c (instrument_expr): Use least_bit_hwi. * var-tracking.c (negative_power_of_two_p): Use pow2_or_zerop. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@240194 138bc75d-0d04-0410-961f-82ee72b054a4
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