summaryrefslogtreecommitdiff
path: root/gcc/ChangeLog
Commit message (Expand)AuthorAgeFilesLines
* [RS6000] power8 unaligned fp load/storeamodra2016-08-031-0/+7
* [RS6000] cost SLOW_UNALIGNED_ACCESSamodra2016-08-031-0/+5
* [RS6000] Force source of fix_trunc<mode>si2 to regamodra2016-08-031-0/+5
* [RS6000] Remove negative from option help stringsamodra2016-08-031-0/+5
* [RS6000] Delete duplicate codeamodra2016-08-031-0/+5
* 2016-08-02 Vladimir Makarov <vmakarov@redhat.com>vmakarov2016-08-021-0/+6
* 2016-08-02 Vladimir Makarov <vmakarov@redhat.com>vmakarov2016-08-021-0/+35
* [Patch AArch64 Obvious] Fix Bootstrap for my mistake in r238977jgreenhalgh2016-08-021-0/+5
* PR tree-optimization/34114amker2016-08-021-0/+6
* PR tree-optimization/34114amker2016-08-021-0/+6
* [PATCH AArch64] Add more AArch64 NEON intrinsicsjgreenhalgh2016-08-021-0/+20
* [gcc]meissner2016-08-011-0/+34
* PR target/71948gjl2016-08-011-0/+6
* This patch optimizes the prolog and epilog code to reduce the number ofwilco2016-08-011-0/+17
* Convert V1TImode register to TImode in debug insnhjl2016-08-011-0/+7
* 2016-08-01 Alan Hayward <alan.hayward@arm.com>alahay012016-08-011-0/+6
* PR target/72767gjl2016-08-011-0/+6
* * doc/extend.texi (AVR Built-in Functions): Documentgjl2016-08-011-0/+8
* [AArch64] Allow multiple-of-8 immediate offsets for TImode LDP/STPktkachov2016-08-011-0/+6
* 2016-08-01 Virendra Pathak <virendra.pathak@broadcom.com>rearnsha2016-08-011-0/+5
* [gcc]meissner2016-07-301-0/+23
* * config/avr/avr.c (avr_out_compare): Use const0_rtx instead of 0gjl2016-07-291-0/+5
* PR tree-optimization/57558amker2016-07-291-0/+24
* * cfgloop.h (struct loop): New field constraints.amker2016-07-291-0/+13
* PR c/7652mpolacek2016-07-291-1/+7
* gcc/gjl2016-07-291-0/+7
* PR c/7652mpolacek2016-07-291-0/+6
* * config/avr/avr.md (addqi3) [cc]: Revert glitch in insn attributegjl2016-07-291-0/+5
* gcc/ChangeLog:kugan2016-07-291-0/+6
* [gcc]meissner2016-07-281-0/+30
* On AArch64 the UXTB and UXTH instructions are aliases of UBFM,wilco2016-07-281-0/+13
* This patchset improves zero extend costs and code generation.wilco2016-07-281-0/+4
* This patch improves the readability of the prolog and epilog code by movingwilco2016-07-281-0/+8
* gcc/ienkovich2016-07-281-0/+9
* gcc/ienkovich2016-07-281-0/+8
* merge adjust_cost and adjust_cost_2 target hookstbsaunde2016-07-281-0/+36
* haifa-sched.c: make twins a auto_vec<rtx_insn *>tbsaunde2016-07-281-0/+4
* make pattern_regs a vectbsaunde2016-07-281-0/+11
* Introduce no_profile_instrument_function attributemarxin2016-07-281-0/+8
* Do not allow make_compound_operation for vector modemarxin2016-07-281-0/+6
* gcc/testsuite/ChangeLog:kugan2016-07-271-0/+6
* 2016-07-27 Bernd Edlinger <bernd.edlinger@hotmail.de>edlinger2016-07-271-0/+9
* 2016-07-27 Michael Meissner <meissner@linux.vnet.ibm.com>meissner2016-07-271-0/+13
* Move make_location from tree.h/c to input.h/cdmalcolm2016-07-271-0/+16
* Add missing PR marker to Changelog for 71216 fixsegher2016-07-271-0/+1
* 2016-07-27 Prathamesh Kulkarni <prathamesh.kulkarni@linaro.org>prathamesh34922016-07-271-0/+5
* Use static_assert for STATIC_ASSERT for C++11 onwardsdmalcolm2016-07-271-0/+5
* 2016-07-27 Richard Biener <rguenther@suse.de>rguenth2016-07-271-0/+6
* 2016-07-27 Richard Biener <rguenther@suse.de>rguenth2016-07-271-0/+4
* predict.c: merge multi-edgesmarxin2016-07-271-0/+5
View Lorry Controller Status