| Commit message (Expand) | Author | Age | Files | Lines |
|---|
| * | [RS6000] power8 unaligned fp load/store | amodra | 2016-08-03 | 1 | -0/+7 |
| * | [RS6000] cost SLOW_UNALIGNED_ACCESS | amodra | 2016-08-03 | 1 | -0/+5 |
| * | [RS6000] Force source of fix_trunc<mode>si2 to reg | amodra | 2016-08-03 | 1 | -0/+5 |
| * | [RS6000] Remove negative from option help strings | amodra | 2016-08-03 | 1 | -0/+5 |
| * | [RS6000] Delete duplicate code | amodra | 2016-08-03 | 1 | -0/+5 |
| * | 2016-08-02 Vladimir Makarov <vmakarov@redhat.com> | vmakarov | 2016-08-02 | 1 | -0/+6 |
| * | 2016-08-02 Vladimir Makarov <vmakarov@redhat.com> | vmakarov | 2016-08-02 | 1 | -0/+35 |
| * | [Patch AArch64 Obvious] Fix Bootstrap for my mistake in r238977 | jgreenhalgh | 2016-08-02 | 1 | -0/+5 |
| * | PR tree-optimization/34114 | amker | 2016-08-02 | 1 | -0/+6 |
| * | PR tree-optimization/34114 | amker | 2016-08-02 | 1 | -0/+6 |
| * | [PATCH AArch64] Add more AArch64 NEON intrinsics | jgreenhalgh | 2016-08-02 | 1 | -0/+20 |
| * | [gcc] | meissner | 2016-08-01 | 1 | -0/+34 |
| * | PR target/71948 | gjl | 2016-08-01 | 1 | -0/+6 |
| * | This patch optimizes the prolog and epilog code to reduce the number of | wilco | 2016-08-01 | 1 | -0/+17 |
| * | Convert V1TImode register to TImode in debug insn | hjl | 2016-08-01 | 1 | -0/+7 |
| * | 2016-08-01 Alan Hayward <alan.hayward@arm.com> | alahay01 | 2016-08-01 | 1 | -0/+6 |
| * | PR target/72767 | gjl | 2016-08-01 | 1 | -0/+6 |
| * | * doc/extend.texi (AVR Built-in Functions): Document | gjl | 2016-08-01 | 1 | -0/+8 |
| * | [AArch64] Allow multiple-of-8 immediate offsets for TImode LDP/STP | ktkachov | 2016-08-01 | 1 | -0/+6 |
| * | 2016-08-01 Virendra Pathak <virendra.pathak@broadcom.com> | rearnsha | 2016-08-01 | 1 | -0/+5 |
| * | [gcc] | meissner | 2016-07-30 | 1 | -0/+23 |
| * | * config/avr/avr.c (avr_out_compare): Use const0_rtx instead of 0 | gjl | 2016-07-29 | 1 | -0/+5 |
| * | PR tree-optimization/57558 | amker | 2016-07-29 | 1 | -0/+24 |
| * | * cfgloop.h (struct loop): New field constraints. | amker | 2016-07-29 | 1 | -0/+13 |
| * | PR c/7652 | mpolacek | 2016-07-29 | 1 | -1/+7 |
| * | gcc/ | gjl | 2016-07-29 | 1 | -0/+7 |
| * | PR c/7652 | mpolacek | 2016-07-29 | 1 | -0/+6 |
| * | * config/avr/avr.md (addqi3) [cc]: Revert glitch in insn attribute | gjl | 2016-07-29 | 1 | -0/+5 |
| * | gcc/ChangeLog: | kugan | 2016-07-29 | 1 | -0/+6 |
| * | [gcc] | meissner | 2016-07-28 | 1 | -0/+30 |
| * | On AArch64 the UXTB and UXTH instructions are aliases of UBFM, | wilco | 2016-07-28 | 1 | -0/+13 |
| * | This patchset improves zero extend costs and code generation. | wilco | 2016-07-28 | 1 | -0/+4 |
| * | This patch improves the readability of the prolog and epilog code by moving | wilco | 2016-07-28 | 1 | -0/+8 |
| * | gcc/ | ienkovich | 2016-07-28 | 1 | -0/+9 |
| * | gcc/ | ienkovich | 2016-07-28 | 1 | -0/+8 |
| * | merge adjust_cost and adjust_cost_2 target hooks | tbsaunde | 2016-07-28 | 1 | -0/+36 |
| * | haifa-sched.c: make twins a auto_vec<rtx_insn *> | tbsaunde | 2016-07-28 | 1 | -0/+4 |
| * | make pattern_regs a vec | tbsaunde | 2016-07-28 | 1 | -0/+11 |
| * | Introduce no_profile_instrument_function attribute | marxin | 2016-07-28 | 1 | -0/+8 |
| * | Do not allow make_compound_operation for vector mode | marxin | 2016-07-28 | 1 | -0/+6 |
| * | gcc/testsuite/ChangeLog: | kugan | 2016-07-27 | 1 | -0/+6 |
| * | 2016-07-27 Bernd Edlinger <bernd.edlinger@hotmail.de> | edlinger | 2016-07-27 | 1 | -0/+9 |
| * | 2016-07-27 Michael Meissner <meissner@linux.vnet.ibm.com> | meissner | 2016-07-27 | 1 | -0/+13 |
| * | Move make_location from tree.h/c to input.h/c | dmalcolm | 2016-07-27 | 1 | -0/+16 |
| * | Add missing PR marker to Changelog for 71216 fix | segher | 2016-07-27 | 1 | -0/+1 |
| * | 2016-07-27 Prathamesh Kulkarni <prathamesh.kulkarni@linaro.org> | prathamesh3492 | 2016-07-27 | 1 | -0/+5 |
| * | Use static_assert for STATIC_ASSERT for C++11 onwards | dmalcolm | 2016-07-27 | 1 | -0/+5 |
| * | 2016-07-27 Richard Biener <rguenther@suse.de> | rguenth | 2016-07-27 | 1 | -0/+6 |
| * | 2016-07-27 Richard Biener <rguenther@suse.de> | rguenth | 2016-07-27 | 1 | -0/+4 |
| * | predict.c: merge multi-edges | marxin | 2016-07-27 | 1 | -0/+5 |
