diff options
Diffstat (limited to 'gcc/testsuite')
35 files changed, 921 insertions, 14 deletions
diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index a3a5f18e118..33920f8651a 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,133 @@ +2012-06-25 Jason Merrill <jason@redhat.com> + + PR c++/52988 + * g++.dg/cpp0x/nullptr28.C: New. + +2012-06-19 Kaz Kojima <kkojima@gcc.gnu.org> + + * gcc.dg/stack-usage-1.c: Remove dg-options line for sh targets + and add __sh__ case. + +2012-06-14 Tobias Burnus <burnus@net-b.de> + + PR fortran/53597 + * gfortran.dg/save_4.f90: New. + +2012-06-13 Christian Bruel <christian.bruel@st.com> + + PR target/53621 + * gcc.dg/stack-usage-1.c: Force -fomit-frame-pointer on SH. + +2012-06-05 Tobias Burnus <burnus@net-b.de> + + PR fortran/50619 + * gfortran.dg/init_flag_10.f90: New. + +2012-06-04 Edmar Wienskoski <edmar@freescale.com> + + PR target/53559 + * gcc.target/powerpc/cell_builtin_1.c: New test case. + * gcc.target/powerpc/cell_builtin_2.c: Ditto. + * gcc.target/powerpc/cell_builtin_3.c: Ditto. + * gcc.target/powerpc/cell_builtin_4.c: Ditto. + * gcc.target/powerpc/cell_builtin_5.c: Ditto. + * gcc.target/powerpc/cell_builtin_6.c: Ditto. + * gcc.target/powerpc/cell_builtin_7.c: Ditto. + * gcc.target/powerpc/cell_builtin_8.c: Ditto. + +2012-05-23 Michael Hope <michael.hope@linaro.org> + + PR c++/52796 + * g++.dg/cpp0x/variadic-value1.C: Change selector for explicit + options. + +2012-05-23 Tobias Burnus <burnus@net-b.de> + + PR fortran/53389 + * gfortran.dg/realloc_on_assign_15.f90: New. + +2012-05-22 Richard Guenther <rguenther@suse.de> + + Backport from mainline + 2011-11-10 Richard Guenther <rguenther@suse.de> + + PR middle-end/51071 + * gcc.dg/torture/pr51071.c: New testcase. + * gcc.dg/torture/pr51071-2.c: Likewise. + +2012-05-22 Richard Guenther <rguenther@suse.de> + + Backport from mainline + 2012-02-28 Richard Guenther <rguenther@suse.de> + + PR target/52407 + * gcc.dg/torture/pr52407.c: New testcase. + +2012-05-22 Richard Guenther <rguenther@suse.de> + + Backport from mainline + 2012-04-12 Richard Guenther <rguenther@suse.de> + + PR c/52862 + * gcc.dg/pr52862.c: New testcase. + +2012-05-21 Joseph Myers <joseph@codesourcery.com> + + PR c/53418 + * gcc.c-torture/compile/pr53418-1.c, + gcc.c-torture/compile/pr53418-2.c: New tests. + +2012-05-21 H.J. Lu <hongjiu.lu@intel.com> + + Backport from mainline + 2012-05-21 Uros Bizjak <ubizjak@gmail.com> + H.J. Lu <hongjiu.lu@intel.com> + + PR target/53416 + * gcc.target/i386/pr53416.c: New file. + +2012-05-14 Uros Bizjak <ubizjak@gmail.com> + + * gcc.target/i386/avx256-unaligned-load-[1234].c: Update scan strings. + * gcc.target/i386/avx256-unaligned-store-[1234].c: Ditto. + +2012-05-03 Michael Meissner <meissner@linux.vnet.ibm.com> + + Backport from mainline + 2012-05-03 Michael Meissner <meissner@linux.vnet.ibm.com> + + PR target/53199 + * gcc.target/powwerpc/pr53199.c: New file. + +2012-05-02 Tobias Burnus <burnus@net-b.de> + + Backport from mainline + 2012-04-16 Tobias Burnus <burnus@net-b.de> + + PR fortran/52864 + * gfortran.dg/pointer_intent_6.f90: New. + +2012-04-30 Uros Bizjak <ubizjak@gmail.com> + + Backport from mainline + 2012-04-27 Paolo Bonzini <bonzini@gnu.org> + + PR target/53138 + * gcc.c-torture/execute/20120427-1.c: New testcase. + +2012-04-24 Jakub Jelinek <jakub@redhat.com> + + PR middle-end/53084 + * gcc.c-torture/execute/pr53084.c: New test. + +2012-04-13 Michael Meissner <meissner@linux.vnet.ibm.com> + + Backport from mainline + 2012-04-12 Michael Meissner <meissner@linux.vnet.ibm.com> + + PR target/52775 + * gcc.target/powerpc/pr52775.c: New file. + 2012-04-03 Jason Merrill <jason@redhat.com> PR c++/52796 diff --git a/gcc/testsuite/g++.dg/cpp0x/nullptr28.C b/gcc/testsuite/g++.dg/cpp0x/nullptr28.C new file mode 100644 index 00000000000..05fbe57b197 --- /dev/null +++ b/gcc/testsuite/g++.dg/cpp0x/nullptr28.C @@ -0,0 +1,16 @@ +// { dg-do run { target c++11 } } + +typedef decltype(nullptr) nullptr_t; + +int i; +nullptr_t n; +const nullptr_t& f() { ++i; return n; } + +nullptr_t g() { return f(); } + +int main() +{ + g(); + if (i != 1) + __builtin_abort (); +} diff --git a/gcc/testsuite/g++.dg/cpp0x/variadic-value1.C b/gcc/testsuite/g++.dg/cpp0x/variadic-value1.C index 179919a5bc7..301bd54631c 100644 --- a/gcc/testsuite/g++.dg/cpp0x/variadic-value1.C +++ b/gcc/testsuite/g++.dg/cpp0x/variadic-value1.C @@ -1,5 +1,5 @@ // PR c++/52796 -// { dg-do run { target c++11 } } +// { dg-options "-std=c++0x -pedantic-errors" } inline void *operator new(__SIZE_TYPE__ s, void *p) { return p; } diff --git a/gcc/testsuite/gcc.c-torture/compile/pr53418-1.c b/gcc/testsuite/gcc.c-torture/compile/pr53418-1.c new file mode 100644 index 00000000000..721b02d7878 --- /dev/null +++ b/gcc/testsuite/gcc.c-torture/compile/pr53418-1.c @@ -0,0 +1,5 @@ +void +f (void) +{ + int i = (0 ? 1 : 0U / 0); +} diff --git a/gcc/testsuite/gcc.c-torture/compile/pr53418-2.c b/gcc/testsuite/gcc.c-torture/compile/pr53418-2.c new file mode 100644 index 00000000000..a437b6a0e62 --- /dev/null +++ b/gcc/testsuite/gcc.c-torture/compile/pr53418-2.c @@ -0,0 +1,5 @@ +void +f (void) +{ + int i = (1 ? 0U / 0 : 1); +} diff --git a/gcc/testsuite/gcc.c-torture/execute/20120427-1.c b/gcc/testsuite/gcc.c-torture/execute/20120427-1.c new file mode 100644 index 00000000000..46ed76ae943 --- /dev/null +++ b/gcc/testsuite/gcc.c-torture/execute/20120427-1.c @@ -0,0 +1,36 @@ +typedef struct sreal +{ + unsigned sig; /* Significant. */ + int exp; /* Exponent. */ +} sreal; + +sreal_compare (sreal *a, sreal *b) +{ + if (a->exp > b->exp) + return 1; + if (a->exp < b->exp) + return -1; + if (a->sig > b->sig) + return 1; + return -(a->sig < b->sig); +} + +sreal a[] = { + { 0, 0 }, + { 1, 0 }, + { 0, 1 }, + { 1, 1 } +}; + +int main() +{ + int i, j; + for (i = 0; i <= 3; i++) { + for (j = 0; j < 3; j++) { + if (i < j && sreal_compare(&a[i], &a[j]) != -1) abort(); + if (i == j && sreal_compare(&a[i], &a[j]) != 0) abort(); + if (i > j && sreal_compare(&a[i], &a[j]) != 1) abort(); + } + } + return 0; +} diff --git a/gcc/testsuite/gcc.c-torture/execute/pr53084.c b/gcc/testsuite/gcc.c-torture/execute/pr53084.c new file mode 100644 index 00000000000..1afc016dfc4 --- /dev/null +++ b/gcc/testsuite/gcc.c-torture/execute/pr53084.c @@ -0,0 +1,18 @@ +/* PR middle-end/53084 */ + +extern void abort (void); + +__attribute__((noinline, noclone)) void +bar (const char *p) +{ + if (p[0] != 'o' || p[1] != 'o' || p[2]) + abort (); +} + +int +main () +{ + static const char *const foo[] = {"foo" + 1}; + bar (foo[0]); + return 0; +} diff --git a/gcc/testsuite/gcc.dg/pr52862.c b/gcc/testsuite/gcc.dg/pr52862.c new file mode 100644 index 00000000000..febe7a8289b --- /dev/null +++ b/gcc/testsuite/gcc.dg/pr52862.c @@ -0,0 +1,9 @@ +/* { dg-do compile } */ +/* { dg-options "-O" } */ + +void ASMAtomicWritePtrVoid(const void *pv); +void rtThreadDestroy(void) +{ + void * const pvTypeChecked = ((void *)0); + ASMAtomicWritePtrVoid((void *)(pvTypeChecked)); +} diff --git a/gcc/testsuite/gcc.dg/stack-usage-1.c b/gcc/testsuite/gcc.dg/stack-usage-1.c index 1d03a8dc994..7de282df26a 100644 --- a/gcc/testsuite/gcc.dg/stack-usage-1.c +++ b/gcc/testsuite/gcc.dg/stack-usage-1.c @@ -41,6 +41,8 @@ # define SIZE 160 /* 256 - 96 bytes for register save area */ #elif defined (__SPU__) # define SIZE 224 +#elif defined (__sh__) +# define SIZE 252 #else # define SIZE 256 #endif diff --git a/gcc/testsuite/gcc.dg/torture/pr51071-2.c b/gcc/testsuite/gcc.dg/torture/pr51071-2.c new file mode 100644 index 00000000000..f66a89f3958 --- /dev/null +++ b/gcc/testsuite/gcc.dg/torture/pr51071-2.c @@ -0,0 +1,38 @@ +/* { dg-do compile } */ +/* { dg-options "-fno-delete-null-pointer-checks" } */ + +extern struct module __this_module; +static inline void +trace_module_get (struct module *mod, unsigned long ip) { } +struct module; +static inline __attribute__((no_instrument_function)) +int try_module_get(struct module *module) +{ + int ret = 1; + if (module) + { + if (module_is_live(module)) + { + __label__ __here; + asm(""); + __here: + trace_module_get(module, (unsigned long)&&__here); + } + else + ret = 0; + } + return ret; +} +struct net_device; +struct net_device_ops { + int (*ndo_open)(struct net_device *dev); +}; +int t3e3_open(struct net_device *dev) +{ + int ret = hdlc_open(dev); + if (ret) + return ret; + try_module_get((&__this_module)); + return 0; +} +const struct net_device_ops t3e3_ops = { .ndo_open = t3e3_open }; diff --git a/gcc/testsuite/gcc.dg/torture/pr51071.c b/gcc/testsuite/gcc.dg/torture/pr51071.c new file mode 100644 index 00000000000..99af9587d05 --- /dev/null +++ b/gcc/testsuite/gcc.dg/torture/pr51071.c @@ -0,0 +1,33 @@ +/* { dg-do compile } */ + +void foo (void); +void bar (void *); +extern int t; + +static void kmalloc_large (int size, int flags) +{ + (void) size; + (void) flags; + foo (); + bar (({__here:&&__here;})); +} + +static void kmalloc (int size, int flags) +{ + if (size) + { + if ((unsigned long) size > 0x1000) + kmalloc_large (size, flags); + + if (flags) + bar (({__here:&&__here;})); + } +} + +void compress_file_range (int i, int j, int k) +{ + int nr_pages = ({j < k;}); + + if (i || t) + kmalloc (0x1000UL * nr_pages, 0x40UL); +} diff --git a/gcc/testsuite/gcc.dg/torture/pr52407.c b/gcc/testsuite/gcc.dg/torture/pr52407.c new file mode 100644 index 00000000000..bb95e51f25b --- /dev/null +++ b/gcc/testsuite/gcc.dg/torture/pr52407.c @@ -0,0 +1,33 @@ +/* { dg-do run } */ + +extern void abort (void); + +typedef long long T; +typedef T vl_t __attribute__((vector_size(2 * sizeof (T)))); + +vl_t ul[4], vl[4] = { { 1, 2 }, { 3, 4 }, { 5, 6 }, { 7, 8 } }; + +static void +mul_vl_l(vl_t *u, vl_t *v, T x, int m) +{ + vl_t w; + T *p = (T *)&w; + p[0] = p[1] = x; + while (m--) + *u++ = *v++ * w; +} + +int +main(int argc, char *argv[]) +{ + int i; + T *pl; + + pl = (T *) &ul; + mul_vl_l(ul, vl, 2, 4); + for (i = 0; i < 8; i++) + if (pl[i] != 2 * (i + 1)) + abort (); + + return 0; +} diff --git a/gcc/testsuite/gcc.target/i386/avx256-unaligned-load-1.c b/gcc/testsuite/gcc.target/i386/avx256-unaligned-load-1.c index 023e859b6c1..c1c7517d711 100644 --- a/gcc/testsuite/gcc.target/i386/avx256-unaligned-load-1.c +++ b/gcc/testsuite/gcc.target/i386/avx256-unaligned-load-1.c @@ -14,6 +14,6 @@ avx_test (void) c[i] = a[i] * b[i+3]; } -/* { dg-final { scan-assembler-not "\\*avx_movups256/1" } } */ -/* { dg-final { scan-assembler "\\*avx_movups/1" } } */ +/* { dg-final { scan-assembler-not "avx_movups256/1" } } */ +/* { dg-final { scan-assembler "avx_movups/1" } } */ /* { dg-final { scan-assembler "vinsertf128" } } */ diff --git a/gcc/testsuite/gcc.target/i386/avx256-unaligned-load-2.c b/gcc/testsuite/gcc.target/i386/avx256-unaligned-load-2.c index 8394e27197b..319cf5e0a01 100644 --- a/gcc/testsuite/gcc.target/i386/avx256-unaligned-load-2.c +++ b/gcc/testsuite/gcc.target/i386/avx256-unaligned-load-2.c @@ -24,6 +24,6 @@ avx_test (void) } } -/* { dg-final { scan-assembler-not "\\*avx_movdqu256/1" } } */ -/* { dg-final { scan-assembler "\\*avx_movdqu/1" } } */ +/* { dg-final { scan-assembler-not "avx_movdqu256/1" } } */ +/* { dg-final { scan-assembler "avx_movdqu/1" } } */ /* { dg-final { scan-assembler "vinsertf128" } } */ diff --git a/gcc/testsuite/gcc.target/i386/avx256-unaligned-load-3.c b/gcc/testsuite/gcc.target/i386/avx256-unaligned-load-3.c index ec7d59d53cc..6ac579aa77c 100644 --- a/gcc/testsuite/gcc.target/i386/avx256-unaligned-load-3.c +++ b/gcc/testsuite/gcc.target/i386/avx256-unaligned-load-3.c @@ -14,6 +14,6 @@ avx_test (void) c[i] = a[i] * b[i+3]; } -/* { dg-final { scan-assembler-not "\\*avx_movupd256/1" } } */ -/* { dg-final { scan-assembler "\\*avx_movupd/1" } } */ +/* { dg-final { scan-assembler-not "avx_movupd256/1" } } */ +/* { dg-final { scan-assembler "avx_movupd/1" } } */ /* { dg-final { scan-assembler "vinsertf128" } } */ diff --git a/gcc/testsuite/gcc.target/i386/avx256-unaligned-load-4.c b/gcc/testsuite/gcc.target/i386/avx256-unaligned-load-4.c index 0d3ef333120..7c015a8b90a 100644 --- a/gcc/testsuite/gcc.target/i386/avx256-unaligned-load-4.c +++ b/gcc/testsuite/gcc.target/i386/avx256-unaligned-load-4.c @@ -14,6 +14,6 @@ avx_test (void) b[i] = a[i+3] * 2; } -/* { dg-final { scan-assembler "\\*avx_movups256/1" } } */ -/* { dg-final { scan-assembler-not "\\*avx_movups/1" } } */ +/* { dg-final { scan-assembler "avx_movups256/1" } } */ +/* { dg-final { scan-assembler-not "avx_movups/1" } } */ /* { dg-final { scan-assembler-not "vinsertf128" } } */ diff --git a/gcc/testsuite/gcc.target/i386/avx256-unaligned-store-1.c b/gcc/testsuite/gcc.target/i386/avx256-unaligned-store-1.c index 99db55c9d0a..cf1944acab2 100644 --- a/gcc/testsuite/gcc.target/i386/avx256-unaligned-store-1.c +++ b/gcc/testsuite/gcc.target/i386/avx256-unaligned-store-1.c @@ -17,6 +17,6 @@ avx_test (void) d[i] = c[i] * 20.0; } -/* { dg-final { scan-assembler-not "\\*avx_movups256/2" } } */ +/* { dg-final { scan-assembler-not "avx_movups256/2" } } */ /* { dg-final { scan-assembler "movups.*\\*avx_movv4sf_internal/3" } } */ /* { dg-final { scan-assembler "vextractf128" } } */ diff --git a/gcc/testsuite/gcc.target/i386/avx256-unaligned-store-2.c b/gcc/testsuite/gcc.target/i386/avx256-unaligned-store-2.c index 38ee9e2a45c..5a10ec3a7fb 100644 --- a/gcc/testsuite/gcc.target/i386/avx256-unaligned-store-2.c +++ b/gcc/testsuite/gcc.target/i386/avx256-unaligned-store-2.c @@ -24,6 +24,6 @@ avx_test (void) } } -/* { dg-final { scan-assembler-not "\\*avx_movdqu256/2" } } */ +/* { dg-final { scan-assembler-not "avx_movdqu256/2" } } */ /* { dg-final { scan-assembler "movdqu.*\\*avx_movv16qi_internal/3" } } */ /* { dg-final { scan-assembler "vextractf128" } } */ diff --git a/gcc/testsuite/gcc.target/i386/avx256-unaligned-store-3.c b/gcc/testsuite/gcc.target/i386/avx256-unaligned-store-3.c index eaab6fd775b..daea7b0ea81 100644 --- a/gcc/testsuite/gcc.target/i386/avx256-unaligned-store-3.c +++ b/gcc/testsuite/gcc.target/i386/avx256-unaligned-store-3.c @@ -17,6 +17,6 @@ avx_test (void) d[i] = c[i] * 20.0; } -/* { dg-final { scan-assembler-not "\\*avx_movupd256/2" } } */ +/* { dg-final { scan-assembler-not "avx_movupd256/2" } } */ /* { dg-final { scan-assembler "movupd.*\\*avx_movv2df_internal/3" } } */ /* { dg-final { scan-assembler "vextractf128" } } */ diff --git a/gcc/testsuite/gcc.target/i386/avx256-unaligned-store-4.c b/gcc/testsuite/gcc.target/i386/avx256-unaligned-store-4.c index 96cca66ae9c..39b6f3bef16 100644 --- a/gcc/testsuite/gcc.target/i386/avx256-unaligned-store-4.c +++ b/gcc/testsuite/gcc.target/i386/avx256-unaligned-store-4.c @@ -14,7 +14,7 @@ avx_test (void) b[i+3] = a[i] * c[i]; } -/* { dg-final { scan-assembler "\\*avx_movups256/2" } } */ -/* { dg-final { scan-assembler-not "\\*avx_movups/2" } } */ +/* { dg-final { scan-assembler "avx_movups256/2" } } */ +/* { dg-final { scan-assembler-not "avx_movups/2" } } */ /* { dg-final { scan-assembler-not "\\*avx_movv4sf_internal/3" } } */ /* { dg-final { scan-assembler-not "vextractf128" } } */ diff --git a/gcc/testsuite/gcc.target/i386/pr53416.c b/gcc/testsuite/gcc.target/i386/pr53416.c new file mode 100644 index 00000000000..68abe8bddbc --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr53416.c @@ -0,0 +1,17 @@ +/* PR target/53416 */ +/* { dg-options "-O2 -mrdrnd" } */ + +int test (void) +{ + unsigned int number = 0; + int result0, result1, result2, result3; + + result0 = __builtin_ia32_rdrand32_step (&number); + result1 = __builtin_ia32_rdrand32_step (&number); + result2 = __builtin_ia32_rdrand32_step (&number); + result3 = __builtin_ia32_rdrand32_step (&number); + + return result0 + result1 +result2 + result3; +} + +/* { dg-final { scan-assembler-times "rdrand" 4 } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/cell_builtin-1.c b/gcc/testsuite/gcc.target/powerpc/cell_builtin-1.c new file mode 100644 index 00000000000..f2bc7ffb3c4 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/cell_builtin-1.c @@ -0,0 +1,48 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-require-effective-target powerpc_altivec_ok } */ +/* { dg-options "-O2 -maltivec -mcpu=cell" } */ +/* { dg-final { scan-assembler-times "lvlx" 19 } } */ + +#include <altivec.h> + +typedef __vector signed char vsc; +typedef __vector signed short vss; +typedef __vector signed int vsi; +typedef __vector unsigned char vuc; +typedef __vector unsigned short vus; +typedef __vector unsigned int vui; +typedef __vector bool char vbc; +typedef __vector bool short vbs; +typedef __vector bool int vbi; +typedef __vector float vsf; +typedef __vector pixel vp; +typedef signed char sc; +typedef signed short ss; +typedef signed int si; +typedef signed long sl; +typedef unsigned char uc; +typedef unsigned short us; +typedef unsigned int ui; +typedef unsigned long ul; +typedef float sf; + +vsc lc1(long a, void *p) { return __builtin_altivec_lvlx (a,p); } +vsf llx01(long a, vsf *p) { return __builtin_vec_lvlx (a,p); } +vsf llx02(long a, sf *p) { return __builtin_vec_lvlx (a,p); } +vbi llx03(long a, vbi *p) { return __builtin_vec_lvlx (a,p); } +vsi llx04(long a, vsi *p) { return __builtin_vec_lvlx (a,p); } +vsi llx05(long a, si *p) { return __builtin_vec_lvlx (a,p); } +vui llx06(long a, vui *p) { return __builtin_vec_lvlx (a,p); } +vui llx07(long a, ui *p) { return __builtin_vec_lvlx (a,p); } +vbs llx08(long a, vbs *p) { return __builtin_vec_lvlx (a,p); } +vp llx09(long a, vp *p) { return __builtin_vec_lvlx (a,p); } +vss llx10(long a, vss *p) { return __builtin_vec_lvlx (a,p); } +vss llx11(long a, ss *p) { return __builtin_vec_lvlx (a,p); } +vus llx12(long a, vus *p) { return __builtin_vec_lvlx (a,p); } +vus llx13(long a, us *p) { return __builtin_vec_lvlx (a,p); } +vbc llx14(long a, vbc *p) { return __builtin_vec_lvlx (a,p); } +vsc llx15(long a, vsc *p) { return __builtin_vec_lvlx (a,p); } +vsc llx16(long a, sc *p) { return __builtin_vec_lvlx (a,p); } +vuc llx17(long a, vuc *p) { return __builtin_vec_lvlx (a,p); } +vuc llx18(long a, uc *p) { return __builtin_vec_lvlx (a,p); } diff --git a/gcc/testsuite/gcc.target/powerpc/cell_builtin-2.c b/gcc/testsuite/gcc.target/powerpc/cell_builtin-2.c new file mode 100644 index 00000000000..220be571659 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/cell_builtin-2.c @@ -0,0 +1,48 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-require-effective-target powerpc_altivec_ok } */ +/* { dg-options "-O2 -maltivec -mcpu=cell" } */ +/* { dg-final { scan-assembler-times "lvlxl" 19 } } */ + +#include <altivec.h> + +typedef __vector signed char vsc; +typedef __vector signed short vss; +typedef __vector signed int vsi; +typedef __vector unsigned char vuc; +typedef __vector unsigned short vus; +typedef __vector unsigned int vui; +typedef __vector bool char vbc; +typedef __vector bool short vbs; +typedef __vector bool int vbi; +typedef __vector float vsf; +typedef __vector pixel vp; +typedef signed char sc; +typedef signed short ss; +typedef signed int si; +typedef signed long sl; +typedef unsigned char uc; +typedef unsigned short us; +typedef unsigned int ui; +typedef unsigned long ul; +typedef float sf; + +vsc lc2(long a, void *p) { return __builtin_altivec_lvlxl (a,p); } +vsf llxl01(long a, vsf *p) { return __builtin_vec_lvlxl (a,p); } +vsf llxl02(long a, sf *p) { return __builtin_vec_lvlxl (a,p); } +vbi llxl03(long a, vbi *p) { return __builtin_vec_lvlxl (a,p); } +vsi llxl04(long a, vsi *p) { return __builtin_vec_lvlxl (a,p); } +vsi llxl05(long a, si *p) { return __builtin_vec_lvlxl (a,p); } +vui llxl06(long a, vui *p) { return __builtin_vec_lvlxl (a,p); } +vui llxl07(long a, ui *p) { return __builtin_vec_lvlxl (a,p); } +vbs llxl08(long a, vbs *p) { return __builtin_vec_lvlxl (a,p); } +vp llxl09(long a, vp *p) { return __builtin_vec_lvlxl (a,p); } +vss llxl10(long a, vss *p) { return __builtin_vec_lvlxl (a,p); } +vss llxl11(long a, ss *p) { return __builtin_vec_lvlxl (a,p); } +vus llxl12(long a, vus *p) { return __builtin_vec_lvlxl (a,p); } +vus llxl13(long a, us *p) { return __builtin_vec_lvlxl (a,p); } +vbc llxl14(long a, vbc *p) { return __builtin_vec_lvlxl (a,p); } +vsc llxl15(long a, vsc *p) { return __builtin_vec_lvlxl (a,p); } +vsc llxl16(long a, sc *p) { return __builtin_vec_lvlxl (a,p); } +vuc llxl17(long a, vuc *p) { return __builtin_vec_lvlxl (a,p); } +vuc llxl18(long a, uc *p) { return __builtin_vec_lvlxl (a,p); } diff --git a/gcc/testsuite/gcc.target/powerpc/cell_builtin-3.c b/gcc/testsuite/gcc.target/powerpc/cell_builtin-3.c new file mode 100644 index 00000000000..4b437291ea5 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/cell_builtin-3.c @@ -0,0 +1,48 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-require-effective-target powerpc_altivec_ok } */ +/* { dg-options "-O2 -maltivec -mcpu=cell" } */ +/* { dg-final { scan-assembler-times "lvrx" 19 } } */ + +#include <altivec.h> + +typedef __vector signed char vsc; +typedef __vector signed short vss; +typedef __vector signed int vsi; +typedef __vector unsigned char vuc; +typedef __vector unsigned short vus; +typedef __vector unsigned int vui; +typedef __vector bool char vbc; +typedef __vector bool short vbs; +typedef __vector bool int vbi; +typedef __vector float vsf; +typedef __vector pixel vp; +typedef signed char sc; +typedef signed short ss; +typedef signed int si; +typedef signed long sl; +typedef unsigned char uc; +typedef unsigned short us; +typedef unsigned int ui; +typedef unsigned long ul; +typedef float sf; + +vsc lc3(long a, void *p) { return __builtin_altivec_lvrx (a,p); } +vsf lrx01(long a, vsf *p) { return __builtin_vec_lvrx (a,p); } +vsf lrx02(long a, sf *p) { return __builtin_vec_lvrx (a,p); } +vbi lrx03(long a, vbi *p) { return __builtin_vec_lvrx (a,p); } +vsi lrx04(long a, vsi *p) { return __builtin_vec_lvrx (a,p); } +vsi lrx05(long a, si *p) { return __builtin_vec_lvrx (a,p); } +vui lrx06(long a, vui *p) { return __builtin_vec_lvrx (a,p); } +vui lrx07(long a, ui *p) { return __builtin_vec_lvrx (a,p); } +vbs lrx08(long a, vbs *p) { return __builtin_vec_lvrx (a,p); } +vp lrx09(long a, vp *p) { return __builtin_vec_lvrx (a,p); } +vss lrx10(long a, vss *p) { return __builtin_vec_lvrx (a,p); } +vss lrx11(long a, ss *p) { return __builtin_vec_lvrx (a,p); } +vus lrx12(long a, vus *p) { return __builtin_vec_lvrx (a,p); } +vus lrx13(long a, us *p) { return __builtin_vec_lvrx (a,p); } +vbc lrx14(long a, vbc *p) { return __builtin_vec_lvrx (a,p); } +vsc lrx15(long a, vsc *p) { return __builtin_vec_lvrx (a,p); } +vsc lrx16(long a, sc *p) { return __builtin_vec_lvrx (a,p); } +vuc lrx17(long a, vuc *p) { return __builtin_vec_lvrx (a,p); } +vuc lrx18(long a, uc *p) { return __builtin_vec_lvrx (a,p); } diff --git a/gcc/testsuite/gcc.target/powerpc/cell_builtin-4.c b/gcc/testsuite/gcc.target/powerpc/cell_builtin-4.c new file mode 100644 index 00000000000..d73328ac43e --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/cell_builtin-4.c @@ -0,0 +1,48 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-require-effective-target powerpc_altivec_ok } */ +/* { dg-options "-O2 -maltivec -mcpu=cell" } */ +/* { dg-final { scan-assembler-times "lvrxl" 19 } } */ + +#include <altivec.h> + +typedef __vector signed char vsc; +typedef __vector signed short vss; +typedef __vector signed int vsi; +typedef __vector unsigned char vuc; +typedef __vector unsigned short vus; +typedef __vector unsigned int vui; +typedef __vector bool char vbc; +typedef __vector bool short vbs; +typedef __vector bool int vbi; +typedef __vector float vsf; +typedef __vector pixel vp; +typedef signed char sc; +typedef signed short ss; +typedef signed int si; +typedef signed long sl; +typedef unsigned char uc; +typedef unsigned short us; +typedef unsigned int ui; +typedef unsigned long ul; +typedef float sf; + +vsc lc4(long a, void *p) { return __builtin_altivec_lvrxl (a,p); } +vsf lrxl01(long a, vsf *p) { return __builtin_vec_lvrxl (a,p); } +vsf lrxl02(long a, sf *p) { return __builtin_vec_lvrxl (a,p); } +vbi lrxl03(long a, vbi *p) { return __builtin_vec_lvrxl (a,p); } +vsi lrxl04(long a, vsi *p) { return __builtin_vec_lvrxl (a,p); } +vsi lrxl05(long a, si *p) { return __builtin_vec_lvrxl (a,p); } +vui lrxl06(long a, vui *p) { return __builtin_vec_lvrxl (a,p); } +vui lrxl07(long a, ui *p) { return __builtin_vec_lvrxl (a,p); } +vbs lrxl08(long a, vbs *p) { return __builtin_vec_lvrxl (a,p); } +vp lrxl09(long a, vp *p) { return __builtin_vec_lvrxl (a,p); } +vss lrxl10(long a, vss *p) { return __builtin_vec_lvrxl (a,p); } +vss lrxl11(long a, ss *p) { return __builtin_vec_lvrxl (a,p); } +vus lrxl12(long a, vus *p) { return __builtin_vec_lvrxl (a,p); } +vus lrxl13(long a, us *p) { return __builtin_vec_lvrxl (a,p); } +vbc lrxl14(long a, vbc *p) { return __builtin_vec_lvrxl (a,p); } +vsc lrxl15(long a, vsc *p) { return __builtin_vec_lvrxl (a,p); } +vsc lrxl16(long a, sc *p) { return __builtin_vec_lvrxl (a,p); } +vuc lrxl17(long a, vuc *p) { return __builtin_vec_lvrxl (a,p); } +vuc lrxl18(long a, uc *p) { return __builtin_vec_lvrxl (a,p); } diff --git a/gcc/testsuite/gcc.target/powerpc/cell_builtin-5.c b/gcc/testsuite/gcc.target/powerpc/cell_builtin-5.c new file mode 100644 index 00000000000..cc6adba8050 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/cell_builtin-5.c @@ -0,0 +1,48 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-require-effective-target powerpc_altivec_ok } */ +/* { dg-options "-O2 -maltivec -mcpu=cell" } */ +/* { dg-final { scan-assembler-times "stvlx" 19 } } */ + +#include <altivec.h> + +typedef __vector signed char vsc; +typedef __vector signed short vss; +typedef __vector signed int vsi; +typedef __vector unsigned char vuc; +typedef __vector unsigned short vus; +typedef __vector unsigned int vui; +typedef __vector bool char vbc; +typedef __vector bool short vbs; +typedef __vector bool int vbi; +typedef __vector float vsf; +typedef __vector pixel vp; +typedef signed char sc; +typedef signed short ss; +typedef signed int si; +typedef signed long sl; +typedef unsigned char uc; +typedef unsigned short us; +typedef unsigned int ui; +typedef unsigned long ul; +typedef float sf; + +void sc1(vsc v, long a, void *p) { __builtin_altivec_stvlx (v,a,p); } +void slx01(vsf v, long a, vsf *p) { __builtin_vec_stvlx (v,a,p); } +void slx02(vsf v, long a, sf *p) { __builtin_vec_stvlx (v,a,p); } +void slx03(vbi v, long a, vbi *p) { __builtin_vec_stvlx (v,a,p); } +void slx04(vsi v, long a, vsi *p) { __builtin_vec_stvlx (v,a,p); } +void slx05(vsi v, long a, si *p) { __builtin_vec_stvlx (v,a,p); } +void slx06(vui v, long a, vui *p) { __builtin_vec_stvlx (v,a,p); } +void slx07(vui v, long a, ui *p) { __builtin_vec_stvlx (v,a,p); } +void slx08(vbs v, long a, vbs *p) { __builtin_vec_stvlx (v,a,p); } +void slx09(vp v, long a, vp *p) { __builtin_vec_stvlx (v,a,p); } +void slx10(vss v, long a, vss *p) { __builtin_vec_stvlx (v,a,p); } +void slx11(vss v, long a, ss *p) { __builtin_vec_stvlx (v,a,p); } +void slx12(vus v, long a, vus *p) { __builtin_vec_stvlx (v,a,p); } +void slx13(vus v, long a, us *p) { __builtin_vec_stvlx (v,a,p); } +void slx14(vbc v, long a, vbc *p) { __builtin_vec_stvlx (v,a,p); } +void slx15(vsc v, long a, vsc *p) { __builtin_vec_stvlx (v,a,p); } +void slx16(vsc v, long a, sc *p) { __builtin_vec_stvlx (v,a,p); } +void slx17(vuc v, long a, vuc *p) { __builtin_vec_stvlx (v,a,p); } +void slx18(vuc v, long a, uc *p) { __builtin_vec_stvlx (v,a,p); } diff --git a/gcc/testsuite/gcc.target/powerpc/cell_builtin-6.c b/gcc/testsuite/gcc.target/powerpc/cell_builtin-6.c new file mode 100644 index 00000000000..9c748d973d8 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/cell_builtin-6.c @@ -0,0 +1,48 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-require-effective-target powerpc_altivec_ok } */ +/* { dg-options "-O2 -maltivec -mcpu=cell" } */ +/* { dg-final { scan-assembler-times "stvlxl" 19 } } */ + +#include <altivec.h> + +typedef __vector signed char vsc; +typedef __vector signed short vss; +typedef __vector signed int vsi; +typedef __vector unsigned char vuc; +typedef __vector unsigned short vus; +typedef __vector unsigned int vui; +typedef __vector bool char vbc; +typedef __vector bool short vbs; +typedef __vector bool int vbi; +typedef __vector float vsf; +typedef __vector pixel vp; +typedef signed char sc; +typedef signed short ss; +typedef signed int si; +typedef signed long sl; +typedef unsigned char uc; +typedef unsigned short us; +typedef unsigned int ui; +typedef unsigned long ul; +typedef float sf; + +void sc2(vsc v, long a, void *p) { __builtin_altivec_stvlxl (v,a,p); } +void slxl01(vsf v, long a, vsf *p) { __builtin_vec_stvlxl (v,a,p); } +void slxl02(vsf v, long a, sf *p) { __builtin_vec_stvlxl (v,a,p); } +void slxl03(vbi v, long a, vbi *p) { __builtin_vec_stvlxl (v,a,p); } +void slxl04(vsi v, long a, vsi *p) { __builtin_vec_stvlxl (v,a,p); } +void slxl05(vsi v, long a, si *p) { __builtin_vec_stvlxl (v,a,p); } +void slxl06(vui v, long a, vui *p) { __builtin_vec_stvlxl (v,a,p); } +void slxl07(vui v, long a, ui *p) { __builtin_vec_stvlxl (v,a,p); } +void slxl08(vbs v, long a, vbs *p) { __builtin_vec_stvlxl (v,a,p); } +void slxl09(vp v, long a, vp *p) { __builtin_vec_stvlxl (v,a,p); } +void slxl10(vss v, long a, vss *p) { __builtin_vec_stvlxl (v,a,p); } +void slxl11(vss v, long a, ss *p) { __builtin_vec_stvlxl (v,a,p); } +void slxl12(vus v, long a, vus *p) { __builtin_vec_stvlxl (v,a,p); } +void slxl13(vus v, long a, us *p) { __builtin_vec_stvlxl (v,a,p); } +void slxl14(vbc v, long a, vbc *p) { __builtin_vec_stvlxl (v,a,p); } +void slxl15(vsc v, long a, vsc *p) { __builtin_vec_stvlxl (v,a,p); } +void slxl16(vsc v, long a, sc *p) { __builtin_vec_stvlxl (v,a,p); } +void slxl17(vuc v, long a, vuc *p) { __builtin_vec_stvlxl (v,a,p); } +void slxl18(vuc v, long a, uc *p) { __builtin_vec_stvlxl (v,a,p); } diff --git a/gcc/testsuite/gcc.target/powerpc/cell_builtin-7.c b/gcc/testsuite/gcc.target/powerpc/cell_builtin-7.c new file mode 100644 index 00000000000..abdb3b0caf1 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/cell_builtin-7.c @@ -0,0 +1,48 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-require-effective-target powerpc_altivec_ok } */ +/* { dg-options "-O2 -maltivec -mcpu=cell" } */ +/* { dg-final { scan-assembler-times "stvrx" 19 } } */ + +#include <altivec.h> + +typedef __vector signed char vsc; +typedef __vector signed short vss; +typedef __vector signed int vsi; +typedef __vector unsigned char vuc; +typedef __vector unsigned short vus; +typedef __vector unsigned int vui; +typedef __vector bool char vbc; +typedef __vector bool short vbs; +typedef __vector bool int vbi; +typedef __vector float vsf; +typedef __vector pixel vp; +typedef signed char sc; +typedef signed short ss; +typedef signed int si; +typedef signed long sl; +typedef unsigned char uc; +typedef unsigned short us; +typedef unsigned int ui; +typedef unsigned long ul; +typedef float sf; + +void sc3(vsc v, long a, void *p) { __builtin_altivec_stvrx (v,a,p); } +void srx01(vsf v, long a, vsf *p) { __builtin_vec_stvrx (v,a,p); } +void srx02(vsf v, long a, sf *p) { __builtin_vec_stvrx (v,a,p); } +void srx03(vbi v, long a, vbi *p) { __builtin_vec_stvrx (v,a,p); } +void srx04(vsi v, long a, vsi *p) { __builtin_vec_stvrx (v,a,p); } +void srx05(vsi v, long a, si *p) { __builtin_vec_stvrx (v,a,p); } +void srx06(vui v, long a, vui *p) { __builtin_vec_stvrx (v,a,p); } +void srx07(vui v, long a, ui *p) { __builtin_vec_stvrx (v,a,p); } +void srx08(vbs v, long a, vbs *p) { __builtin_vec_stvrx (v,a,p); } +void srx09(vp v, long a, vp *p) { __builtin_vec_stvrx (v,a,p); } +void srx10(vss v, long a, vss *p) { __builtin_vec_stvrx (v,a,p); } +void srx11(vss v, long a, ss *p) { __builtin_vec_stvrx (v,a,p); } +void srx12(vus v, long a, vus *p) { __builtin_vec_stvrx (v,a,p); } +void srx13(vus v, long a, us *p) { __builtin_vec_stvrx (v,a,p); } +void srx14(vbc v, long a, vbc *p) { __builtin_vec_stvrx (v,a,p); } +void srx15(vsc v, long a, vsc *p) { __builtin_vec_stvrx (v,a,p); } +void srx16(vsc v, long a, sc *p) { __builtin_vec_stvrx (v,a,p); } +void srx17(vuc v, long a, vuc *p) { __builtin_vec_stvrx (v,a,p); } +void srx18(vuc v, long a, uc *p) { __builtin_vec_stvrx (v,a,p); } diff --git a/gcc/testsuite/gcc.target/powerpc/cell_builtin-8.c b/gcc/testsuite/gcc.target/powerpc/cell_builtin-8.c new file mode 100644 index 00000000000..ec7fc3031b4 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/cell_builtin-8.c @@ -0,0 +1,48 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-require-effective-target powerpc_altivec_ok } */ +/* { dg-options "-O2 -maltivec -mcpu=cell" } */ +/* { dg-final { scan-assembler-times "stvrxl" 19 } } */ + +#include <altivec.h> + +typedef __vector signed char vsc; +typedef __vector signed short vss; +typedef __vector signed int vsi; +typedef __vector unsigned char vuc; +typedef __vector unsigned short vus; +typedef __vector unsigned int vui; +typedef __vector bool char vbc; +typedef __vector bool short vbs; +typedef __vector bool int vbi; +typedef __vector float vsf; +typedef __vector pixel vp; +typedef signed char sc; +typedef signed short ss; +typedef signed int si; +typedef signed long sl; +typedef unsigned char uc; +typedef unsigned short us; +typedef unsigned int ui; +typedef unsigned long ul; +typedef float sf; + +void sc4(vsc v, long a, void *p) { __builtin_altivec_stvrxl (v,a,p); } +void srxl01(vsf v, long a, vsf *p) { __builtin_vec_stvrxl (v,a,p); } +void srxl02(vsf v, long a, sf *p) { __builtin_vec_stvrxl (v,a,p); } +void srxl03(vbi v, long a, vbi *p) { __builtin_vec_stvrxl (v,a,p); } +void srxl04(vsi v, long a, vsi *p) { __builtin_vec_stvrxl (v,a,p); } +void srxl05(vsi v, long a, si *p) { __builtin_vec_stvrxl (v,a,p); } +void srxl06(vui v, long a, vui *p) { __builtin_vec_stvrxl (v,a,p); } +void srxl07(vui v, long a, ui *p) { __builtin_vec_stvrxl (v,a,p); } +void srxl08(vbs v, long a, vbs *p) { __builtin_vec_stvrxl (v,a,p); } +void srxl09(vp v, long a, vp *p) { __builtin_vec_stvrxl (v,a,p); } +void srxl10(vss v, long a, vss *p) { __builtin_vec_stvrxl (v,a,p); } +void srxl11(vss v, long a, ss *p) { __builtin_vec_stvrxl (v,a,p); } +void srxl12(vus v, long a, vus *p) { __builtin_vec_stvrxl (v,a,p); } +void srxl13(vus v, long a, us *p) { __builtin_vec_stvrxl (v,a,p); } +void srxl14(vbc v, long a, vbc *p) { __builtin_vec_stvrxl (v,a,p); } +void srxl15(vsc v, long a, vsc *p) { __builtin_vec_stvrxl (v,a,p); } +void srxl16(vsc v, long a, sc *p) { __builtin_vec_stvrxl (v,a,p); } +void srxl17(vuc v, long a, vuc *p) { __builtin_vec_stvrxl (v,a,p); } +void srxl18(vuc v, long a, uc *p) { __builtin_vec_stvrxl (v,a,p); } diff --git a/gcc/testsuite/gcc.target/powerpc/pr52775.c b/gcc/testsuite/gcc.target/powerpc/pr52775.c new file mode 100644 index 00000000000..4027819ee63 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/pr52775.c @@ -0,0 +1,16 @@ +/* { dg-do compile { target { powerpc*-*-* && ilp32 } } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-options "-O1 -mcpu=power4" } */ +/* { dg-final { scan-assembler-times "fcfid" 2 } } */ + +double +int_to_double (int *p) +{ + return (double)*p; +} + +double +long_long_to_double (long long *p) +{ + return (double)*p; +} diff --git a/gcc/testsuite/gcc.target/powerpc/pr53199.c b/gcc/testsuite/gcc.target/powerpc/pr53199.c new file mode 100644 index 00000000000..89a0cad06fe --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/pr53199.c @@ -0,0 +1,50 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-options "-O2 -mcpu=power6 -mavoid-indexed-addresses" } */ +/* { dg-final { scan-assembler-times "lwbrx" 6 } } */ +/* { dg-final { scan-assembler-times "stwbrx" 6 } } */ + +/* PR 51399: bswap gets an error if -mavoid-indexed-addresses was used in + creating the two lwbrx instructions. */ + +long long +load64_reverse_1 (long long *p) +{ + return __builtin_bswap64 (*p); +} + +long long +load64_reverse_2 (long long *p) +{ + return __builtin_bswap64 (p[1]); +} + +long long +load64_reverse_3 (long long *p, int i) +{ + return __builtin_bswap64 (p[i]); +} + +void +store64_reverse_1 (long long *p, long long x) +{ + *p = __builtin_bswap64 (x); +} + +void +store64_reverse_2 (long long *p, long long x) +{ + p[1] = __builtin_bswap64 (x); +} + +void +store64_reverse_3 (long long *p, long long x, int i) +{ + p[i] = __builtin_bswap64 (x); +} + +long long +reg_reverse (long long x) +{ + return __builtin_bswap64 (x); +} diff --git a/gcc/testsuite/gfortran.dg/init_flag_10.f90 b/gcc/testsuite/gfortran.dg/init_flag_10.f90 new file mode 100644 index 00000000000..826a34b81ea --- /dev/null +++ b/gcc/testsuite/gfortran.dg/init_flag_10.f90 @@ -0,0 +1,43 @@ +! { dg-do run } +! { dg-options "-finit-real=NAN" } +! { dg-add-options ieee } +! { dg-skip-if "NaN not supported" { spu-*-* } { "*" } { "" } } +! +! PR fortran/50619 +! +! Contributed by Fred Krogh +! +! The NaN initialization used to set the associate name to NaN! +! + +module testa2 +type, public :: test_ty + real :: rmult = 1.0e0 +end type test_ty + +contains + subroutine test(e, var1) + type(test_ty) :: e + real :: var1, var2 ! Should get NaN initialized + + ! Should be the default value + if (e%rmult /= 1.0) call abort () + + ! Check that NaN initialization is really turned on + if (var1 == var1) call abort () + if (var2 == var2) call abort () + + ! The following was failing: + associate (rmult=>e%rmult) + if (e%rmult /= 1.0) call abort () + end associate + end subroutine test +end module testa2 + +program testa1 + use testa2 + type(test_ty) :: e + real :: var1 ! Should get NaN initialized + call test(e, var1) + stop +end program testa1 diff --git a/gcc/testsuite/gfortran.dg/pointer_intent_6.f90 b/gcc/testsuite/gfortran.dg/pointer_intent_6.f90 new file mode 100644 index 00000000000..56c7de5ebba --- /dev/null +++ b/gcc/testsuite/gfortran.dg/pointer_intent_6.f90 @@ -0,0 +1,19 @@ +! { dg-do compile } +! +! PR fortran/52864 +! +! Assigning to an intent(in) pointer (which is valid). +! + program test + type PoisFFT_Solver3D + complex, dimension(:,:,:), & + pointer :: work => null() + end type PoisFFT_Solver3D + contains + subroutine PoisFFT_Solver3D_FullPeriodic(D, p) + type(PoisFFT_Solver3D), intent(in) :: D + real, intent(in), pointer :: p(:) + D%work(i,j,k) = 0.0 + p = 0.0 + end subroutine + end diff --git a/gcc/testsuite/gfortran.dg/realloc_on_assign_15.f90 b/gcc/testsuite/gfortran.dg/realloc_on_assign_15.f90 new file mode 100644 index 00000000000..2a0e5be9101 --- /dev/null +++ b/gcc/testsuite/gfortran.dg/realloc_on_assign_15.f90 @@ -0,0 +1,40 @@ +! { dg-do run } +! +! PR fortran/53389 +! +! The program was leaking memory before due to +! realloc on assignment and nested functions. +! +module foo + implicit none + contains + + function filler(array, val) + real, dimension(:), intent(in):: array + real, dimension(size(array)):: filler + real, intent(in):: val + + filler=val + + end function filler +end module + +program test + use foo + implicit none + + real, dimension(:), allocatable:: x, y + integer, parameter:: N=1000 !*1000 + integer:: i + +! allocate( x(N) ) + allocate( y(N) ) + y=0.0 + + do i=1, N +! print *,i + x=filler(filler(y, real(2*i)), real(i)) + y=y+x + end do + +end program test diff --git a/gcc/testsuite/gfortran.dg/save_4.f90 b/gcc/testsuite/gfortran.dg/save_4.f90 new file mode 100644 index 00000000000..74ea6e83531 --- /dev/null +++ b/gcc/testsuite/gfortran.dg/save_4.f90 @@ -0,0 +1,13 @@ +! { dg-do compile } +! { dg-options "-std=f2003" } +! +! PR fortran/53597 +! +MODULE somemodule + IMPLICIT NONE + TYPE sometype + INTEGER :: i + DOUBLE PRECISION, POINTER, DIMENSION(:,:) :: coef => NULL() + END TYPE sometype + TYPE(sometype) :: somevariable ! { dg-error "Fortran 2008: Implied SAVE for module variable 'somevariable' at .1., needed due to the default initialization" } +END MODULE somemodule |