diff options
Diffstat (limited to 'gcc/testsuite/gcc.target')
58 files changed, 990 insertions, 7 deletions
diff --git a/gcc/testsuite/gcc.target/aarch64/extr.c b/gcc/testsuite/gcc.target/aarch64/extr.c new file mode 100644 index 00000000000..a78dd8d607b --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/extr.c @@ -0,0 +1,34 @@ +/* { dg-options "-O2 --save-temps" } */ +/* { dg-do run } */ + +extern void abort (void); + +int +test_si (int a, int b) +{ + /* { dg-final { scan-assembler "extr\tw\[0-9\]+, w\[0-9\]+, w\[0-9\]+, 27\n" } } */ + return (a << 5) | ((unsigned int) b >> 27); +} + +long long +test_di (long long a, long long b) +{ + /* { dg-final { scan-assembler "extr\tx\[0-9\]+, x\[0-9\]+, x\[0-9\]+, 45\n" } } */ + return (a << 19) | ((unsigned long long) b >> 45); +} + +int +main () +{ + int v; + long long w; + v = test_si (0x00000004, 0x30000000); + if (v != 0x00000086) + abort(); + w = test_di (0x0001040040040004ll, 0x0070050066666666ll); + if (w != 0x2002002000200380ll) + abort(); + return 0; +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/movk.c b/gcc/testsuite/gcc.target/aarch64/movk.c new file mode 100644 index 00000000000..e4b22098c44 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/movk.c @@ -0,0 +1,31 @@ +/* { dg-do run } */ +/* { dg-options "-O2 --save-temps -fno-inline" } */ + +extern void abort (void); + +long long int +dummy_number_generator () +{ + /* { dg-final { scan-assembler "movk\tx\[0-9\]+, 0xefff, lsl 16" } } */ + /* { dg-final { scan-assembler "movk\tx\[0-9\]+, 0xc4cc, lsl 32" } } */ + /* { dg-final { scan-assembler "movk\tx\[0-9\]+, 0xfffe, lsl 48" } } */ + return -346565474575675; +} + +int +main (void) +{ + + long long int num = dummy_number_generator (); + if (num > 0) + abort (); + + /* { dg-final { scan-assembler "movk\tx\[0-9\]+, 0x4667, lsl 16" } } */ + /* { dg-final { scan-assembler "movk\tx\[0-9\]+, 0x7a3d, lsl 32" } } */ + if (num / 69313094915135 != -5) + abort (); + + return 0; +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/ror.c b/gcc/testsuite/gcc.target/aarch64/ror.c new file mode 100644 index 00000000000..4d266f00471 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/ror.c @@ -0,0 +1,34 @@ +/* { dg-options "-O2 --save-temps" } */ +/* { dg-do run } */ + +extern void abort (void); + +int +test_si (int a) +{ + /* { dg-final { scan-assembler "ror\tw\[0-9\]+, w\[0-9\]+, 27\n" } } */ + return (a << 5) | ((unsigned int) a >> 27); +} + +long long +test_di (long long a) +{ + /* { dg-final { scan-assembler "ror\tx\[0-9\]+, x\[0-9\]+, 45\n" } } */ + return (a << 19) | ((unsigned long long) a >> 45); +} + +int +main () +{ + int v; + long long w; + v = test_si (0x0203050); + if (v != 0x4060a00) + abort(); + w = test_di (0x0000020506010304ll); + if (w != 0x1028300818200000ll) + abort(); + return 0; +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/sbc.c b/gcc/testsuite/gcc.target/aarch64/sbc.c new file mode 100644 index 00000000000..e479910bc2c --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sbc.c @@ -0,0 +1,41 @@ +/* { dg-do run } */ +/* { dg-options "-O2 --save-temps" } */ + +extern void abort (void); + +typedef unsigned int u32int; +typedef unsigned long long u64int; + +u32int +test_si (u32int w1, u32int w2, u32int w3, u32int w4) +{ + u32int w0; + /* { dg-final { scan-assembler "sbc\tw\[0-9\]+, w\[0-9\]+, w\[0-9\]+\n" } } */ + w0 = w1 - w2 - (w3 < w4); + return w0; +} + +u64int +test_di (u64int x1, u64int x2, u64int x3, u64int x4) +{ + u64int x0; + /* { dg-final { scan-assembler "sbc\tx\[0-9\]+, x\[0-9\]+, x\[0-9\]+\n" } } */ + x0 = x1 - x2 - (x3 < x4); + return x0; +} + +int +main () +{ + u32int x; + u64int y; + x = test_si (7, 8, 12, 15); + if (x != -2) + abort(); + y = test_di (0x987654321ll, 0x123456789ll, 0x345345345ll, 0x123123123ll); + if (y != 0x8641fdb98ll) + abort(); + return 0; +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/vect-compile.c b/gcc/testsuite/gcc.target/aarch64/vect-compile.c index 260c1e041c0..33130aab55d 100644 --- a/gcc/testsuite/gcc.target/aarch64/vect-compile.c +++ b/gcc/testsuite/gcc.target/aarch64/vect-compile.c @@ -16,5 +16,7 @@ /* { dg-final { scan-assembler "uminv" } } */ /* { dg-final { scan-assembler "smaxv" } } */ /* { dg-final { scan-assembler "sminv" } } */ +/* { dg-final { scan-assembler "sabd" } } */ +/* { dg-final { scan-assembler "saba" } } */ /* { dg-final { scan-assembler-times "addv" 2} } */ /* { dg-final { scan-assembler-times "addp" 2} } */ diff --git a/gcc/testsuite/gcc.target/aarch64/vect-fp-compile.c b/gcc/testsuite/gcc.target/aarch64/vect-fp-compile.c index b953dfae3b8..47ef100e87b 100644 --- a/gcc/testsuite/gcc.target/aarch64/vect-fp-compile.c +++ b/gcc/testsuite/gcc.target/aarch64/vect-fp-compile.c @@ -11,3 +11,4 @@ /* { dg-final { scan-assembler "fdiv\\tv" } } */ /* { dg-final { scan-assembler "fneg\\tv" } } */ /* { dg-final { scan-assembler "fabs\\tv" } } */ +/* { dg-final { scan-assembler "fabd\\tv" } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/vect-fp.c b/gcc/testsuite/gcc.target/aarch64/vect-fp.c index a7357b7f065..bcf9d9d7530 100644 --- a/gcc/testsuite/gcc.target/aarch64/vect-fp.c +++ b/gcc/testsuite/gcc.target/aarch64/vect-fp.c @@ -117,6 +117,16 @@ int main (void) 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0 }; + F32 fabd_F32_vector[] = { 1.0f, 1.0f, 1.0f, 1.0f, + 1.0f, 1.0f, 1.0f, 1.0f, + 1.0f, 1.0f, 1.0f, 1.0f, + 1.0f, 1.0f, 1.0f, 1.0f }; + + F64 fabd_F64_vector[] = { 1.0, 1.0, 1.0, 1.0, + 1.0, 1.0, 1.0, 1.0, + 1.0, 1.0, 1.0, 1.0, + 1.0, 1.0, 1.0, 1.0 }; + /* Setup input vectors. */ for (i=1; i<=16; i++) { @@ -132,6 +142,7 @@ int main (void) TEST (div, 3); TEST (neg, 2); TEST (abs, 2); + TEST (fabd, 3); return 0; } diff --git a/gcc/testsuite/gcc.target/aarch64/vect-fp.x b/gcc/testsuite/gcc.target/aarch64/vect-fp.x index 338f6edf945..82d1b1c50ee 100644 --- a/gcc/testsuite/gcc.target/aarch64/vect-fp.x +++ b/gcc/testsuite/gcc.target/aarch64/vect-fp.x @@ -7,13 +7,23 @@ typedef double *__restrict__ pRF64; extern float fabsf (float); extern double fabs (double); +#define DEF3a(fname, type, op) \ + void fname##_##type (pR##type a, \ + pR##type b, \ + pR##type c) \ + { \ + int i; \ + for (i = 0; i < 16; i++) \ + a[i] = op (b[i] - c[i]); \ + } + #define DEF3(fname, type, op) \ void fname##_##type (pR##type a, \ pR##type b, \ pR##type c) \ { \ int i; \ - for (i=0; i<16; i++) \ + for (i = 0; i < 16; i++) \ a[i] = b[i] op c[i]; \ } @@ -22,11 +32,15 @@ extern double fabs (double); pR##type b) \ { \ int i; \ - for (i=0; i<16; i++) \ + for (i = 0; i < 16; i++) \ a[i] = op(b[i]); \ } +#define DEFN3a(fname, op) \ + DEF3a (fname, F32, op) \ + DEF3a (fname, F64, op) + #define DEFN3(fname, op) \ DEF3 (fname, F32, op) \ DEF3 (fname, F64, op) @@ -42,3 +56,5 @@ DEFN3 (div, /) DEFN2 (neg, -) DEF2 (abs, F32, fabsf) DEF2 (abs, F64, fabs) +DEF3a (fabd, F32, fabsf) +DEF3a (fabd, F64, fabs) diff --git a/gcc/testsuite/gcc.target/aarch64/vect.c b/gcc/testsuite/gcc.target/aarch64/vect.c index fc4874440a0..ff70cae43b4 100644 --- a/gcc/testsuite/gcc.target/aarch64/vect.c +++ b/gcc/testsuite/gcc.target/aarch64/vect.c @@ -55,6 +55,8 @@ int main (void) int smin_vector[] = {0, -1, -2, -3, -4, -5, -6, -7, -8, -9, -10, -11, -12, -13, -14, -15}; unsigned int umax_vector[] = {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15}; unsigned int umin_vector[] = {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15}; + int sabd_vector[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}; + int saba_vector[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}; int reduce_smax_value = 0; int reduce_smin_value = -15; unsigned int reduce_umax_value = 15; @@ -81,6 +83,8 @@ int main (void) TEST (smin, s); TEST (umax, u); TEST (umin, u); + TEST (sabd, s); + TEST (saba, s); TESTV (reduce_smax, s); TESTV (reduce_smin, s); TESTV (reduce_umax, u); diff --git a/gcc/testsuite/gcc.target/aarch64/vect.x b/gcc/testsuite/gcc.target/aarch64/vect.x index 88078349750..c0f79b50b80 100644 --- a/gcc/testsuite/gcc.target/aarch64/vect.x +++ b/gcc/testsuite/gcc.target/aarch64/vect.x @@ -138,3 +138,17 @@ long long reduce_add_s64 (pRINT64 a) return s; } + +void sabd (pRINT a, pRINT b, pRINT c) +{ + int i; + for (i = 0; i < 16; i++) + c[i] = abs (a[i] - b[i]); +} + +void saba (pRINT a, pRINT b, pRINT c) +{ + int i; + for (i = 0; i < 16; i++) + c[i] += abs (a[i] - b[i]); +} diff --git a/gcc/testsuite/gcc.target/arm/neon-for-64bits-1.c b/gcc/testsuite/gcc.target/arm/neon-for-64bits-1.c new file mode 100644 index 00000000000..a2a4103b9a2 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon-for-64bits-1.c @@ -0,0 +1,54 @@ +/* Check that Neon is *not* used by default to handle 64-bits scalar + operations. */ + +/* { dg-do compile } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-O2" } */ +/* { dg-add-options arm_neon } */ + +typedef long long i64; +typedef unsigned long long u64; +typedef unsigned int u32; +typedef int i32; + +/* Unary operators */ +#define UNARY_OP(name, op) \ + void unary_##name(u64 *a, u64 *b) { *a = op (*b + 0x1234567812345678ULL) ; } + +/* Binary operators */ +#define BINARY_OP(name, op) \ + void binary_##name(u64 *a, u64 *b, u64 *c) { *a = *b op *c ; } + +/* Unsigned shift */ +#define SHIFT_U(name, op, amount) \ + void ushift_##name(u64 *a, u64 *b, int c) { *a = *b op amount; } + +/* Signed shift */ +#define SHIFT_S(name, op, amount) \ + void sshift_##name(i64 *a, i64 *b, int c) { *a = *b op amount; } + +UNARY_OP(not, ~) + +BINARY_OP(add, +) +BINARY_OP(sub, -) +BINARY_OP(and, &) +BINARY_OP(or, |) +BINARY_OP(xor, ^) + +SHIFT_U(right1, >>, 1) +SHIFT_U(right2, >>, 2) +SHIFT_U(right5, >>, 5) +SHIFT_U(rightn, >>, c) + +SHIFT_S(right1, >>, 1) +SHIFT_S(right2, >>, 2) +SHIFT_S(right5, >>, 5) +SHIFT_S(rightn, >>, c) + +/* { dg-final {scan-assembler-times "vmvn" 0} } */ +/* { dg-final {scan-assembler-times "vadd" 0} } */ +/* { dg-final {scan-assembler-times "vsub" 0} } */ +/* { dg-final {scan-assembler-times "vand" 0} } */ +/* { dg-final {scan-assembler-times "vorr" 0} } */ +/* { dg-final {scan-assembler-times "veor" 0} } */ +/* { dg-final {scan-assembler-times "vshr" 0} } */ diff --git a/gcc/testsuite/gcc.target/arm/neon-for-64bits-2.c b/gcc/testsuite/gcc.target/arm/neon-for-64bits-2.c new file mode 100644 index 00000000000..035bfb77a37 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon-for-64bits-2.c @@ -0,0 +1,57 @@ +/* Check that Neon is used to handle 64-bits scalar operations. */ + +/* { dg-do compile } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-O2 -mneon-for-64bits" } */ +/* { dg-add-options arm_neon } */ + +typedef long long i64; +typedef unsigned long long u64; +typedef unsigned int u32; +typedef int i32; + +/* Unary operators */ +#define UNARY_OP(name, op) \ + void unary_##name(u64 *a, u64 *b) { *a = op (*b + 0x1234567812345678ULL) ; } + +/* Binary operators */ +#define BINARY_OP(name, op) \ + void binary_##name(u64 *a, u64 *b, u64 *c) { *a = *b op *c ; } + +/* Unsigned shift */ +#define SHIFT_U(name, op, amount) \ + void ushift_##name(u64 *a, u64 *b, int c) { *a = *b op amount; } + +/* Signed shift */ +#define SHIFT_S(name, op, amount) \ + void sshift_##name(i64 *a, i64 *b, int c) { *a = *b op amount; } + +UNARY_OP(not, ~) + +BINARY_OP(add, +) +BINARY_OP(sub, -) +BINARY_OP(and, &) +BINARY_OP(or, |) +BINARY_OP(xor, ^) + +SHIFT_U(right1, >>, 1) +SHIFT_U(right2, >>, 2) +SHIFT_U(right5, >>, 5) +SHIFT_U(rightn, >>, c) + +SHIFT_S(right1, >>, 1) +SHIFT_S(right2, >>, 2) +SHIFT_S(right5, >>, 5) +SHIFT_S(rightn, >>, c) + +/* { dg-final {scan-assembler-times "vmvn" 1} } */ +/* Two vadd: 1 in unary_not, 1 in binary_add */ +/* { dg-final {scan-assembler-times "vadd" 2} } */ +/* { dg-final {scan-assembler-times "vsub" 1} } */ +/* { dg-final {scan-assembler-times "vand" 1} } */ +/* { dg-final {scan-assembler-times "vorr" 1} } */ +/* { dg-final {scan-assembler-times "veor" 1} } */ +/* 6 vshr for right shifts by constant, and variable right shift uses + vshl with a negative amount in register. */ +/* { dg-final {scan-assembler-times "vshr" 6} } */ +/* { dg-final {scan-assembler-times "vshl" 2} } */ diff --git a/gcc/testsuite/gcc.target/arm/neon-vcond-gt.c b/gcc/testsuite/gcc.target/arm/neon-vcond-gt.c new file mode 100644 index 00000000000..86ccf95ada6 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon-vcond-gt.c @@ -0,0 +1,17 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-O1 -funsafe-math-optimizations -ftree-vectorize" } */ +/* { dg-add-options arm_neon } */ + +#define MAX(a, b) (a > b ? a : b) +void foo (int ilast,float* w, float* w2) +{ + int i; + for (i = 0; i < ilast; ++i) + { + w[i] = MAX (0.0f, w2[i]); + } +} + +/* { dg-final { scan-assembler "vcgt\\.f32\[\\t \]*q\[0-9\]+,\[\\t \]*q\[0-9\]+,\[\\t \]*q\[0-9\]+" } } */ +/* { dg-final { scan-assembler "vbit\[\\t \]*q\[0-9\]+,\[\\t \]*q\[0-9\]+,\[\\t \]*q\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon-vcond-ltgt.c b/gcc/testsuite/gcc.target/arm/neon-vcond-ltgt.c new file mode 100644 index 00000000000..acb23a947ff --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon-vcond-ltgt.c @@ -0,0 +1,18 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-O1 -funsafe-math-optimizations -ftree-vectorize" } */ +/* { dg-add-options arm_neon } */ + +#define LTGT(a, b) (__builtin_islessgreater (a, b) ? a : b) +void foo (int ilast,float* w, float* w2) +{ + int i; + for (i = 0; i < ilast; ++i) + { + w[i] = LTGT (0.0f, w2[i]); + } +} + +/* { dg-final { scan-assembler-times "vcgt\\.f32\[\\t \]*q\[0-9\]+,\[\\t \]*q\[0-9\]+,\[\\t \]*q\[0-9\]+" 2 } } */ +/* { dg-final { scan-assembler "vorr\[\\t \]*q\[0-9\]+,\[\\t \]*q\[0-9\]+,\[\\t \]*q\[0-9\]+" } } */ +/* { dg-final { scan-assembler "vbsl\[\\t \]*q\[0-9\]+,\[\\t \]*q\[0-9\]+,\[\\t \]*q\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon-vcond-unordered.c b/gcc/testsuite/gcc.target/arm/neon-vcond-unordered.c new file mode 100644 index 00000000000..c3e448d621b --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon-vcond-unordered.c @@ -0,0 +1,19 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-O1 -funsafe-math-optimizations -ftree-vectorize" } */ +/* { dg-add-options arm_neon } */ + +#define UNORD(a, b) (__builtin_isunordered (a, b) ? a : b) +void foo (int ilast,float* w, float* w2) +{ + int i; + for (i = 0; i < ilast; ++i) + { + w[i] = UNORD (0.0f, w2[i]); + } +} + +/* { dg-final { scan-assembler "vcgt\\.f32\[\\t \]*q\[0-9\]+,\[\\t \]*q\[0-9\]+,\[\\t \]*q\[0-9\]+" } } */ +/* { dg-final { scan-assembler "vcge\\.f32\[\\t \]*q\[0-9\]+,\[\\t \]*q\[0-9\]+,\[\\t \]*q\[0-9\]+" } } */ +/* { dg-final { scan-assembler "vorr\[\\t \]*q\[0-9\]+,\[\\t \]*q\[0-9\]+,\[\\t \]*q\[0-9\]+" } } */ +/* { dg-final { scan-assembler "vbsl\[\\t \]*q\[0-9\]+,\[\\t \]*q\[0-9\]+,\[\\t \]*q\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/i386/movti.c b/gcc/testsuite/gcc.target/i386/movti.c index e306c1e3f01..86a0279faa2 100644 --- a/gcc/testsuite/gcc.target/i386/movti.c +++ b/gcc/testsuite/gcc.target/i386/movti.c @@ -7,4 +7,4 @@ _Decimal128 test (void) return 1234123412341234.123412341234dl; } -/* { dg-final { scan-assembler-not "movabs" } } */ +/* { dg-final { scan-assembler-not "movabs" { target { ! x86_64-*-mingw* } } } } */ diff --git a/gcc/testsuite/gcc.target/i386/pr20020-1.c b/gcc/testsuite/gcc.target/i386/pr20020-1.c index 3f10970a943..f36a8a0953d 100644 --- a/gcc/testsuite/gcc.target/i386/pr20020-1.c +++ b/gcc/testsuite/gcc.target/i386/pr20020-1.c @@ -1,5 +1,6 @@ /* Check that 128-bit struct's are represented as TImode values. */ /* { dg-do compile { target int128 } } */ +/* { dg-skip-if "different ABI" { x86_64-*-mingw* } } */ /* { dg-options "-O2 -fdump-rtl-expand" } */ struct shared_ptr_struct diff --git a/gcc/testsuite/gcc.target/i386/pr20020-2.c b/gcc/testsuite/gcc.target/i386/pr20020-2.c index e8c5b3d06a4..fa5b6edaf81 100644 --- a/gcc/testsuite/gcc.target/i386/pr20020-2.c +++ b/gcc/testsuite/gcc.target/i386/pr20020-2.c @@ -1,5 +1,6 @@ /* Check that 128-bit struct's are represented as TImode values. */ /* { dg-do compile { target int128 } } */ +/* { dg-skip-if "different ABI" { x86_64-*-mingw* } } */ /* { dg-options "-O2 -fdump-rtl-expand" } */ struct shared_ptr_struct diff --git a/gcc/testsuite/gcc.target/i386/pr20020-3.c b/gcc/testsuite/gcc.target/i386/pr20020-3.c index b1cc9260ec8..a30fbc4b11c 100644 --- a/gcc/testsuite/gcc.target/i386/pr20020-3.c +++ b/gcc/testsuite/gcc.target/i386/pr20020-3.c @@ -1,5 +1,6 @@ /* Check that 128-bit struct's are represented as TImode values. */ /* { dg-do compile { target int128 } } */ +/* { dg-skip-if "different ABI" { x86_64-*-mingw* } } */ /* { dg-options "-O2 -fdump-rtl-expand" } */ struct shared_ptr_struct diff --git a/gcc/testsuite/gcc.target/i386/pr22152.c b/gcc/testsuite/gcc.target/i386/pr22152.c index 0b00169d026..b20a22a4c90 100644 --- a/gcc/testsuite/gcc.target/i386/pr22152.c +++ b/gcc/testsuite/gcc.target/i386/pr22152.c @@ -1,6 +1,6 @@ /* { dg-do compile } */ -/* { dg-options "-O2 -msse2" } */ -/* { dg-options "-O2 -msse2 -mno-vect8-ret-in-mem" { target i?86-*-solaris2.9 *-*-vxworks* } } */ +/* { dg-options "-O2 -msse2 -mtune=core2" } */ +/* { dg-additional-options "-mno-vect8-ret-in-mem" { target i?86-*-solaris2.9 *-*-vxworks* } } */ /* { dg-additional-options "-mabi=sysv" { target x86_64-*-mingw* } } */ #include <mmintrin.h> diff --git a/gcc/testsuite/gcc.target/i386/pr53425-1.c b/gcc/testsuite/gcc.target/i386/pr53425-1.c index 2446c0f5419..00143f32ab3 100644 --- a/gcc/testsuite/gcc.target/i386/pr53425-1.c +++ b/gcc/testsuite/gcc.target/i386/pr53425-1.c @@ -1,6 +1,7 @@ /* PR target/53425 */ /* { dg-do compile { target { ! { ia32 } } } } */ /* { dg-options "-O2 -mno-sse" } */ +/* { dg-skip-if "no SSE vector" { x86_64-*-mingw* } } */ typedef double __v2df __attribute__ ((__vector_size__ (16))); diff --git a/gcc/testsuite/gcc.target/i386/pr53425-2.c b/gcc/testsuite/gcc.target/i386/pr53425-2.c index b89a5b1fa8c..97523f35bb5 100644 --- a/gcc/testsuite/gcc.target/i386/pr53425-2.c +++ b/gcc/testsuite/gcc.target/i386/pr53425-2.c @@ -1,6 +1,7 @@ /* PR target/53425 */ /* { dg-do compile { target { ! { ia32 } } } } */ /* { dg-options "-O2 -mno-sse" } */ +/* { dg-skip-if "no SSE vector" { x86_64-*-mingw* } } */ typedef float __v2sf __attribute__ ((__vector_size__ (8))); diff --git a/gcc/testsuite/gcc.target/i386/pr53907.c b/gcc/testsuite/gcc.target/i386/pr53907.c index 8de8f0de985..27e2e02985f 100644 --- a/gcc/testsuite/gcc.target/i386/pr53907.c +++ b/gcc/testsuite/gcc.target/i386/pr53907.c @@ -3,10 +3,12 @@ #include <emmintrin.h> +__extension__ typedef __UINTPTR_TYPE__ uintptr_t; + __m128i x(char *s) { __m128i sz,z,mvec; - s-=((unsigned long) s)%16; + s-=((uintptr_t) s)%16; sz=_mm_load_si128((__m128i *)s); return sz; } diff --git a/gcc/testsuite/gcc.target/i386/pr55093.c b/gcc/testsuite/gcc.target/i386/pr55093.c index 76b4042302f..3d32a5799d7 100644 --- a/gcc/testsuite/gcc.target/i386/pr55093.c +++ b/gcc/testsuite/gcc.target/i386/pr55093.c @@ -1,5 +1,6 @@ /* { dg-do compile { target { ! { ia32 } } } } */ /* { dg-options "-O2 -mx32 -maddress-mode=long" } */ +/* { dg-skip-if "different ABI" { x86_64-*-mingw* } } */ typedef union tree_node *tree; typedef const union tree_node *const_tree; diff --git a/gcc/testsuite/gcc.target/mips/mips.exp b/gcc/testsuite/gcc.target/mips/mips.exp index ad32fb67713..15b1386bd9e 100644 --- a/gcc/testsuite/gcc.target/mips/mips.exp +++ b/gcc/testsuite/gcc.target/mips/mips.exp @@ -238,6 +238,7 @@ set mips_option_groups { fp "-mfp(32|64)" gp "-mgp(32|64)" long "-mlong(32|64)" + micromips "-mmicromips|-mno-micromips" mips16 "-mips16|-mno-mips16|-mflip-mips16" mips3d "-mips3d|-mno-mips3d" pic "-f(no-|)(pic|PIC)" @@ -816,6 +817,8 @@ proc mips-dg-finish {} { # | | # -mips16/-mflip-mips16 -mno-mips16 # | | +# -micromips -mno-micromips +# | | # -mips3d -mno-mips3d # | | # -mpaired-single -mno-paired-single @@ -904,6 +907,8 @@ proc mips-dg-options { args } { # Handle dependencies between options on the left of the # dependency diagram. + mips_option_dependency options "-mips16" "-mno-micromips" + mips_option_dependency options "-mmicromips" "-mno-mips16" mips_option_dependency options "-mips3d" "-mpaired-single" mips_option_dependency options "-mpaired-single" "-mfp64" mips_option_dependency options "-mfp64" "-mhard-float" @@ -1246,6 +1251,10 @@ proc mips-dg-options { args } { append extra_tool_flags " -DMIPS16=__attribute__((mips16))" } + if { [mips_have_test_option_p options "-mmicromips"] } { + append extra_tool_flags " -DMICROMIPS=__attribute__((micromips))" + } + # Use our version of gcc-dg-test for this test. if { ![string equal [info procs "mips-gcc-dg-test"] ""] } { rename gcc-dg-test mips-old-gcc-dg-test @@ -1275,6 +1284,6 @@ proc mips-gcc-dg-test { prog do_what extra_tool_flags } { dg-init mips-dg-init gcc-dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/*.c]] \ - "-DNOMIPS16=__attribute__((nomips16))" + "-DNOMIPS16=__attribute__((nomips16)) -DNOMICROMIPS=__attribute__((nomicromips)) -DNOCOMPRESSION=__attribute__((nocompression))" mips-dg-finish dg-finish diff --git a/gcc/testsuite/gcc.target/mips/umips-constraints-1.c b/gcc/testsuite/gcc.target/mips/umips-constraints-1.c index e69de29bb2d..ddec815b0f3 100644 --- a/gcc/testsuite/gcc.target/mips/umips-constraints-1.c +++ b/gcc/testsuite/gcc.target/mips/umips-constraints-1.c @@ -0,0 +1,14 @@ +/* { dg-options "(-mmicromips)" } */ +/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */ + +MICROMIPS void +foo (int *x) +{ + asm volatile ("insn1\t%a0" :: "ZD" (&x[0])); + asm volatile ("insn2\t%a0" :: "ZD" (&x[511])); + asm volatile ("insn3\t%a0" :: "ZD" (&x[512])); +} + +/* { dg-final { scan-assembler "\tinsn1\t0\\(" } } */ +/* { dg-final { scan-assembler "\tinsn2\t2044\\(" } } */ +/* { dg-final { scan-assembler-not "\tinsn3\t2048\\(" } } */ diff --git a/gcc/testsuite/gcc.target/mips/umips-constraints-2.c b/gcc/testsuite/gcc.target/mips/umips-constraints-2.c index e69de29bb2d..0240d467026 100644 --- a/gcc/testsuite/gcc.target/mips/umips-constraints-2.c +++ b/gcc/testsuite/gcc.target/mips/umips-constraints-2.c @@ -0,0 +1,14 @@ +/* { dg-options "(-mmicromips)" } */ +/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */ + +MICROMIPS void +foo (int *x) +{ + asm volatile ("insn1\t%0" :: "ZC" (x[0])); + asm volatile ("insn2\t%0" :: "ZC" (x[511])); + asm volatile ("insn3\t%0" :: "ZC" (x[512])); +} + +/* { dg-final { scan-assembler "\tinsn1\t0\\(" } } */ +/* { dg-final { scan-assembler "\tinsn2\t2044\\(" } } */ +/* { dg-final { scan-assembler-not "\tinsn3\t2048\\(" } } */ diff --git a/gcc/testsuite/gcc.target/mips/umips-lwp-1.c b/gcc/testsuite/gcc.target/mips/umips-lwp-1.c index e69de29bb2d..0cdb1b7f2bc 100644 --- a/gcc/testsuite/gcc.target/mips/umips-lwp-1.c +++ b/gcc/testsuite/gcc.target/mips/umips-lwp-1.c @@ -0,0 +1,17 @@ +/* { dg-options "-mgp32 -fpeephole2 -mtune=m14k (-mmicromips)" } */ +/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */ + +void MICROMIPS +foo (int *r4) +{ + int r5 = r4[0]; + int r6 = r4[1]; + r4[2] = r5 * r5; + { + register int r5asm asm ("$5") = r5; + register int r6asm asm ("$6") = r6; + asm ("#foo" : "=m" (r4[3]) : "d" (r5asm), "d" (r6asm)); + } +} + +/* { dg-final { scan-assembler "\tlwp\t\\\$5,0\\(\\\$4\\)" } }*/ diff --git a/gcc/testsuite/gcc.target/mips/umips-lwp-2.c b/gcc/testsuite/gcc.target/mips/umips-lwp-2.c index e69de29bb2d..ea3f3960742 100644 --- a/gcc/testsuite/gcc.target/mips/umips-lwp-2.c +++ b/gcc/testsuite/gcc.target/mips/umips-lwp-2.c @@ -0,0 +1,17 @@ +/* { dg-options "-mgp32 -fpeephole2 -mtune=m14k (-mmicromips)" } */ +/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */ + +void MICROMIPS +foo (int *r4) +{ + int r5 = r4[0]; + int r6 = r4[1]; + r4[2] = r6 * r6; + { + register int r5asm asm ("$5") = r5; + register int r6asm asm ("$6") = r6; + asm ("#foo" : "=m" (r4[3]) : "d" (r5asm), "d" (r6asm)); + } +} + +/* { dg-final { scan-assembler "\tlwp\t\\\$5,0\\(\\\$4\\)" } }*/ diff --git a/gcc/testsuite/gcc.target/mips/umips-lwp-3.c b/gcc/testsuite/gcc.target/mips/umips-lwp-3.c index e69de29bb2d..2cb37510feb 100644 --- a/gcc/testsuite/gcc.target/mips/umips-lwp-3.c +++ b/gcc/testsuite/gcc.target/mips/umips-lwp-3.c @@ -0,0 +1,17 @@ +/* { dg-options "-mgp32 -fpeephole2 -mtune=m14k (-mmicromips)" } */ +/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */ + +void MICROMIPS +foo (int *r4) +{ + int r5 = r4[511]; + int r6 = r4[512]; + r4[2] = r5 * r5; + { + register int r5asm asm ("$5") = r5; + register int r6asm asm ("$6") = r6; + asm ("#foo" : "=m" (r4[3]) : "d" (r5asm), "d" (r6asm)); + } +} + +/* { dg-final { scan-assembler "\tlwp\t\\\$5,2044\\(\\\$4\\)" } }*/ diff --git a/gcc/testsuite/gcc.target/mips/umips-lwp-4.c b/gcc/testsuite/gcc.target/mips/umips-lwp-4.c index e69de29bb2d..b8a86b4ed90 100644 --- a/gcc/testsuite/gcc.target/mips/umips-lwp-4.c +++ b/gcc/testsuite/gcc.target/mips/umips-lwp-4.c @@ -0,0 +1,17 @@ +/* { dg-options "-mgp32 -fpeephole2 -mtune=m14k (-mmicromips)" } */ +/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */ + +void MICROMIPS +foo (int *r4) +{ + int r5 = r4[511]; + int r6 = r4[512]; + r4[2] = r6 * r6; + { + register int r5asm asm ("$5") = r5; + register int r6asm asm ("$6") = r6; + asm ("#foo" : "=m" (r4[3]) : "d" (r5asm), "d" (r6asm)); + } +} + +/* { dg-final { scan-assembler "\tlwp\t\\\$5,2044\\(\\\$4\\)" } }*/ diff --git a/gcc/testsuite/gcc.target/mips/umips-lwp-5.c b/gcc/testsuite/gcc.target/mips/umips-lwp-5.c index e69de29bb2d..2315f21e91e 100644 --- a/gcc/testsuite/gcc.target/mips/umips-lwp-5.c +++ b/gcc/testsuite/gcc.target/mips/umips-lwp-5.c @@ -0,0 +1,17 @@ +/* { dg-options "-mgp32 -fpeephole2 -mtune=m14k (-mmicromips)" } */ +/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */ + +void MICROMIPS +foo (int *r4) +{ + int r5 = r4[512]; + int r6 = r4[513]; + r4[2] = r5 * r5; + { + register int r5asm asm ("$5") = r5; + register int r6asm asm ("$6") = r6; + asm ("#foo" : "=m" (r4[3]) : "d" (r5asm), "d" (r6asm)); + } +} + +/* { dg-final { scan-assembler-not "\tlwp" } }*/ diff --git a/gcc/testsuite/gcc.target/mips/umips-lwp-6.c b/gcc/testsuite/gcc.target/mips/umips-lwp-6.c index e69de29bb2d..9534974de8f 100644 --- a/gcc/testsuite/gcc.target/mips/umips-lwp-6.c +++ b/gcc/testsuite/gcc.target/mips/umips-lwp-6.c @@ -0,0 +1,17 @@ +/* { dg-options "-mgp32 -fpeephole2 -mtune=m14k (-mmicromips)" } */ +/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */ + +void MICROMIPS +foo (int *r4) +{ + int r5 = r4[512]; + int r6 = r4[513]; + r4[2] = r6 * r6; + { + register int r5asm asm ("$5") = r5; + register int r6asm asm ("$6") = r6; + asm ("#foo" : "=m" (r4[3]) : "d" (r5asm), "d" (r6asm)); + } +} + +/* { dg-final { scan-assembler-not "\tlwp" } }*/ diff --git a/gcc/testsuite/gcc.target/mips/umips-lwp-7.c b/gcc/testsuite/gcc.target/mips/umips-lwp-7.c index e69de29bb2d..87ff6dc1154 100644 --- a/gcc/testsuite/gcc.target/mips/umips-lwp-7.c +++ b/gcc/testsuite/gcc.target/mips/umips-lwp-7.c @@ -0,0 +1,41 @@ +/* { dg-options "-mgp32 -fpeephole2 -mtune=m14k (-mmicromips)" } */ +/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */ + +void MICROMIPS +f1 (int *r4, int dummy, int *other) +{ + int r5 = r4[1]; + int newr4 = r4[0]; + other[0] = r5 * r5; + { + register int r5asm asm ("$5") = r5; + register int r4asm asm ("$4") = newr4; + asm ("#foo" : "=m" (other[1]) : "d" (r4asm), "d" (r5asm)); + } +} + +void MICROMIPS +f2 (int *r4, int dummy, int *other) +{ + int newr4 = r4[0]; + int r5 = *(int *)(newr4 + 4); + { + register int r5asm asm ("$5") = r5; + register int r4asm asm ("$4") = newr4; + asm ("#foo" : "=m" (other[0]) : "d" (r4asm), "d" (r5asm)); + } +} + +void MICROMIPS +f3 (int dummy, int *r5, int *other) +{ + int newr5 = r5[1]; + int r4 = *(int *)newr5; + { + register int r5asm asm ("$4") = r4; + register int r4asm asm ("$5") = newr5; + asm ("#foo" : "=m" (other[0]) : "d" (r4asm), "d" (r5asm)); + } +} + +/* { dg-final { scan-assembler-not "\tlwp" } }*/ diff --git a/gcc/testsuite/gcc.target/mips/umips-lwp-8.c b/gcc/testsuite/gcc.target/mips/umips-lwp-8.c index e69de29bb2d..43b98423dfd 100644 --- a/gcc/testsuite/gcc.target/mips/umips-lwp-8.c +++ b/gcc/testsuite/gcc.target/mips/umips-lwp-8.c @@ -0,0 +1,17 @@ +/* { dg-options "-mgp32 -fpeephole2 -mtune=m14k (-mmicromips)" } */ +/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */ + +void MICROMIPS +f1 (int dummy, int *r5, int *other) +{ + int r4 = r5[0]; + int newr5 = r5[1]; + other[0] = r4 * r4; + { + register int r5asm asm ("$4") = r4; + register int r4asm asm ("$5") = newr5; + asm ("#foo" : "=m" (other[1]) : "d" (r4asm), "d" (r5asm)); + } +} + +/* { dg-final { scan-assembler "\tlwp\t\\\$4,0\\(\\\$5\\)" } }*/ diff --git a/gcc/testsuite/gcc.target/mips/umips-lwp-swp-volatile.c b/gcc/testsuite/gcc.target/mips/umips-lwp-swp-volatile.c index e69de29bb2d..da2cbaff38b 100644 --- a/gcc/testsuite/gcc.target/mips/umips-lwp-swp-volatile.c +++ b/gcc/testsuite/gcc.target/mips/umips-lwp-swp-volatile.c @@ -0,0 +1,42 @@ +/* { dg-do compile } */ +/* { dg-options "-mmicromips" } */ + +/* This test ensures that we do not generate microMIPS SWP or LWP + instructions when any component of the accessed memory is volatile; + they are unsafe for such since they might cause replay of partial + accesses if interrupted by an exception. */ + +static void set_csr (volatile void *p, int v) +{ + *(volatile int *) (p) = v; +} + +static int get_csr (volatile void *p) +{ + return *(volatile int *) (p); +} + +int main () +{ + int i, q = 0, p = 0, r = 0; + + for (i = 0; i < 20; i++) + { + set_csr ((volatile void *) 0xbf0100a8, 0xffff0002); + set_csr ((volatile void *) 0xbf0100a4, 0x80000008); + } + + for (i = 0; i < 20; i++) + { + register int k, j; + k = get_csr ((volatile void *) 0xbf0100b8); + p += k; + j = get_csr ((volatile void *) 0xbf0100b4); + r += j; + q = j + k; + } + return q + r + p; +} + +/* { dg-final { scan-assembler-not "\tswp" } } */ +/* { dg-final { scan-assembler-not "\tlwp" } } */ diff --git a/gcc/testsuite/gcc.target/mips/umips-movep-1.c b/gcc/testsuite/gcc.target/mips/umips-movep-1.c index e69de29bb2d..0865b78bd8c 100644 --- a/gcc/testsuite/gcc.target/mips/umips-movep-1.c +++ b/gcc/testsuite/gcc.target/mips/umips-movep-1.c @@ -0,0 +1,16 @@ +/* Check that we can generate the MOVEP instruction. */ +/* { dg-options "-mgp32 -fpeephole2 (-mmicromips)" } */ +/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */ + +long long bar (long long, long long); + +MICROMIPS long long +foo (long long n, long long a) +{ + long long i, j; + + i = bar (n, a); + j = bar (n, a); + return i + j; +} +/* { dg-final { scan-assembler "\tmovep\t" } } */ diff --git a/gcc/testsuite/gcc.target/mips/umips-movep-2.c b/gcc/testsuite/gcc.target/mips/umips-movep-2.c index e69de29bb2d..5a3a8419eee 100644 --- a/gcc/testsuite/gcc.target/mips/umips-movep-2.c +++ b/gcc/testsuite/gcc.target/mips/umips-movep-2.c @@ -0,0 +1,13 @@ +/* Check that we can generate the MOVEP instruction. */ +/* { dg-options "-fpeephole2 -mgp32 (-mmicromips)" } */ +/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */ + +int bar (int, int); + +int MICROMIPS +foo (int n, int a) +{ + return bar (0, 0); +} + +/* { dg-final { scan-assembler "\tmovep\t\\\$4,\\\$5,\\\$0,\\\$0" } } */ diff --git a/gcc/testsuite/gcc.target/mips/umips-save-restore-1.c b/gcc/testsuite/gcc.target/mips/umips-save-restore-1.c index e69de29bb2d..ff1ea4b339a 100644 --- a/gcc/testsuite/gcc.target/mips/umips-save-restore-1.c +++ b/gcc/testsuite/gcc.target/mips/umips-save-restore-1.c @@ -0,0 +1,18 @@ +/* Check that we can use the swm/lwm instructions. */ +/* { dg-options "-mabi=32 (-mmicromips)" } */ +/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */ + +int bar (int, int, int, int, int); + +MICROMIPS int +foo (int n, int a, int b, int c, int d) +{ + int i, j; + + i = bar (n, a, b, c, d); + j = bar (n, a, b, c, d); + return i + j; +} + +/* { dg-final { scan-assembler "\tswm\t\\\$16-\\\$2(0|1),\\\$31" } } */ +/* { dg-final { scan-assembler "\tlwm\t\\\$16-\\\$2(0|1),\\\$31" } } */ diff --git a/gcc/testsuite/gcc.target/mips/umips-save-restore-2.c b/gcc/testsuite/gcc.target/mips/umips-save-restore-2.c index e69de29bb2d..cb421d5d4be 100644 --- a/gcc/testsuite/gcc.target/mips/umips-save-restore-2.c +++ b/gcc/testsuite/gcc.target/mips/umips-save-restore-2.c @@ -0,0 +1,16 @@ +/* Check that we can use the save instruction to save spilled arguments. */ +/* { dg-options "-mabi=32 (-mmicromips)" } */ +/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */ + +MICROMIPS void +foo (int *a, int b, int c) +{ + asm volatile ("" ::: "$2", "$3", "$4", "$5", "$6", "$7", "$8", + "$9", "$10", "$11", "$12", "$13", "$14", "$15", "$16", + "$17", "$18", "$19", "$20", "$21", "$22", "$23", "$24", + "$25", "$30", "memory"); + a[b] = 1; + a[c] = 1; +} +/* { dg-final { scan-assembler "\tswm\t\\\$16-\\\$23,\\\$fp" } } */ +/* { dg-final { scan-assembler "\tlwm\t\\\$16-\\\$23,\\\$fp" } } */ diff --git a/gcc/testsuite/gcc.target/mips/umips-save-restore-3.c b/gcc/testsuite/gcc.target/mips/umips-save-restore-3.c index e69de29bb2d..22c6f45f717 100644 --- a/gcc/testsuite/gcc.target/mips/umips-save-restore-3.c +++ b/gcc/testsuite/gcc.target/mips/umips-save-restore-3.c @@ -0,0 +1,14 @@ +/* Check that we can use the swm instruction to save $16, $17 and $31. */ +/* { dg-options "-mgp32 (-mmicromips)" } */ +/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */ + +void bar (void); + +MICROMIPS void +foo (void) +{ + bar (); + asm volatile ("" ::: "$16", "$17"); +} +/* { dg-final { scan-assembler "\tswm\t\\\$16-\\\$17,\\\$31" } } */ +/* { dg-final { scan-assembler "\tlwm\t\\\$16-\\\$17,\\\$31" } } */ diff --git a/gcc/testsuite/gcc.target/mips/umips-swp-1.c b/gcc/testsuite/gcc.target/mips/umips-swp-1.c index e69de29bb2d..5e337b27b6c 100644 --- a/gcc/testsuite/gcc.target/mips/umips-swp-1.c +++ b/gcc/testsuite/gcc.target/mips/umips-swp-1.c @@ -0,0 +1,10 @@ +/* { dg-options "-fpeephole2 -mgp32 (-mmicromips)" } */ +/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */ + +void MICROMIPS +foo (long long l1, long long *l2) +{ + *l2 = l1; +} + +/* { dg-final { scan-assembler "\tswp\t\\\$4,0\\(\\\$6\\)" } }*/ diff --git a/gcc/testsuite/gcc.target/mips/umips-swp-2.c b/gcc/testsuite/gcc.target/mips/umips-swp-2.c index e69de29bb2d..042322c2175 100644 --- a/gcc/testsuite/gcc.target/mips/umips-swp-2.c +++ b/gcc/testsuite/gcc.target/mips/umips-swp-2.c @@ -0,0 +1,17 @@ +/* { dg-options "-fpeephole2 -mtune=m14k (-mmicromips)" } */ +/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */ + +void MICROMIPS +foo (int *r4, int r5, int r6) +{ + r6 *= r6; + r4[0] = r5; + r4[1] = r6; + { + register int r5asm asm ("$5") = r5; + register int r6asm asm ("$6") = r6; + asm ("#foo" : "=m" (r4[2]) : "d" (r5asm), "d" (r6asm)); + } +} + +/* { dg-final { scan-assembler "\tswp\t\\\$5,0\\(\\\$4\\)" } }*/ diff --git a/gcc/testsuite/gcc.target/mips/umips-swp-3.c b/gcc/testsuite/gcc.target/mips/umips-swp-3.c index e69de29bb2d..f0e54647d9c 100644 --- a/gcc/testsuite/gcc.target/mips/umips-swp-3.c +++ b/gcc/testsuite/gcc.target/mips/umips-swp-3.c @@ -0,0 +1,17 @@ +/* { dg-options "-fpeephole2 -mtune=m14k (-mmicromips)" } */ +/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */ + +void MICROMIPS +foo (int *r4, int r5, int r6) +{ + r5 *= r5; + r4[0] = r5; + r4[1] = r6; + { + register int r5asm asm ("$5") = r5; + register int r6asm asm ("$6") = r6; + asm ("#foo" : "=m" (r4[2]) : "d" (r5asm), "d" (r6asm)); + } +} + +/* { dg-final { scan-assembler "\tswp\t\\\$5,0\\(\\\$4\\)" } }*/ diff --git a/gcc/testsuite/gcc.target/mips/umips-swp-4.c b/gcc/testsuite/gcc.target/mips/umips-swp-4.c index e69de29bb2d..5e8f5ea2a76 100644 --- a/gcc/testsuite/gcc.target/mips/umips-swp-4.c +++ b/gcc/testsuite/gcc.target/mips/umips-swp-4.c @@ -0,0 +1,17 @@ +/* { dg-options "-fpeephole2 -mtune=m14k (-mmicromips)" } */ +/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */ + +void MICROMIPS +foo (int *r4, int r5, int r6) +{ + r6 *= r6; + r4[511] = r5; + r4[512] = r6; + { + register int r5asm asm ("$5") = r5; + register int r6asm asm ("$6") = r6; + asm ("#foo" : "=m" (r4[2]) : "d" (r5asm), "d" (r6asm)); + } +} + +/* { dg-final { scan-assembler "\tswp\t\\\$5,2044\\(\\\$4\\)" } }*/ diff --git a/gcc/testsuite/gcc.target/mips/umips-swp-5.c b/gcc/testsuite/gcc.target/mips/umips-swp-5.c index e69de29bb2d..dc1938e47b5 100644 --- a/gcc/testsuite/gcc.target/mips/umips-swp-5.c +++ b/gcc/testsuite/gcc.target/mips/umips-swp-5.c @@ -0,0 +1,17 @@ +/* { dg-options "-fpeephole2 -mtune=m14k (-mmicromips)" } */ +/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */ + +void MICROMIPS +foo (int *r4, int r5, int r6) +{ + r5 *= r5; + r4[511] = r5; + r4[512] = r6; + { + register int r5asm asm ("$5") = r5; + register int r6asm asm ("$6") = r6; + asm ("#foo" : "=m" (r4[2]) : "d" (r5asm), "d" (r6asm)); + } +} + +/* { dg-final { scan-assembler "\tswp\t\\\$5,2044\\(\\\$4\\)" } }*/ diff --git a/gcc/testsuite/gcc.target/mips/umips-swp-6.c b/gcc/testsuite/gcc.target/mips/umips-swp-6.c index e69de29bb2d..b489006ce99 100644 --- a/gcc/testsuite/gcc.target/mips/umips-swp-6.c +++ b/gcc/testsuite/gcc.target/mips/umips-swp-6.c @@ -0,0 +1,17 @@ +/* { dg-options "-fpeephole2 -mtune=m14k (-mmicromips)" } */ +/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */ + +void MICROMIPS +foo (int *r4, int r5, int r6) +{ + r6 *= r6; + r4[512] = r5; + r4[513] = r6; + { + register int r5asm asm ("$5") = r5; + register int r6asm asm ("$6") = r6; + asm ("#foo" : "=m" (r4[2]) : "d" (r5asm), "d" (r6asm)); + } +} + +/* { dg-final { scan-assembler-not "\tswp" } }*/ diff --git a/gcc/testsuite/gcc.target/mips/umips-swp-7.c b/gcc/testsuite/gcc.target/mips/umips-swp-7.c index e69de29bb2d..6dde49b8a35 100644 --- a/gcc/testsuite/gcc.target/mips/umips-swp-7.c +++ b/gcc/testsuite/gcc.target/mips/umips-swp-7.c @@ -0,0 +1,17 @@ +/* { dg-options "-fpeephole2 -mtune=m14k (-mmicromips)" } */ +/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */ + +void MICROMIPS +foo (int *r4, int r5, int r6) +{ + r5 *= r5; + r4[512] = r5; + r4[513] = r6; + { + register int r5asm asm ("$5") = r5; + register int r6asm asm ("$6") = r6; + asm ("#foo" : "=m" (r4[2]) : "d" (r5asm), "d" (r6asm)); + } +} + +/* { dg-final { scan-assembler-not "\tswp" } }*/ diff --git a/gcc/testsuite/gcc.target/powerpc/mmfpgpr.c b/gcc/testsuite/gcc.target/powerpc/mmfpgpr.c new file mode 100644 index 00000000000..7f2d3d3eff9 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/mmfpgpr.c @@ -0,0 +1,22 @@ +/* { dg-do compile { target { powerpc*-*-* && lp64 } } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-O2 -mcpu=power6x -mmfpgpr" } */ +/* { dg-final { scan-assembler "mffgpr" } } */ +/* { dg-final { scan-assembler "mftgpr" } } */ + +/* Test that we generate the instructions to move between the GPR and FPR + registers under power6x. */ + +extern long return_long (void); +extern double return_double (void); + +double return_double2 (void) +{ + return (double) return_long (); +} + +long return_long2 (void) +{ + return (long) return_double (); +} diff --git a/gcc/testsuite/gcc.target/powerpc/pr56605.c b/gcc/testsuite/gcc.target/powerpc/pr56605.c new file mode 100644 index 00000000000..7e5af449d05 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/pr56605.c @@ -0,0 +1,13 @@ +/* PR rtl-optimization/56605 */ +/* { dg-do compile { target { powerpc64-*-* && lp64 } } } */ +/* { dg-options "-O3 -mvsx -mcpu=power7 -fno-unroll-loops -fdump-rtl-loop2_doloop" } */ + +void foo (short* __restrict sb, int* __restrict ia) +{ + int i; + for (i = 0; i < 4000; i++) + ia[i] = (int) sb[i]; +} + +/* { dg-final { scan-rtl-dump-times "\\\(compare:CC \\\(subreg:SI \\\(reg:DI" 1 "loop2_doloop" } } */ +/* { dg-final { cleanup-rtl-dump "loop2_doloop" } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/sd-pwr6.c b/gcc/testsuite/gcc.target/powerpc/sd-pwr6.c new file mode 100644 index 00000000000..947382b7f7b --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/sd-pwr6.c @@ -0,0 +1,19 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-O2 -mcpu=power6 -mhard-dfp" } */ +/* { dg-final { scan-assembler-not "lfiwzx" } } */ +/* { dg-final { scan-assembler-times "lfd" 2 } } */ +/* { dg-final { scan-assembler-times "dctdp" 2 } } */ +/* { dg-final { scan-assembler-times "dadd" 1 } } */ +/* { dg-final { scan-assembler-times "drsp" 1 } } */ + +/* Test that for power6 we need to use a bounce buffer on the stack to load + SDmode variables because the power6 does not have a way to directly load + 32-bit values from memory. */ +_Decimal32 a; + +void inc_dec32 (void) +{ + a += (_Decimal32) 1.0; +} diff --git a/gcc/testsuite/gcc.target/powerpc/sd-vsx.c b/gcc/testsuite/gcc.target/powerpc/sd-vsx.c new file mode 100644 index 00000000000..7e41e1e84cc --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/sd-vsx.c @@ -0,0 +1,20 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-O2 -mcpu=power7 -mhard-dfp" } */ +/* { dg-final { scan-assembler-times "lfiwzx" 2 } } */ +/* { dg-final { scan-assembler-times "stfiwx" 1 } } */ +/* { dg-final { scan-assembler-not "lfd" } } */ +/* { dg-final { scan-assembler-not "stfd" } } */ +/* { dg-final { scan-assembler-times "dctdp" 2 } } */ +/* { dg-final { scan-assembler-times "dadd" 1 } } */ +/* { dg-final { scan-assembler-times "drsp" 1 } } */ + +/* Test that power7 can directly load/store SDmode variables without using a + bounce buffer. */ +_Decimal32 a; + +void inc_dec32 (void) +{ + a += (_Decimal32) 1.0; +} diff --git a/gcc/testsuite/gcc.target/powerpc/vsx-float0.c b/gcc/testsuite/gcc.target/powerpc/vsx-float0.c new file mode 100644 index 00000000000..7e4fea68957 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/vsx-float0.c @@ -0,0 +1,16 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-O2 -mcpu=power7" } */ +/* { dg-final { scan-assembler "xxlxor" } } */ + +/* Test that we generate xxlor to clear a SFmode register. */ + +float sum (float *p, unsigned long n) +{ + float sum = 0.0f; /* generate xxlxor instead of load */ + while (n-- > 0) + sum += *p++; + + return sum; +} diff --git a/gcc/testsuite/gcc.target/sh/pr49880-1.c b/gcc/testsuite/gcc.target/sh/pr49880-1.c new file mode 100644 index 00000000000..e19f1bf38a1 --- /dev/null +++ b/gcc/testsuite/gcc.target/sh/pr49880-1.c @@ -0,0 +1,22 @@ +/* Check that the option -mdiv=call-div1 works. */ +/* { dg-do link { target "sh*-*-*" } } */ +/* { dg-options "-mdiv=call-div1" } */ +/* { dg-skip-if "" { "sh*-*-*" } { "-m5*"} { "" } } */ + +int +test00 (int a, int b) +{ + return a / b; +} + +unsigned int +test01 (unsigned int a, unsigned b) +{ + return a / b; +} + +int +main (int argc, char** argv) +{ + return test00 (argc, 123) + test01 (argc, 123); +} diff --git a/gcc/testsuite/gcc.target/sh/pr49880-2.c b/gcc/testsuite/gcc.target/sh/pr49880-2.c new file mode 100644 index 00000000000..eef832e30db --- /dev/null +++ b/gcc/testsuite/gcc.target/sh/pr49880-2.c @@ -0,0 +1,22 @@ +/* Check that the option -mdiv=call-fp works. */ +/* { dg-do link { target "sh*-*-*" } } */ +/* { dg-options "-mdiv=call-fp" } */ +/* { dg-skip-if "" { "sh*-*-*" } { "-m5*"} { "" } } */ + +int +test00 (int a, int b) +{ + return a / b; +} + +unsigned int +test01 (unsigned int a, unsigned b) +{ + return a / b; +} + +int +main (int argc, char** argv) +{ + return test00 (argc, 123) + test01 (argc, 123); +} diff --git a/gcc/testsuite/gcc.target/sh/pr49880-3.c b/gcc/testsuite/gcc.target/sh/pr49880-3.c new file mode 100644 index 00000000000..80a7df548a8 --- /dev/null +++ b/gcc/testsuite/gcc.target/sh/pr49880-3.c @@ -0,0 +1,22 @@ +/* Check that the option -mdiv=call-table works. */ +/* { dg-do link { target "sh*-*-*" } } */ +/* { dg-options "-mdiv=call-table" } */ +/* { dg-skip-if "" { "sh*-*-*" } { "-m5*"} { "" } } */ + +int +test00 (int a, int b) +{ + return a / b; +} + +unsigned int +test01 (unsigned int a, unsigned b) +{ + return a / b; +} + +int +main (int argc, char** argv) +{ + return test00 (argc, 123) + test01 (argc, 123); +} diff --git a/gcc/testsuite/gcc.target/sh/pr49880-4.c b/gcc/testsuite/gcc.target/sh/pr49880-4.c new file mode 100644 index 00000000000..998a8b69fdd --- /dev/null +++ b/gcc/testsuite/gcc.target/sh/pr49880-4.c @@ -0,0 +1,19 @@ +/* Check that the option -mdiv=call-fp does not produce calls to the + library function that uses FPU to implement integer division if FPU insns + are not supported or are disabled. */ +/* { dg-do compile { target "sh*-*-*" } } */ +/* { dg-options "-mdiv=call-fp" } */ +/* { dg-skip-if "" { "sh*-*-*" } { "*"} { "-m1" "-m2" "-m3" "-m4al" "*nofpu" "-m4-340*" "-m4-400*" "-m4-500*" } } */ +/* { dg-final { scan-assembler-not "sdivsi3_i4\n|udivsi3_i4\n" } } */ + +int +test00 (int a, int b) +{ + return a / b; +} + +unsigned int +test01 (unsigned int a, unsigned b) +{ + return a / b; +} diff --git a/gcc/testsuite/gcc.target/sh/pr49880-5.c b/gcc/testsuite/gcc.target/sh/pr49880-5.c new file mode 100644 index 00000000000..09e99a85f63 --- /dev/null +++ b/gcc/testsuite/gcc.target/sh/pr49880-5.c @@ -0,0 +1,19 @@ +/* Check that the option -mdiv=call-fp results in the corresponding library + function calls on targets that have a double precision FPU. */ +/* { dg-do compile { target "sh*-*-*" } } */ +/* { dg-options "-mdiv=call-fp" } */ +/* { dg-skip-if "" { "sh*-*-*" } { "*"} { "-m2a" "-m4" "-m4a" "*single-only" } } */ +/* { dg-final { scan-assembler "sdivsi3_i4\n" } } */ +/* { dg-final { scan-assembler "udivsi3_i4\n" } } */ + +int +test00 (int a, int b) +{ + return a / b; +} + +unsigned int +test01 (unsigned int a, unsigned b) +{ + return a / b; +} |