diff options
Diffstat (limited to 'gcc/testsuite/gcc.target/powerpc')
186 files changed, 4684 insertions, 2096 deletions
diff --git a/gcc/testsuite/gcc.target/powerpc/bfp/scalar-cmp-exp-eq-3.c b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-cmp-exp-eq-3.c new file mode 100644 index 00000000000..e069fb49af9 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-cmp-exp-eq-3.c @@ -0,0 +1,32 @@ +/* { dg-do run { target { powerpc*-*-* } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ +/* { dg-require-effective-target p9vector_hw } */ +/* { dg-options "-mcpu=power9" } */ + +/* This test should succeed on 32-bit and 64-bit configurations. */ +#include <altivec.h> +#include <stdlib.h> + +int +compare_exponents_eq (double *exponent1_p, double *exponent2_p) +{ + double exponent1 = *exponent1_p; + double exponent2 = *exponent2_p; + + return scalar_cmp_exp_eq (exponent1, exponent2); +} + +int +main () +{ + double x = (double) (0x1100LL << 50); + double y = (double) (0x1101LL << 50); + double z = (double) (0x1101LL << 37); + + if (!compare_exponents_eq (&x, &y)) + abort (); + if (compare_exponents_eq (&x, &z)) + abort (); + return 0; +} + diff --git a/gcc/testsuite/gcc.target/powerpc/bfp/scalar-cmp-exp-eq-4.c b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-cmp-exp-eq-4.c new file mode 100644 index 00000000000..800c32c6e07 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-cmp-exp-eq-4.c @@ -0,0 +1,34 @@ +/* { dg-do run { target { powerpc*-*-* } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ +/* { dg-require-effective-target p9vector_hw } */ +/* { dg-options "-mcpu=power9" } */ + +/* This test should succeed on 32-bit and 64-bit configurations. */ +#include <altivec.h> +#include <stdlib.h> + +char +compare_exponents_eq (double *exponent1_p, double *exponent2_p) +{ + double exponent1 = *exponent1_p; + double exponent2 = *exponent2_p; + + if (scalar_cmp_exp_eq (exponent1, exponent2)) + return 't'; + else + return 'f'; +} + +int +main () +{ + double x = (double) (0x1100LL << 50); + double y = (double) (0x1101LL << 50); + double z = (double) (0x1101LL << 37); + + if (compare_exponents_eq (&x, &y) == 'f') + abort (); + if (compare_exponents_eq (&x, &z) == 't') + abort (); + return 0; +} diff --git a/gcc/testsuite/gcc.target/powerpc/bfp/scalar-cmp-exp-gt-3.c b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-cmp-exp-gt-3.c new file mode 100644 index 00000000000..c0cedecaa7f --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-cmp-exp-gt-3.c @@ -0,0 +1,31 @@ +/* { dg-do run { target { powerpc*-*-* } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ +/* { dg-require-effective-target p9vector_hw } */ +/* { dg-options "-mcpu=power9" } */ + +/* This test should succeed on 32-bit and 64-bit configurations. */ +#include <altivec.h> +#include <stdlib.h> + +int +compare_exponents_gt (double *exponent1_p, double *exponent2_p) +{ + double exponent1 = *exponent1_p; + double exponent2 = *exponent2_p; + + return scalar_cmp_exp_gt (exponent1, exponent2); +} + +int +main () +{ + double x = (double) (0x1100LL << 50); + double y = (double) (0x1101LL << 50); + double z = (double) (0x1101LL << 37); + + if (compare_exponents_gt (&x, &y)) + abort (); + if (!compare_exponents_gt (&x, &z)) + abort (); + return 0; +} diff --git a/gcc/testsuite/gcc.target/powerpc/bfp/scalar-cmp-exp-gt-4.c b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-cmp-exp-gt-4.c new file mode 100644 index 00000000000..1e24355d7f1 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-cmp-exp-gt-4.c @@ -0,0 +1,34 @@ +/* { dg-do run { target { powerpc*-*-* } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ +/* { dg-require-effective-target p9vector_hw } */ +/* { dg-options "-mcpu=power9" } */ + +/* This test should succeed on 32-bit and 64-bit configurations. */ +#include <altivec.h> +#include <stdlib.h> + +char +compare_exponents_gt (double *exponent1_p, double *exponent2_p) +{ + double exponent1 = *exponent1_p; + double exponent2 = *exponent2_p; + + if (scalar_cmp_exp_gt (exponent1, exponent2)) + return 't'; + else + return 'f'; +} + +int +main () +{ + double x = (double) (0x1100LL << 50); + double y = (double) (0x1101LL << 50); + double z = (double) (0x1101LL << 37); + + if (compare_exponents_gt (&x, &y) == 't') + abort (); + if (compare_exponents_gt (&x, &z) == 'f') + abort (); + return 0; +} diff --git a/gcc/testsuite/gcc.target/powerpc/bfp/scalar-cmp-exp-lt-3.c b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-cmp-exp-lt-3.c new file mode 100644 index 00000000000..acc24b5658e --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-cmp-exp-lt-3.c @@ -0,0 +1,31 @@ +/* { dg-do run { target { powerpc*-*-* } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ +/* { dg-require-effective-target p9vector_hw } */ +/* { dg-options "-mcpu=power9" } */ + +/* This test should succeed on 32-bit and 64-bit configurations. */ +#include <altivec.h> +#include <stdlib.h> + +int +compare_exponents_lt (double *exponent1_p, double *exponent2_p) +{ + double exponent1 = *exponent1_p; + double exponent2 = *exponent2_p; + + return scalar_cmp_exp_lt (exponent1, exponent2); +} + +int +main () +{ + double x = (double) (0x1100LL << 50); + double y = (double) (0x1101LL << 50); + double z = (double) (0x1101LL << 37); + + if (compare_exponents_lt (&x, &y)) + abort (); + if (!compare_exponents_lt (&z, &x)) + abort (); + return 0; +} diff --git a/gcc/testsuite/gcc.target/powerpc/bfp/scalar-cmp-exp-lt-4.c b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-cmp-exp-lt-4.c new file mode 100644 index 00000000000..b8bd278dce5 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-cmp-exp-lt-4.c @@ -0,0 +1,34 @@ +/* { dg-do run { target { powerpc*-*-* } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ +/* { dg-require-effective-target p9vector_hw } */ +/* { dg-options "-mcpu=power9" } */ + +/* This test should succeed on 32-bit and 64-bit configurations. */ +#include <altivec.h> +#include <stdlib.h> + +char +compare_exponents_lt (double *exponent1_p, double *exponent2_p) +{ + double exponent1 = *exponent1_p; + double exponent2 = *exponent2_p; + + if (scalar_cmp_exp_lt (exponent1, exponent2)) + return 't'; + else + return 'f'; +} + +int +main () +{ + double x = (double) (0x1100LL << 50); + double y = (double) (0x1101LL << 50); + double z = (double) (0x1101LL << 37); + + if (compare_exponents_lt (&x, &y) == 't') + abort (); + if (compare_exponents_lt (&z, &x) == 'f') + abort (); + return 0; +} diff --git a/gcc/testsuite/gcc.target/powerpc/bfp/scalar-cmp-exp-unordered-3.c b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-cmp-exp-unordered-3.c new file mode 100644 index 00000000000..79900c21b5a --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-cmp-exp-unordered-3.c @@ -0,0 +1,36 @@ +/* { dg-do run { target { powerpc*-*-* } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ +/* { dg-require-effective-target p9vector_hw } */ +/* { dg-options "-mcpu=power9" } */ + +/* This test should succeed on 32-bit and 64-bit configurations. */ +#include <altivec.h> +#include <stdlib.h> + +int +compare_exponents_unordered (double *exponent1_p, double *exponent2_p) +{ + double exponent1 = *exponent1_p; + double exponent2 = *exponent2_p; + + /* This test succeeds if either exponent1 or exponent2 is NaN. */ + return scalar_cmp_exp_unordered (exponent1, exponent2); +} + +int +main () +{ + /* NaN is denoted by exponent = 2047 and fraction != 0 */ + unsigned long long int nan_image = 0x7ff0000000000003LL; + double *nan_ptr = (double *) &nan_image; + + double x = (double) (0x1100LL << 50); + double y = (double) (0x1101LL << 50); + double z = (double) (0x1101LL << 37); + + if (!compare_exponents_unordered (&x, nan_ptr)) + abort (); + if (compare_exponents_unordered (&x, &z)) + abort (); + return 0; +} diff --git a/gcc/testsuite/gcc.target/powerpc/bfp/scalar-cmp-exp-unordered-4.c b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-cmp-exp-unordered-4.c new file mode 100644 index 00000000000..4371946a6d7 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-cmp-exp-unordered-4.c @@ -0,0 +1,39 @@ +/* { dg-do run { target { powerpc*-*-* } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ +/* { dg-require-effective-target p9vector_hw } */ +/* { dg-options "-mcpu=power9" } */ + +/* This test should succeed on 32-bit and 64-bit configurations. */ +#include <altivec.h> +#include <stdlib.h> + +char +compare_exponents_unordered (double *exponent1_p, double *exponent2_p) +{ + double exponent1 = *exponent1_p; + double exponent2 = *exponent2_p; + + /* This test succeeds if either exponent1 or exponent2 is NaN. */ + if (scalar_cmp_exp_unordered (exponent1, exponent2)) + return 't'; + else + return 'f'; +} + +int +main () +{ + /* NaN is denoted by exponent = 2047 and fraction != 0 */ + unsigned long long int nan_image = 0x7ff0000000000003LL; + double *nan_ptr = (double *) &nan_image; + + double x = (double) (0x1100LL << 50); + double y = (double) (0x1101LL << 50); + double z = (double) (0x1101LL << 37); + + if (compare_exponents_unordered (&x, nan_ptr) == 'f') + abort (); + if (compare_exponents_unordered (&x, &z) == 't') + abort (); + return 0; +} diff --git a/gcc/testsuite/gcc.target/powerpc/bfp/scalar-extract-exp-3.c b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-extract-exp-3.c new file mode 100644 index 00000000000..9e6fb085d47 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-extract-exp-3.c @@ -0,0 +1,18 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ +/* { dg-require-effective-target lp64 } */ +/* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-options "-mcpu=power9" } */ + +/* This test should succeed only on 64-bit configurations. */ +#include <altivec.h> + +unsigned long long int +get_exponent (__ieee128 *p) +{ + __ieee128 source = *p; + + return scalar_extract_exp (source); +} + +/* { dg-final { scan-assembler "xsxexpqp" } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/bfp/scalar-extract-exp-4.c b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-extract-exp-4.c new file mode 100644 index 00000000000..502241581d9 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-extract-exp-4.c @@ -0,0 +1,18 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power8" } } */ +/* { dg-require-effective-target lp64 } */ +/* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-options "-mcpu=power8" } */ + +/* This test should succeed only on 64-bit configurations. */ +#include <altivec.h> + +unsigned long long int +get_exponent (__ieee128 *p) +{ + __ieee128 source = *p; + + return __builtin_vec_scalar_extract_exp (source); /* { dg-error "Builtin function __builtin_vsx_scalar_extract_expq requires" } */ +} + + diff --git a/gcc/testsuite/gcc.target/powerpc/bfp/scalar-extract-exp-5.c b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-extract-exp-5.c new file mode 100644 index 00000000000..07e0c1de7e3 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-extract-exp-5.c @@ -0,0 +1,21 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ +/* { dg-require-effective-target ilp32 } */ +/* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-options "-mcpu=power9" } */ + +/* This test only runs on 32-bit configurations, where a compiler error + should be issued because this builtin is not available on + 32-bit configurations. */ + +#include <altivec.h> + +unsigned long long int +get_exponent (__ieee128 *p) +{ + __ieee128 source = *p; + + return scalar_extract_exp (source); /* { dg-error "Builtin function __builtin_vec_scalar_extract_exp not supported in this compiler configuration" } */ +} + + diff --git a/gcc/testsuite/gcc.target/powerpc/bfp/scalar-extract-exp-6.c b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-extract-exp-6.c new file mode 100644 index 00000000000..a5e31bf51ab --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-extract-exp-6.c @@ -0,0 +1,30 @@ +/* { dg-do run { target { powerpc*-*-* } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ +/* { dg-require-effective-target lp64 } */ +/* { dg-require-effective-target p9vector_hw } */ +/* { dg-options "-mcpu=power9" } */ + +/* This test should succeed only on 64-bit configurations. */ +#include <altivec.h> +#include <stdlib.h> + +unsigned int +get_unbiased_exponent (double *p) +{ + double source = *p; + + return scalar_extract_exp (source) - 1023; +} + +int +main () +{ + double x = (double) (0x1100LL << 50); + double z = (double) (0x1101LL << 37); + + if (get_unbiased_exponent (&x) != 62) + abort (); + if (get_unbiased_exponent (&z) != 49) + abort (); + return 0; +} diff --git a/gcc/testsuite/gcc.target/powerpc/bfp/scalar-extract-exp-7.c b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-extract-exp-7.c new file mode 100644 index 00000000000..3920594b657 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-extract-exp-7.c @@ -0,0 +1,30 @@ +/* { dg-do run { target { powerpc*-*-* } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ +/* { dg-require-effective-target lp64 } */ +/* { dg-require-effective-target p9vector_hw } */ +/* { dg-options "-mcpu=power9" } */ + +/* This test should succeed only on 64-bit configurations. */ +#include <altivec.h> +#include <stdlib.h> + +unsigned long long int +get_unbiased_exponent (__ieee128 *p) +{ + __ieee128 source = *p; + + return scalar_extract_exp (source) - 16383; +} + +int +main () +{ + __ieee128 x = (__ieee128) (((__int128) 0x1100LL) << 114); + __ieee128 z = (__ieee128) (((__int128) 0x1101LL) << 112); + + if (get_unbiased_exponent (&x) != 126) + abort (); + if (get_unbiased_exponent (&z) != 124) + abort (); + return 0; +} diff --git a/gcc/testsuite/gcc.target/powerpc/bfp/scalar-extract-sig-3.c b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-extract-sig-3.c new file mode 100644 index 00000000000..093ba337785 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-extract-sig-3.c @@ -0,0 +1,18 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ +/* { dg-require-effective-target lp64 } */ +/* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-options "-mcpu=power9" } */ + +/* This test should succeed only on 64-bit configurations. */ +#include <altivec.h> + +unsigned __int128 +get_significand (__ieee128 *p) +{ + __ieee128 source = *p; + + return scalar_extract_sig (source); +} + +/* { dg-final { scan-assembler "xsxsigqp" } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/bfp/scalar-extract-sig-4.c b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-extract-sig-4.c new file mode 100644 index 00000000000..0c2ec4739f5 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-extract-sig-4.c @@ -0,0 +1,16 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power8" } } */ +/* { dg-require-effective-target lp64 } */ +/* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-options "-mcpu=power8" } */ + +/* This test should succeed only on 64-bit configurations. */ +#include <altivec.h> + +unsigned __int128 +get_significand (__ieee128 *p) +{ + __ieee128 source = *p; + + return __builtin_vec_scalar_extract_sig (source); /* { dg-error "Builtin function __builtin_vsx_scalar_extract_sigq requires" } */ +} diff --git a/gcc/testsuite/gcc.target/powerpc/bfp/scalar-extract-sig-5.c b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-extract-sig-5.c new file mode 100644 index 00000000000..19ca4c4a09a --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-extract-sig-5.c @@ -0,0 +1,17 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ +/* { dg-require-effective-target ilp32 } */ +/* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-options "-mcpu=power9" } */ + +/* This test only runs on 32-bit configurations, producing a compiler + error because the builtin requires 64 bits. */ +#include <altivec.h> + +unsigned __int128 /* { dg-error "'__int128' is not supported on this target" } */ +get_significand (__ieee128 *p) +{ + __ieee128 source = *p; + + return __builtin_vec_scalar_extract_sig (source); /* { dg-error "Builtin function __builtin_vec_scalar_extract_sig not supported in this compiler configuration" } */ +} diff --git a/gcc/testsuite/gcc.target/powerpc/bfp/scalar-extract-sig-6.c b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-extract-sig-6.c new file mode 100644 index 00000000000..298268dadf4 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-extract-sig-6.c @@ -0,0 +1,30 @@ +/* { dg-do run { target { powerpc*-*-* } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ +/* { dg-require-effective-target lp64 } */ +/* { dg-require-effective-target p9vector_hw } */ +/* { dg-options "-mcpu=power9" } */ + +/* This test should succeed only on 64-bit configurations. */ +#include <altivec.h> +#include <stdlib.h> + +unsigned long long int +get_significand (double *p) +{ + double source = *p; + + return scalar_extract_sig (source); +} + +int +main () +{ + double x = (double) (0x1100LL << 50); + double z = (double) (0x1101LL << 37); + + if (get_significand (&x) != 0x11000000000000ULL) + abort (); + if (get_significand (&z) != 0x11010000000000ULL) + abort (); + return 0; +} diff --git a/gcc/testsuite/gcc.target/powerpc/bfp/scalar-extract-sig-7.c b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-extract-sig-7.c new file mode 100644 index 00000000000..52081310ac5 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-extract-sig-7.c @@ -0,0 +1,36 @@ +/* { dg-do run { target { powerpc*-*-* } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ +/* { dg-require-effective-target lp64 } */ +/* { dg-require-effective-target p9vector_hw } */ +/* { dg-options "-mcpu=power9" } */ + +/* This test should succeed only on 64-bit configurations. */ +#include <altivec.h> +#include <stdlib.h> + +unsigned __int128 +get_significand (__ieee128 *p) +{ + __ieee128 source = *p; + + return scalar_extract_sig (source); +} + +int +main () +{ + __ieee128 x = (__ieee128) (((__int128) 0x1100LL) << 114); + __ieee128 z = (__ieee128) (((__int128) 0x1101LL) << 112); + + /* 113 bits in the significand */ + /* our constant mantissas have 13 bits */ + + unsigned __int128 first_anticipated_result = ((__int128) 0x1100LL) << 100; + unsigned __int128 second_anticipated_result = ((__int128) 0x1101LL) << 100; + + if (get_significand (&x) != first_anticipated_result) + abort (); + if (get_significand (&z) != second_anticipated_result) + abort (); + return 0; +} diff --git a/gcc/testsuite/gcc.target/powerpc/bfp/scalar-insert-exp-10.c b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-insert-exp-10.c new file mode 100644 index 00000000000..e730556c5c9 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-insert-exp-10.c @@ -0,0 +1,18 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power8" } } */ +/* { dg-require-effective-target lp64 } */ +/* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-options "-mcpu=power8" } */ + +/* This test should succeed only on 64-bit configurations. */ +#include <altivec.h> + +__ieee128 +insert_exponent (__ieee128 *significand_p, + unsigned long long int *exponent_p) +{ + __ieee128 significand = *significand_p; + unsigned long long int exponent = *exponent_p; + + return __builtin_vec_scalar_insert_exp (significand, exponent); /* { dg-error "Builtin function __builtin_vsx_scalar_insert_exp_qp requires" } */ +} diff --git a/gcc/testsuite/gcc.target/powerpc/bfp/scalar-insert-exp-11.c b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-insert-exp-11.c new file mode 100644 index 00000000000..d44e6ccec5b --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-insert-exp-11.c @@ -0,0 +1,21 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ +/* { dg-require-effective-target ilp32 } */ +/* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-options "-mcpu=power9" } */ + +/* This test only runs on 32-bit configurations, where a compiler error + should be issued because this builtin is not available on + 32-bit configurations. */ + +#include <altivec.h> + +__ieee128 +insert_exponent (__ieee128 *significand_p, + unsigned long long int *exponent_p) +{ + __ieee128 significand = *significand_p; + unsigned long long int exponent = *exponent_p; + + return scalar_insert_exp (significand, exponent); /* { dg-error "Builtin function __builtin_vec_scalar_insert_exp not supported in this compiler configuration" } */ +} diff --git a/gcc/testsuite/gcc.target/powerpc/bfp/scalar-insert-exp-12.c b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-insert-exp-12.c new file mode 100644 index 00000000000..b76c9c81145 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-insert-exp-12.c @@ -0,0 +1,40 @@ +/* { dg-do run { target { powerpc*-*-* } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ +/* { dg-require-effective-target lp64 } */ +/* { dg-require-effective-target p9vector_hw } */ +/* { dg-options "-mcpu=power9" } */ + +/* This test should succeed only on 64-bit configurations. */ +#include <altivec.h> +#include <stdlib.h> + +double +insert_exponent (unsigned long long int *significand_p, + unsigned long long int *exponent_p) +{ + unsigned long long int significand = *significand_p; + unsigned long long int exponent = *exponent_p; + + return scalar_insert_exp (significand, exponent); +} + +#define BIAS_FOR_DOUBLE_EXP 1023 + +int +main () +{ + unsigned long long int significand_1 = 0x18000000000000LL; + unsigned long long int significand_2 = 0x1a000000000000LL; + unsigned long long int exponent_1 = 62 + BIAS_FOR_DOUBLE_EXP; + unsigned long long int exponent_2 = 49 + BIAS_FOR_DOUBLE_EXP; + + double x = (double) (0x1800ULL << 50); + double z = (double) (0x1a00ULL << 37); + + + if (insert_exponent (&significand_1, &exponent_1) != x) + abort (); + if (insert_exponent (&significand_2, &exponent_2) != z) + abort (); + return 0; +} diff --git a/gcc/testsuite/gcc.target/powerpc/bfp/scalar-insert-exp-13.c b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-insert-exp-13.c new file mode 100644 index 00000000000..212563c84b1 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-insert-exp-13.c @@ -0,0 +1,43 @@ +/* { dg-do run { target { powerpc*-*-* } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ +/* { dg-require-effective-target lp64 } */ +/* { dg-require-effective-target p9vector_hw } */ +/* { dg-options "-mcpu=power9" } */ + +/* This test should succeed only on 64-bit configurations. */ +#include <altivec.h> +#include <stdlib.h> + +double +insert_exponent (double *significand_p, + unsigned long long int *exponent_p) +{ + double significand = *significand_p; + unsigned long long int exponent = *exponent_p; + + return scalar_insert_exp (significand, exponent); +} + +#define BIAS_FOR_DOUBLE_EXP 1023 + +int +main () +{ + unsigned long long int significand_1 = 0x11000000000000LL; + unsigned long long int significand_2 = 0x11010000000000LL; + unsigned long long int exponent_1 = 62 + BIAS_FOR_DOUBLE_EXP; + unsigned long long int exponent_2 = 49 + BIAS_FOR_DOUBLE_EXP; + + double *significand_1_ptr = (double *) &significand_1; + double *significand_2_ptr = (double *) &significand_2; + + + double x = (double) (0x1100LL << 50); + double z = (double) (0x1101LL << 37); + + if (insert_exponent (significand_1_ptr, &exponent_1) != x) + abort (); + if (insert_exponent (significand_2_ptr, &exponent_2) != z) + abort (); + return 0; +} diff --git a/gcc/testsuite/gcc.target/powerpc/bfp/scalar-insert-exp-14.c b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-insert-exp-14.c new file mode 100644 index 00000000000..fc6c3817b98 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-insert-exp-14.c @@ -0,0 +1,40 @@ +/* { dg-do run { target { powerpc*-*-* } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ +/* { dg-require-effective-target lp64 } */ +/* { dg-require-effective-target p9vector_hw } */ +/* { dg-options "-mcpu=power9" } */ + +/* This test should succeed only on 64-bit configurations. */ +#include <altivec.h> +#include <stdlib.h> + +__ieee128 +insert_exponent (unsigned __int128 *significand_p, + unsigned long long int *exponent_p) +{ + unsigned __int128 significand = *significand_p; + unsigned long long int exponent = *exponent_p; + + return scalar_insert_exp (significand, exponent); +} + +#define BIAS_FOR_QUAD_EXP 16383 + +int +main () +{ + /* most-significant bit @13, shift it to position 113 */ + unsigned __int128 significand_1 = ((__int128) 0x1100) << 100; + unsigned __int128 significand_2 = ((__int128) 0x1101) << 100; + unsigned long long int exponent_1 = 126 + BIAS_FOR_QUAD_EXP; + unsigned long long int exponent_2 = 124 + BIAS_FOR_QUAD_EXP; + + __ieee128 x = (__ieee128) (((__int128) 0x1100LL) << 114); + __ieee128 z = (__ieee128) (((__int128) 0x1101LL) << 112); + + if (insert_exponent (&significand_1, &exponent_1) != x) + abort (); + if (insert_exponent (&significand_2, &exponent_2) != z) + abort (); + return 0; +} diff --git a/gcc/testsuite/gcc.target/powerpc/bfp/scalar-insert-exp-15.c b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-insert-exp-15.c new file mode 100644 index 00000000000..5843880d382 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-insert-exp-15.c @@ -0,0 +1,43 @@ +/* { dg-do run { target { powerpc*-*-* } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ +/* { dg-require-effective-target lp64 } */ +/* { dg-require-effective-target p9vector_hw } */ +/* { dg-options "-mcpu=power9" } */ + +/* This test should succeed only on 64-bit configurations. */ +#include <altivec.h> +#include <stdlib.h> + +__ieee128 +insert_exponent (__ieee128 *significand_p, + unsigned long long int *exponent_p) +{ + __ieee128 significand = *significand_p; + unsigned long long int exponent = *exponent_p; + + return scalar_insert_exp (significand, exponent); +} + +#define BIAS_FOR_QUAD_EXP 16383 + +int +main () +{ + /* most-significant bit @13, shift it to position 113 */ + unsigned __int128 significand_1 = ((unsigned __int128) 0x1100) << 100; + unsigned __int128 significand_2 = ((unsigned __int128) 0x1101) << 100; + unsigned long long int exponent_1 = 126 + BIAS_FOR_QUAD_EXP; + unsigned long long int exponent_2 = 124 + BIAS_FOR_QUAD_EXP; + + __ieee128 *significand_1_ptr = (__ieee128 *) &significand_1; + __ieee128 *significand_2_ptr = (__ieee128 *) &significand_2; + + __ieee128 x = (__ieee128) (((__int128) 0x1100LL) << 114); + __ieee128 z = (__ieee128) (((__int128) 0x1101LL) << 112); + + if (insert_exponent (significand_1_ptr, &exponent_1) != x) + abort (); + if (insert_exponent (significand_2_ptr, &exponent_2) != z) + abort (); + return 0; +} diff --git a/gcc/testsuite/gcc.target/powerpc/bfp/scalar-insert-exp-6.c b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-insert-exp-6.c new file mode 100644 index 00000000000..d896fa5d7b1 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-insert-exp-6.c @@ -0,0 +1,20 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ +/* { dg-require-effective-target lp64 } */ +/* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-options "-mcpu=power9" } */ + +/* This test should succeed only on 64-bit configurations. */ +#include <altivec.h> + +__ieee128 +insert_exponent (unsigned __int128 *significand_p, + unsigned long long int *exponent_p) +{ + unsigned __int128 significand = *significand_p; + unsigned long long int exponent = *exponent_p; + + return scalar_insert_exp (significand, exponent); +} + +/* { dg-final { scan-assembler "xsiexpqp" } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/bfp/scalar-insert-exp-7.c b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-insert-exp-7.c new file mode 100644 index 00000000000..fe565c8f416 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-insert-exp-7.c @@ -0,0 +1,18 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power8" } } */ +/* { dg-require-effective-target lp64 } */ +/* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-options "-mcpu=power8" } */ + +/* This test should succeed only on 64-bit configurations. */ +#include <altivec.h> + +__ieee128 +insert_exponent (unsigned __int128 *significand_p, + unsigned long long int *exponent_p) +{ + unsigned __int128 significand = *significand_p; + unsigned long long int exponent = *exponent_p; + + return __builtin_vec_scalar_insert_exp (significand, exponent); /* { dg-error "Builtin function __builtin_vsx_scalar_insert_exp_q requires" } */ +} diff --git a/gcc/testsuite/gcc.target/powerpc/bfp/scalar-insert-exp-8.c b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-insert-exp-8.c new file mode 100644 index 00000000000..3a3f1c4aa82 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-insert-exp-8.c @@ -0,0 +1,21 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ +/* { dg-require-effective-target ilp32 } */ +/* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-options "-mcpu=power9" } */ + +/* This test only runs on 32-bit configurations, where a compiler error + should be issued because this builtin is not available on + 32-bit configurations. */ + +#include <altivec.h> + +__ieee128 +insert_exponent (unsigned __int128 *significand_p, /* { dg-error "'__int128' is not supported on this target" } */ + unsigned long long int *exponent_p) +{ + unsigned __int128 significand = *significand_p; /* { dg-error "'__int128' is not supported on this target" } */ + unsigned long long int exponent = *exponent_p; + + return scalar_insert_exp (significand, exponent); /* { dg-error "Builtin function __builtin_vec_scalar_insert_exp not supported in this compiler configuration" } */ +} diff --git a/gcc/testsuite/gcc.target/powerpc/bfp/scalar-insert-exp-9.c b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-insert-exp-9.c new file mode 100644 index 00000000000..dca5c0ab5b7 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-insert-exp-9.c @@ -0,0 +1,20 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ +/* { dg-require-effective-target lp64 } */ +/* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-options "-mcpu=power9" } */ + +/* This test should succeed only on 64-bit configurations. */ +#include <altivec.h> + +__ieee128 +insert_exponent (__ieee128 *significand_p, + unsigned long long int *exponent_p) +{ + __ieee128 significand = *significand_p; + unsigned long long int exponent = *exponent_p; + + return scalar_insert_exp (significand, exponent); +} + +/* { dg-final { scan-assembler "xsiexpqp" } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/bfp/scalar-test-data-class-10.c b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-test-data-class-10.c new file mode 100644 index 00000000000..32fd8b1deee --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-test-data-class-10.c @@ -0,0 +1,16 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ +/* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-options "-mcpu=power9" } */ + +#include <altivec.h> +#include <stdbool.h> + +bool +test_data_class (__ieee128 *p, const int condition_flag) +{ + __ieee128 source = *p; + + return scalar_test_data_class (source, condition_flag); /* { dg-error "argument 2 must be a 7-bit unsigned literal" } */ +} + diff --git a/gcc/testsuite/gcc.target/powerpc/bfp/scalar-test-data-class-11.c b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-test-data-class-11.c new file mode 100644 index 00000000000..0065b77746a --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-test-data-class-11.c @@ -0,0 +1,15 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power8" } } */ +/* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-options "-mcpu=power8" } */ + +#include <altivec.h> +#include <stdbool.h> + +bool +test_data_class (__ieee128 *p) +{ + __ieee128 source = *p; + + return __builtin_vec_scalar_test_data_class (source, 3); /* { dg-error "Builtin function __builtin_vsx_scalar_test_data_class_qp requires" } */ +} diff --git a/gcc/testsuite/gcc.target/powerpc/bfp/scalar-test-data-class-12.c b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-test-data-class-12.c new file mode 100644 index 00000000000..46c4fd22735 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-test-data-class-12.c @@ -0,0 +1,44 @@ +/* { dg-do run { target { powerpc*-*-* } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ +/* { dg-require-effective-target p9vector_hw } */ +/* { dg-options "-mcpu=power9" } */ + +#include <altivec.h> +#include <stdbool.h> +#include <stdlib.h> + +bool +test_denormal (double *p) +{ + double source = *p; + + /* + 0x40 Test for NaN + 0x20 Test for +Infinity + 0x10 Test for -Infinity + 0x08 Test for +Zero + 0x04 Test for -Zero + 0x02 Test for +Denormal + 0x01 Test for -Denormal + */ + return scalar_test_data_class (source, 3); +} + +int +main () +{ + /* A Denormal number has a biased exponent value of zero and a + * non-zero fraction value. */ + double denormal_plus = scalar_insert_exp (0x0008000000000000ULL, 0x0ULL); + double denormal_minus = scalar_insert_exp (0x8008000000000000ULL, 0x0ULL); + double not_denormal = scalar_insert_exp (0x8000000000000000ULL, 1023ULL); + + if (!test_denormal (&denormal_plus)) + abort (); + if (!test_denormal (&denormal_minus)) + abort (); + if (test_denormal (¬_denormal)) + abort (); + return 0; +} + diff --git a/gcc/testsuite/gcc.target/powerpc/bfp/scalar-test-data-class-13.c b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-test-data-class-13.c new file mode 100644 index 00000000000..0beb66ae643 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-test-data-class-13.c @@ -0,0 +1,47 @@ +/* { dg-do run { target { powerpc*-*-* } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ +/* { dg-require-effective-target p9vector_hw } */ +/* { dg-options "-mcpu=power9" } */ + +#include <altivec.h> +#include <stdbool.h> +#include <stdlib.h> + +bool +test_zero (float *p) +{ + float source = *p; + + /* + 0x40 Test for NaN + 0x20 Test for +Infinity + 0x10 Test for -Infinity + 0x08 Test for +Zero + 0x04 Test for -Zero + 0x02 Test for +Denormal + 0x01 Test for -Denormal + */ + return scalar_test_data_class (source, 12); +} + +int +main () +{ + /* A Zero value has a biased exponent value of zero and a zero + * fraction value. The sign may be either positive or negative. */ + unsigned int zero_plus_image = 0x0; + unsigned int zero_minus_image = 0x80000000; + unsigned int non_zero_image = 0x60000000; + + float *zero_plus_p = (float *) &zero_plus_image; + float *zero_minus_p = (float *) &zero_minus_image; + float *not_zero_p = (float *) &non_zero_image; + + if (!test_zero (zero_plus_p)) + abort (); + if (!test_zero (zero_minus_p)) + abort (); + if (test_zero (not_zero_p)) + abort (); + return 0; +} diff --git a/gcc/testsuite/gcc.target/powerpc/bfp/scalar-test-data-class-14.c b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-test-data-class-14.c new file mode 100644 index 00000000000..90dd64637c9 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-test-data-class-14.c @@ -0,0 +1,54 @@ +/* { dg-do run { target { powerpc*-*-* } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ +/* { dg-require-effective-target p9vector_hw } */ +/* { dg-options "-mcpu=power9" } */ + +#include <altivec.h> +#include <stdbool.h> +#include <stdlib.h> + +bool +test_nan (__ieee128 *p) +{ + __ieee128 source = *p; + + /* + 0x40 Test for NaN + 0x20 Test for +Infinity + 0x10 Test for -Infinity + 0x08 Test for +Zero + 0x04 Test for -Zero + 0x02 Test for +Denormal + 0x01 Test for -Denormal + */ + return scalar_test_data_class (source, 0x40); +} + +int +main () +{ + /* NaN is represented with the maximum biased exponent value and a + * non-zero fraction value. The sign bit ignored. If the + * high-order bit of the fraction field is 0, then the NaN is a + * Signaling NaN. Otherwise, it is a Quiet NaN. */ + __int128 signal_significand = (__int128) 0xffffffff; + __int128 quiet_significand = (((__int128) 0x1) << 112) | 0xffffffff; + __int128 a_number_significand = (((__int128) 0x1) << 112); + unsigned long long int nan_exponent = 0x7fff; + unsigned long long int a_number_exponent = 16383; + + __ieee128 signaling_nan = + scalar_insert_exp (signal_significand, nan_exponent); + __ieee128 quiet_nan = + scalar_insert_exp (quiet_significand, nan_exponent); + __ieee128 a_number = + scalar_insert_exp (a_number_significand, a_number_exponent); + + if (!test_nan (&signaling_nan)) + abort (); + if (!test_nan (&quiet_nan)) + abort (); + if (test_nan (&a_number)) + abort (); + return 0; +} diff --git a/gcc/testsuite/gcc.target/powerpc/bfp/scalar-test-data-class-15.c b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-test-data-class-15.c new file mode 100644 index 00000000000..5da7a3fe1b6 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-test-data-class-15.c @@ -0,0 +1,56 @@ +/* { dg-do run { target { powerpc*-*-* } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ +/* { dg-require-effective-target p9vector_hw } */ +/* { dg-options "-mcpu=power9" } */ + +#include <altivec.h> +#include <stdbool.h> +#include <stdlib.h> + +bool +test_infinity (__ieee128 *p) +{ + __ieee128 source = *p; + + /* + 0x40 Test for NaN + 0x20 Test for +Infinity + 0x10 Test for -Infinity + 0x08 Test for +Zero + 0x04 Test for -Zero + 0x02 Test for +Denormal + 0x01 Test for -Denormal + */ + return scalar_test_data_class (source, 0x30); +} + +int +main () +{ + /* Infinity is represented by a biased exponent value of: + * 255 in single format + * 2047 in double format + * 32767 in ieee128 format + * and a zero fraction value. */ + __int128 plus_significand = (__int128) 0; + __int128 minus_significand = ((__int128) 0x1) << 127; + __int128 a_number_significand = (((__int128) 0x1) << 112); + + unsigned long long int infinite_exponent = 0x7fff; + unsigned long long int a_number_exponent = 16383; + + __ieee128 plus_infinity = + scalar_insert_exp (plus_significand, infinite_exponent); + __ieee128 minus_infinity = + scalar_insert_exp (minus_significand, infinite_exponent); + __ieee128 a_number = + scalar_insert_exp (a_number_significand, a_number_exponent); + + if (!test_infinity (&plus_infinity)) + abort (); + if (!test_infinity (&minus_infinity)) + abort (); + if (test_infinity (&a_number)) + abort (); + return 0; +} diff --git a/gcc/testsuite/gcc.target/powerpc/bfp/scalar-test-data-class-8.c b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-test-data-class-8.c new file mode 100644 index 00000000000..25192506992 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-test-data-class-8.c @@ -0,0 +1,17 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ +/* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-options "-mcpu=power9" } */ + +#include <altivec.h> +#include <stdbool.h> + +bool +test_data_class (__ieee128 *p) +{ + __ieee128 source = *p; + + return scalar_test_data_class (source, 3); +} + +/* { dg-final { scan-assembler "xststdcqp" } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/bfp/scalar-test-data-class-9.c b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-test-data-class-9.c new file mode 100644 index 00000000000..28c1e090ce5 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-test-data-class-9.c @@ -0,0 +1,16 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ +/* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-options "-mcpu=power9" } */ + +#include <altivec.h> +#include <stdbool.h> + +bool +test_data_class (__ieee128 *p) +{ + __ieee128 source = *p; + + return scalar_test_data_class (source, 256); /* { dg-error "argument 2 must be a 7-bit unsigned literal" } */ +} + diff --git a/gcc/testsuite/gcc.target/powerpc/bfp/scalar-test-neg-4.c b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-test-neg-4.c new file mode 100644 index 00000000000..13fee32cdf8 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-test-neg-4.c @@ -0,0 +1,17 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ +/* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-options "-mcpu=power9" } */ + +#include <altivec.h> +#include <stdbool.h> + +bool +test_neg (__ieee128 *p) +{ + __ieee128 source = *p; + + return scalar_test_neg (source); +} + +/* { dg-final { scan-assembler "xststdcqp" } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/bfp/scalar-test-neg-5.c b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-test-neg-5.c new file mode 100644 index 00000000000..041a4a1c820 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-test-neg-5.c @@ -0,0 +1,15 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power8" } } */ +/* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-options "-mcpu=power8" } */ + +#include <altivec.h> +#include <stdbool.h> + +bool +test_neg (__ieee128 *p) +{ + __ieee128 source = *p; + + return __builtin_vec_scalar_test_neg_qp (source); /* { dg-error "Builtin function __builtin_vsx_scalar_test_neg_qp requires" } */ +} diff --git a/gcc/testsuite/gcc.target/powerpc/bfp/scalar-test-neg-6.c b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-test-neg-6.c new file mode 100644 index 00000000000..497ac7b14aa --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-test-neg-6.c @@ -0,0 +1,30 @@ +/* { dg-do run { target { powerpc*-*-* } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ +/* { dg-require-effective-target p9vector_hw } */ +/* { dg-options "-mcpu=power9" } */ + +#include <altivec.h> +#include <stdbool.h> +#include <stdlib.h> + +bool +test_neg (double *p) +{ + double source = *p; + + return scalar_test_neg (source); +} + +int +main () +{ + double neg_number = (double) -1; + double plus_number = (double) 1; + + if (!test_neg (&neg_number)) + abort (); + if (test_neg (&plus_number)) + abort (); + return 0; +} + diff --git a/gcc/testsuite/gcc.target/powerpc/bfp/scalar-test-neg-7.c b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-test-neg-7.c new file mode 100644 index 00000000000..f7dfb5f9ed6 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-test-neg-7.c @@ -0,0 +1,29 @@ +/* { dg-do run { target { powerpc*-*-* } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ +/* { dg-require-effective-target p9vector_hw } */ +/* { dg-options "-mcpu=power9" } */ + +#include <altivec.h> +#include <stdbool.h> +#include <stdlib.h> + +bool +test_neg (float *p) +{ + float source = *p; + + return scalar_test_neg (source); +} + +int +main () +{ + float neg_number = (float) -1; + float plus_number = (float) 1; + + if (!test_neg (&neg_number)) + abort (); + if (test_neg (&plus_number)) + abort (); + return 0; +} diff --git a/gcc/testsuite/gcc.target/powerpc/bfp/scalar-test-neg-8.c b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-test-neg-8.c new file mode 100644 index 00000000000..fff837ace70 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-test-neg-8.c @@ -0,0 +1,30 @@ +/* { dg-do run { target { powerpc*-*-* } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ +/* { dg-require-effective-target p9vector_hw } */ +/* { dg-options "-mcpu=power9" } */ + +#include <altivec.h> +#include <stdbool.h> +#include <stdlib.h> + +bool +test_neg (__ieee128 *p) +{ + __ieee128 source = *p; + + return scalar_test_neg (source); +} + +int +main () +{ + __ieee128 neg_number = (__ieee128) -1; + __ieee128 plus_number = (__ieee128) 1; + + if (!test_neg (&neg_number)) + abort (); + if (test_neg (&plus_number)) + abort (); + return 0; +} + diff --git a/gcc/testsuite/gcc.target/powerpc/bfp/vec-extract-exp-4.c b/gcc/testsuite/gcc.target/powerpc/bfp/vec-extract-exp-4.c new file mode 100644 index 00000000000..ab0e05e17c8 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/bfp/vec-extract-exp-4.c @@ -0,0 +1,39 @@ +/* { dg-do run { target { powerpc*-*-* } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ +/* { dg-require-effective-target p9vector_hw } */ +/* { dg-options "-mcpu=power9" } */ + +#include <altivec.h> +#include <stdlib.h> + +__vector unsigned int +get_exponents (__vector float *p) +{ + __vector float source = *p; + + return vec_extract_exp (source); +} + +unsigned int bias_float_exp (int unbiased_exp) +{ + return (unsigned int) (unbiased_exp + 127); +} + +int +main () +{ + __vector float argument; + __vector unsigned int result; + + argument[0] = (float) (0x1 << 10); + argument[1] = (float) (0x1 << 9); + argument[2] = (float) (0x1 << 8); + argument[3] = (float) (0x1 << 7); + + result = get_exponents (&argument); + if ((result[0] != bias_float_exp (10)) || + (result[1] != bias_float_exp (9)) || + (result[2] != bias_float_exp (8)) || (result[3] != bias_float_exp (7))) + abort(); + return 0; +} diff --git a/gcc/testsuite/gcc.target/powerpc/bfp/vec-extract-exp-5.c b/gcc/testsuite/gcc.target/powerpc/bfp/vec-extract-exp-5.c new file mode 100644 index 00000000000..1dabd6cf2c5 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/bfp/vec-extract-exp-5.c @@ -0,0 +1,37 @@ +/* { dg-do run { target { powerpc*-*-* } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ +/* { dg-require-effective-target p9vector_hw } */ +/* { dg-options "-mcpu=power9" } */ + +#include <altivec.h> +#include <stdlib.h> + +__vector unsigned long long int +get_exponents (__vector double *p) +{ + __vector double source = *p; + + return vec_extract_exp (source); +} + +unsigned long long int +bias_double_exp (long long int unbiased_exp) +{ + return (unsigned long long int) (unbiased_exp + 1023); +} + +int +main () +{ + __vector double argument; + __vector unsigned long long int result; + + argument[0] = (double) (0x1 << 22); + argument[1] = (double) (0x1 << 23); + + result = get_exponents (&argument); + if ((result[0] != bias_double_exp (22)) || + (result[1] != bias_double_exp (23))) + abort(); + return 0; +} diff --git a/gcc/testsuite/gcc.target/powerpc/bfp/vec-extract-sig-4.c b/gcc/testsuite/gcc.target/powerpc/bfp/vec-extract-sig-4.c new file mode 100644 index 00000000000..6d4a9277f18 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/bfp/vec-extract-sig-4.c @@ -0,0 +1,33 @@ +/* { dg-do run { target { powerpc*-*-* } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ +/* { dg-require-effective-target p9vector_hw } */ +/* { dg-options "-mcpu=power9" } */ + +#include <altivec.h> +#include <stdlib.h> + +__vector unsigned int +get_significands (__vector float *p) +{ + __vector float source = *p; + + return vec_extract_sig (source); +} + +int +main () +{ + __vector float argument; + __vector unsigned int result; + + argument[0] = (float) (0x1234 << 10); + argument[1] = (float) (0x4321 << 9); + argument[2] = (float) (0xbabe << 8); + argument[3] = (float) (0xcafe << 7); + + result = get_significands (&argument); + if ((result[0] != 0x91a000) || (result[1] != 0x864200) || + (result[2] != 0xbabe00) || (result[3] != 0xcafe00)) + abort(); + return 0; +} diff --git a/gcc/testsuite/gcc.target/powerpc/bfp/vec-extract-sig-5.c b/gcc/testsuite/gcc.target/powerpc/bfp/vec-extract-sig-5.c new file mode 100644 index 00000000000..ff2ca48798f --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/bfp/vec-extract-sig-5.c @@ -0,0 +1,31 @@ +/* { dg-do run { target { powerpc*-*-* } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ +/* { dg-require-effective-target p9vector_hw } */ +/* { dg-options "-mcpu=power9" } */ + +#include <altivec.h> +#include <stdlib.h> + +__vector unsigned long long int +get_significands (__vector double *p) +{ + __vector double source = *p; + + return vec_extract_sig (source); +} + +int +main () +{ + __vector double argument; + __vector unsigned long long int result; + + argument[0] = (double) (0xbabeLL << 22); + argument[1] = (double) (0xcafeLL << 23); + + result = get_significands (&argument); + if ((result[0] != (0xbabeULL << 37)) || (result[1] != (0xcafeULL << 37))) + abort(); + return 0; +} + diff --git a/gcc/testsuite/gcc.target/powerpc/bfp/vec-insert-exp-10.c b/gcc/testsuite/gcc.target/powerpc/bfp/vec-insert-exp-10.c new file mode 100644 index 00000000000..020d09abe13 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/bfp/vec-insert-exp-10.c @@ -0,0 +1,44 @@ +/* { dg-do run { target { powerpc*-*-* } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ +/* { dg-require-effective-target p9vector_hw } */ +/* { dg-options "-mcpu=power9" } */ + +#include <altivec.h> +#include <stdlib.h> + +__vector float +make_floats (__vector float *significands_p, + __vector unsigned int *exponents_p) +{ + __vector float significands = *significands_p; + __vector unsigned int exponents = *exponents_p; + + return vec_insert_exp (significands, exponents); +} + +int +main () +{ + __vector unsigned int significands; + __vector float *significands_p = (__vector float *) &significands; + __vector unsigned int exponents; + __vector float result; + + /* 24 bits in significand, plus the sign bit: 0x80ffffff */ + significands[0] = 0x00800000; /* 1.0 */ + significands[1] = 0x00c00000; /* 1.5 */ + significands[2] = 0x80e00000; /* -1.75 */ + significands[3] = 0x80c00000; /* -1.5 */ + + exponents[0] = 127; /* exp = 0: 1.0 */ + exponents[1] = 128; /* exp = 1: 3.0 */ + exponents[2] = 129; /* exp = 2: -7.0 */ + exponents[3] = 125; /* exp = -2: -0.375 */ + + result = make_floats (significands_p, &exponents); + if ((result[0] != 1.0f) || + (result[1] != 3.0f) || (result[2] != -7.0f) || (result[3] != -0.375f)) + abort(); + return 0; +} + diff --git a/gcc/testsuite/gcc.target/powerpc/bfp/vec-insert-exp-11.c b/gcc/testsuite/gcc.target/powerpc/bfp/vec-insert-exp-11.c new file mode 100644 index 00000000000..5bf2c9cfdaa --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/bfp/vec-insert-exp-11.c @@ -0,0 +1,39 @@ +/* { dg-do run { target { powerpc*-*-* } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ +/* { dg-require-effective-target p9vector_hw } */ +/* { dg-options "-mcpu=power9" } */ + +#include <altivec.h> +#include <stdlib.h> + +__vector double +make_doubles (__vector double *significands_p, + __vector unsigned long long int *exponents_p) +{ + __vector double significands = *significands_p; + __vector unsigned long long int exponents = *exponents_p; + + return vec_insert_exp (significands, exponents); +} + +int +main () +{ + __vector unsigned long long int significands; + __vector double *significands_p = (__vector double *) &significands; + __vector unsigned long long int exponents; + __vector double result; + + /* 53 bits in significand, plus the sign bit: 0x8000_0000_0000_0000 */ + significands[0] = 0x0010000000000000; /* 1.0 */ + significands[1] = 0x801c000000000000; /* -1.75 */ + + exponents[0] = 1023; /* exp = 0: 1.0 */ + exponents[1] = 1021; /* exp = -2: -0.4375 (7/16) */ + + result = make_doubles (significands_p, &exponents); + if ((result[0] != 1.0) || (result[1] != -0.4375)) + abort(); + return 0; +} + diff --git a/gcc/testsuite/gcc.target/powerpc/bfp/vec-insert-exp-8.c b/gcc/testsuite/gcc.target/powerpc/bfp/vec-insert-exp-8.c new file mode 100644 index 00000000000..3f9bd988aad --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/bfp/vec-insert-exp-8.c @@ -0,0 +1,43 @@ +/* { dg-do run { target { powerpc*-*-* } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ +/* { dg-require-effective-target p9vector_hw } */ +/* { dg-options "-mcpu=power9" } */ + +#include <altivec.h> +#include <stdlib.h> + +__vector float +make_floats (__vector unsigned int *significands_p, + __vector unsigned int *exponents_p) +{ + __vector unsigned int significands = *significands_p; + __vector unsigned int exponents = *exponents_p; + + return vec_insert_exp (significands, exponents); +} + +int +main () +{ + __vector unsigned int significands; + __vector unsigned int exponents; + __vector float result; + + /* 24 bits in significand, plus the sign bit: 0x80ffffff */ + significands[0] = 0x00800000; /* 1.0 */ + significands[1] = 0x00c00000; /* 1.5 */ + significands[2] = 0x80e00000; /* -1.75 */ + significands[3] = 0x80c00000; /* -1.5 */ + + exponents[0] = 127; /* exp = 0: 1.0 */ + exponents[1] = 128; /* exp = 1: 3.0.0 */ + exponents[2] = 129; /* exp = 2: -7.0 */ + exponents[3] = 125; /* exp = -2: -0.375 */ + + result = make_floats (&significands, &exponents); + if ((result[0] != 1.0f) || + (result[1] != 3.0f) || (result[2] != -7.0f) || (result[3] != -0.375f)) + abort(); + return 0; +} + diff --git a/gcc/testsuite/gcc.target/powerpc/bfp/vec-insert-exp-9.c b/gcc/testsuite/gcc.target/powerpc/bfp/vec-insert-exp-9.c new file mode 100644 index 00000000000..5dc71951aee --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/bfp/vec-insert-exp-9.c @@ -0,0 +1,38 @@ +/* { dg-do run { target { powerpc*-*-* } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ +/* { dg-require-effective-target p9vector_hw } */ +/* { dg-options "-mcpu=power9" } */ + +#include <altivec.h> +#include <stdlib.h> + +__vector double +make_doubles (__vector unsigned long long int *significands_p, + __vector unsigned long long int *exponents_p) +{ + __vector unsigned long long int significands = *significands_p; + __vector unsigned long long int exponents = *exponents_p; + + return vec_insert_exp (significands, exponents); +} + +int +main () +{ + __vector unsigned long long int significands; + __vector unsigned long long int exponents; + __vector double result; + + /* 53 bits in significand, plus the sign bit: 0x8000_0000_0000_0000 */ + significands[0] = 0x0010000000000000; /* 1.0 */ + significands[1] = 0x801c000000000000; /* -1.75 */ + + exponents[0] = 1023; /* exp = 0: 1.0 */ + exponents[1] = 1021; /* exp = -2: -0.4375 (7/16) */ + + result = make_doubles (&significands, &exponents); + if ((result[0] != 1.0) || (result[1] != -0.4375)) + abort(); + return 0; +} + diff --git a/gcc/testsuite/gcc.target/powerpc/bfp/vec-test-data-class-8.c b/gcc/testsuite/gcc.target/powerpc/bfp/vec-test-data-class-8.c new file mode 100644 index 00000000000..636a3012612 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/bfp/vec-test-data-class-8.c @@ -0,0 +1,112 @@ +/* { dg-do run { target { powerpc*-*-* } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ +/* { dg-require-effective-target p9vector_hw } */ +/* { dg-options "-mcpu=power9" } */ + +#include <altivec.h> +#include <stdlib.h> + +/* Flags to select tests: + 0x40 Test for NaN + 0x20 Test for +Infinity + 0x10 Test for -Infinity + 0x08 Test for +Zero + 0x04 Test for -Zero + 0x02 Test for +Denormal + 0x01 Test for -Denormal */ + +__vector bool int +test_nan (__vector float *p) +{ + __vector float source = *p; + + return vec_test_data_class (source, 0x40); +} + +__vector bool int +test_infinity (__vector float *p) +{ + __vector float source = *p; + + return vec_test_data_class (source, 0x30); +} + +__vector bool int +test_zero (__vector float *p) +{ + __vector float source = *p; + + return vec_test_data_class (source, 0x0c); +} + +__vector bool int +test_denormal (__vector float *p) +{ + __vector float source = *p; + + return vec_test_data_class (source, 0x03); +} + +float +float_scalar_insert_exp (unsigned int significand, unsigned int exponent) +{ + float result; + unsigned int *result_as_uip = (unsigned int *) &result; + + *result_as_uip = (significand & ~0x800000) | ((exponent & 0xff) << 23); + return result; +} + +int +main () +{ + __vector float argument; + __vector bool result; + + unsigned int signaling_significand = 0x00a00000; + unsigned int quiet_significand = 0x00c00000; + unsigned int one_significand = 0x00800000; + unsigned int three_significand = 0x00c00000; + unsigned int five_significand = 0x00a00000; + unsigned int zero_significand = 0x00000000; + unsigned int minus_zero_significand = 0x80000000; + + /* A NaN is represented with the maximum biased exponent value and a + * non-zero fraction value. The sign bit ignored. If the + * high-order bit of the fraction field is 0, then the NaN + * is a Signaling NaN. Otherwise, it is a Quiet NaN. */ + argument[0] = float_scalar_insert_exp (signaling_significand, 255); + argument[1] = float_scalar_insert_exp (quiet_significand, 255); + argument[2] = 1.0f; + argument[3] = -0.07f; + result = test_nan (&argument); + if (!result[0] || !result[1] || result[2] || result[3]) + abort (); + + /* Infinity is represented by a biased exponent value of: + * 255 in single format + * 2047 in double format + * and a zero fraction value. The difference between +infinity and + * -infinity is the value of the sign bit. */ + argument[2] = float_scalar_insert_exp (zero_significand, 255); + argument[3] = float_scalar_insert_exp (minus_zero_significand, 255); + result = test_infinity (&argument); + if (result[0] || result[1] || !result[2] || !result[3]) + abort (); + + /* A Zero value has a biased exponent value of zero and a zero + * fraction value. The sign may be either positive or negative. */ + argument[1] = float_scalar_insert_exp (minus_zero_significand, 0); + argument[2] = float_scalar_insert_exp (zero_significand, 0); + result = test_zero (&argument); + if (result[0] || !result[1] || !result[2] || result[3]) + abort (); + + /* A Denormal number has a biased exponent value of zero and a + * non-zero fraction value. */ + argument[0] = float_scalar_insert_exp (five_significand, 0); + argument[3] = float_scalar_insert_exp (three_significand, 0); + result = test_denormal (&argument); + if (!result[0] || result[1] || result[2] || !result[3]) + abort (); +} diff --git a/gcc/testsuite/gcc.target/powerpc/bfp/vec-test-data-class-9.c b/gcc/testsuite/gcc.target/powerpc/bfp/vec-test-data-class-9.c new file mode 100644 index 00000000000..5ccac12df87 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/bfp/vec-test-data-class-9.c @@ -0,0 +1,125 @@ +/* { dg-do run { target { powerpc*-*-* } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ +/* { dg-require-effective-target p9vector_hw } */ +/* { dg-options "-mcpu=power9" } */ + +#include <altivec.h> +#include <stdlib.h> + +/* Flags to select tests: + 0x40 Test for NaN + 0x20 Test for +Infinity + 0x10 Test for -Infinity + 0x08 Test for +Zero + 0x04 Test for -Zero + 0x02 Test for +Denormal + 0x01 Test for -Denormal */ + +__vector bool long long int +test_nan (__vector double *p) +{ + __vector double source = *p; + + return vec_test_data_class (source, 0x40); +} + +__vector bool long long int +test_infinity (__vector double *p) +{ + __vector double source = *p; + + return vec_test_data_class (source, 0x30); +} + +__vector bool long long int +test_zero (__vector double *p) +{ + __vector double source = *p; + + return vec_test_data_class (source, 0x0c); +} + +__vector bool long long int +test_denormal (__vector double *p) +{ + __vector double source = *p; + + return vec_test_data_class (source, 0x03); +} + +int +main () +{ + __vector double special_argument; + __vector double nonspecial_argument; + __vector bool long long int result; + + unsigned long long int signaling_significand = + 0x0017000000000000ULL; + unsigned long long int quiet_significand = + 0x001f000000000000ULL; + unsigned long long int one_significand = + 0x0010000000000000ULL; + unsigned long long int three_significand = + 0x0018000000000000ULL; + unsigned long long int five_significand = + 0x0014000000000000ULL; + unsigned long long int zero_significand = + 0x0000000000000000ULL; + unsigned long long int minus_zero_significand = + 0x8000000000000000ULL; + + nonspecial_argument[0] = -3.825; + nonspecial_argument[1] = 3.14159; + + /* A NaN is represented with the maximum biased exponent value and a + * non-zero fraction value. The sign bit ignored. If the + * high-order bit of the fraction field is 0, then the NaN + * is a Signaling NaN. Otherwise, it is a Quiet NaN. */ + special_argument[0] = scalar_insert_exp (signaling_significand, 2047); + special_argument[1] = scalar_insert_exp (quiet_significand, 2047); + result = test_nan (&special_argument); + if (!result[0] || !result[1]) + abort (); + result = test_nan (&nonspecial_argument); + if (result[0] || result[1]) + abort (); + + /* Infinity is represented by a biased exponent value of: + * 255 in single format + * 2047 in double format + * and a zero fraction value. The difference between +infinity and + * -infinity is the value of the sign bit. */ + special_argument[0] = scalar_insert_exp (zero_significand, 2047); + special_argument[1] = scalar_insert_exp (minus_zero_significand, 2047); + result = test_infinity (&special_argument); + if (!result[0] || !result[1]) + abort (); + result = test_infinity (&nonspecial_argument); + if (result[0] || result[1]) + abort (); + + /* A Zero value has a biased exponent value of zero and a zero + * fraction value. The sign may be either positive or negative. */ + special_argument[0] = scalar_insert_exp (minus_zero_significand, 0); + special_argument[1] = scalar_insert_exp (zero_significand, 0); + result = test_zero (&special_argument); + if (!result[0] || !result[1]) + abort (); + result = test_zero (&nonspecial_argument); + if (result[0] || result[1]) + abort (); + + /* A Denormal number has a biased exponent value of zero and a + * non-zero fraction value. */ + special_argument[0] = scalar_insert_exp (five_significand, 0); + special_argument[1] = scalar_insert_exp (three_significand, 0); + result = test_denormal (&special_argument); + if (!result[0] || !result[1]) + abort (); + result = test_denormal (&nonspecial_argument); + if (result[0] || result[1]) + abort (); + return 0; +} + diff --git a/gcc/testsuite/gcc.target/powerpc/bmi-andn-1.c b/gcc/testsuite/gcc.target/powerpc/bmi-andn-1.c index 8d8d643e088..3702bdd77fe 100644 --- a/gcc/testsuite/gcc.target/powerpc/bmi-andn-1.c +++ b/gcc/testsuite/gcc.target/powerpc/bmi-andn-1.c @@ -1,6 +1,7 @@ /* { dg-do run } */ /* { dg-options "-O3" } */ /* { dg-require-effective-target lp64 } */ +/* { dg-require-effective-target ppc_cpu_supports_hw } */ #define NO_WARN_X86_INTRINSICS 1 #include <x86intrin.h> diff --git a/gcc/testsuite/gcc.target/powerpc/bmi-andn-2.c b/gcc/testsuite/gcc.target/powerpc/bmi-andn-2.c index a4260b51b79..a6f5d5084c9 100644 --- a/gcc/testsuite/gcc.target/powerpc/bmi-andn-2.c +++ b/gcc/testsuite/gcc.target/powerpc/bmi-andn-2.c @@ -1,6 +1,7 @@ /* { dg-do run } */ /* { dg-options "-O3" } */ /* { dg-require-effective-target lp64 } */ +/* { dg-require-effective-target ppc_cpu_supports_hw } */ #define NO_WARN_X86_INTRINSICS 1 #include <x86intrin.h> diff --git a/gcc/testsuite/gcc.target/powerpc/bmi-bextr-1.c b/gcc/testsuite/gcc.target/powerpc/bmi-bextr-1.c index f532c6a3bb5..45e5bdd8510 100644 --- a/gcc/testsuite/gcc.target/powerpc/bmi-bextr-1.c +++ b/gcc/testsuite/gcc.target/powerpc/bmi-bextr-1.c @@ -1,6 +1,7 @@ /* { dg-do run } */ /* { dg-options "-O2 -fno-inline" } */ /* { dg-require-effective-target lp64 } */ +/* { dg-require-effective-target ppc_cpu_supports_hw } */ #define NO_WARN_X86_INTRINSICS 1 #include <x86intrin.h> diff --git a/gcc/testsuite/gcc.target/powerpc/bmi-bextr-2.c b/gcc/testsuite/gcc.target/powerpc/bmi-bextr-2.c index b3515259fca..52f78df1267 100644 --- a/gcc/testsuite/gcc.target/powerpc/bmi-bextr-2.c +++ b/gcc/testsuite/gcc.target/powerpc/bmi-bextr-2.c @@ -1,6 +1,7 @@ /* { dg-do run } */ /* { dg-options "-O3 -fno-inline" } */ /* { dg-require-effective-target lp64 } */ +/* { dg-require-effective-target ppc_cpu_supports_hw } */ #define NO_WARN_X86_INTRINSICS 1 #include <x86intrin.h> diff --git a/gcc/testsuite/gcc.target/powerpc/bmi-bextr-4.c b/gcc/testsuite/gcc.target/powerpc/bmi-bextr-4.c index 8701d9fbd1d..3ca56665033 100644 --- a/gcc/testsuite/gcc.target/powerpc/bmi-bextr-4.c +++ b/gcc/testsuite/gcc.target/powerpc/bmi-bextr-4.c @@ -1,6 +1,7 @@ /* { dg-do run } */ /* { dg-options "-O3 -fno-inline" } */ /* { dg-require-effective-target lp64 } */ +/* { dg-require-effective-target ppc_cpu_supports_hw } */ #define NO_WARN_X86_INTRINSICS 1 #include <x86intrin.h> diff --git a/gcc/testsuite/gcc.target/powerpc/bmi-bextr-5.c b/gcc/testsuite/gcc.target/powerpc/bmi-bextr-5.c index 2835adedced..e43e2da422a 100644 --- a/gcc/testsuite/gcc.target/powerpc/bmi-bextr-5.c +++ b/gcc/testsuite/gcc.target/powerpc/bmi-bextr-5.c @@ -1,6 +1,7 @@ /* { dg-do run } */ /* { dg-options "-O3 -fno-inline" } */ /* { dg-require-effective-target lp64 } */ +/* { dg-require-effective-target ppc_cpu_supports_hw } */ #define NO_WARN_X86_INTRINSICS 1 #include <x86intrin.h> diff --git a/gcc/testsuite/gcc.target/powerpc/bmi-blsi-1.c b/gcc/testsuite/gcc.target/powerpc/bmi-blsi-1.c index 418d336b43e..345a7eb9def 100644 --- a/gcc/testsuite/gcc.target/powerpc/bmi-blsi-1.c +++ b/gcc/testsuite/gcc.target/powerpc/bmi-blsi-1.c @@ -1,6 +1,7 @@ /* { dg-do run } */ /* { dg-options "-O3 -fno-inline" } */ /* { dg-require-effective-target lp64 } */ +/* { dg-require-effective-target ppc_cpu_supports_hw } */ #define NO_WARN_X86_INTRINSICS 1 #include <x86intrin.h> diff --git a/gcc/testsuite/gcc.target/powerpc/bmi-blsi-2.c b/gcc/testsuite/gcc.target/powerpc/bmi-blsi-2.c index 1d51b5a75bb..f2e1a58f5ed 100644 --- a/gcc/testsuite/gcc.target/powerpc/bmi-blsi-2.c +++ b/gcc/testsuite/gcc.target/powerpc/bmi-blsi-2.c @@ -1,6 +1,7 @@ /* { dg-do run } */ /* { dg-options "-O3 -fno-inline" } */ /* { dg-require-effective-target lp64 } */ +/* { dg-require-effective-target ppc_cpu_supports_hw } */ #define NO_WARN_X86_INTRINSICS 1 #include <x86intrin.h> diff --git a/gcc/testsuite/gcc.target/powerpc/bmi-blsmsk-1.c b/gcc/testsuite/gcc.target/powerpc/bmi-blsmsk-1.c index df34d53ab86..481b09f77ce 100644 --- a/gcc/testsuite/gcc.target/powerpc/bmi-blsmsk-1.c +++ b/gcc/testsuite/gcc.target/powerpc/bmi-blsmsk-1.c @@ -1,6 +1,7 @@ /* { dg-do run } */ /* { dg-options "-O3 -fno-inline" } */ /* { dg-require-effective-target lp64 } */ +/* { dg-require-effective-target ppc_cpu_supports_hw } */ #define NO_WARN_X86_INTRINSICS 1 #include <x86intrin.h> diff --git a/gcc/testsuite/gcc.target/powerpc/bmi-blsmsk-2.c b/gcc/testsuite/gcc.target/powerpc/bmi-blsmsk-2.c index e5fe12d4ee0..3ba7e97dd47 100644 --- a/gcc/testsuite/gcc.target/powerpc/bmi-blsmsk-2.c +++ b/gcc/testsuite/gcc.target/powerpc/bmi-blsmsk-2.c @@ -1,6 +1,7 @@ /* { dg-do run } */ /* { dg-options "-O3 -fno-inline" } */ /* { dg-require-effective-target lp64 } */ +/* { dg-require-effective-target ppc_cpu_supports_hw } */ #define NO_WARN_X86_INTRINSICS 1 #include <x86intrin.h> diff --git a/gcc/testsuite/gcc.target/powerpc/bmi-blsr-1.c b/gcc/testsuite/gcc.target/powerpc/bmi-blsr-1.c index 645e00f05ee..c383b7914e2 100644 --- a/gcc/testsuite/gcc.target/powerpc/bmi-blsr-1.c +++ b/gcc/testsuite/gcc.target/powerpc/bmi-blsr-1.c @@ -1,6 +1,7 @@ /* { dg-do run } */ /* { dg-options "-O3 -fno-inline" } */ /* { dg-require-effective-target lp64 } */ +/* { dg-require-effective-target ppc_cpu_supports_hw } */ #define NO_WARN_X86_INTRINSICS 1 #include <x86intrin.h> diff --git a/gcc/testsuite/gcc.target/powerpc/bmi-blsr-2.c b/gcc/testsuite/gcc.target/powerpc/bmi-blsr-2.c index f290b838001..61d962b9150 100644 --- a/gcc/testsuite/gcc.target/powerpc/bmi-blsr-2.c +++ b/gcc/testsuite/gcc.target/powerpc/bmi-blsr-2.c @@ -1,6 +1,7 @@ /* { dg-do run } */ /* { dg-options "-O3 -fno-inline" } */ /* { dg-require-effective-target lp64 } */ +/* { dg-require-effective-target ppc_cpu_supports_hw } */ #define NO_WARN_X86_INTRINSICS 1 #include <x86intrin.h> diff --git a/gcc/testsuite/gcc.target/powerpc/bmi-check.h b/gcc/testsuite/gcc.target/powerpc/bmi-check.h index 35a2ac29bc3..1a9ad13f38c 100644 --- a/gcc/testsuite/gcc.target/powerpc/bmi-check.h +++ b/gcc/testsuite/gcc.target/powerpc/bmi-check.h @@ -13,6 +13,7 @@ do_test (void) int main () { +#ifdef __BUILTIN_CPU_SUPPORTS__ /* Need 64-bit for 64-bit longs as single instruction. */ if ( __builtin_cpu_supports ("ppc64") ) { @@ -25,6 +26,6 @@ main () else printf ("SKIPPED\n"); #endif - +#endif /* __BUILTIN_CPU_SUPPORTS__ */ return 0; } diff --git a/gcc/testsuite/gcc.target/powerpc/bmi-tzcnt-1.c b/gcc/testsuite/gcc.target/powerpc/bmi-tzcnt-1.c index 25b096ad0bc..25ba3dc238e 100644 --- a/gcc/testsuite/gcc.target/powerpc/bmi-tzcnt-1.c +++ b/gcc/testsuite/gcc.target/powerpc/bmi-tzcnt-1.c @@ -1,6 +1,7 @@ /* { dg-do run } */ /* { dg-options "-O3 -fno-inline" } */ /* { dg-require-effective-target lp64 } */ +/* { dg-require-effective-target ppc_cpu_supports_hw } */ #define NO_WARN_X86_INTRINSICS 1 #include <x86intrin.h> diff --git a/gcc/testsuite/gcc.target/powerpc/bmi-tzcnt-2.c b/gcc/testsuite/gcc.target/powerpc/bmi-tzcnt-2.c index 75397e53eb6..1b80ccbdaa9 100644 --- a/gcc/testsuite/gcc.target/powerpc/bmi-tzcnt-2.c +++ b/gcc/testsuite/gcc.target/powerpc/bmi-tzcnt-2.c @@ -1,6 +1,7 @@ /* { dg-do run } */ /* { dg-options "-O3 -fno-inline" } */ /* { dg-require-effective-target lp64 } */ +/* { dg-require-effective-target ppc_cpu_supports_hw } */ #define NO_WARN_X86_INTRINSICS 1 #include <x86intrin.h> diff --git a/gcc/testsuite/gcc.target/powerpc/bmi2-bzhi32-1.c b/gcc/testsuite/gcc.target/powerpc/bmi2-bzhi32-1.c index b2a6d4d74ea..f0943d7f974 100644 --- a/gcc/testsuite/gcc.target/powerpc/bmi2-bzhi32-1.c +++ b/gcc/testsuite/gcc.target/powerpc/bmi2-bzhi32-1.c @@ -1,6 +1,7 @@ /* { dg-do run } */ /* { dg-options "-O3" } */ /* { dg-require-effective-target lp64 } */ +/* { dg-require-effective-target ppc_cpu_supports_hw } */ #define NO_WARN_X86_INTRINSICS 1 #include <x86intrin.h> diff --git a/gcc/testsuite/gcc.target/powerpc/bmi2-bzhi64-1.c b/gcc/testsuite/gcc.target/powerpc/bmi2-bzhi64-1.c index a09d5d24b51..33f1748b44e 100644 --- a/gcc/testsuite/gcc.target/powerpc/bmi2-bzhi64-1.c +++ b/gcc/testsuite/gcc.target/powerpc/bmi2-bzhi64-1.c @@ -1,6 +1,7 @@ /* { dg-do run } */ /* { dg-options "-O3" } */ /* { dg-require-effective-target lp64 } */ +/* { dg-require-effective-target ppc_cpu_supports_hw } */ #define NO_WARN_X86_INTRINSICS 1 #include <x86intrin.h> diff --git a/gcc/testsuite/gcc.target/powerpc/bmi2-check.h b/gcc/testsuite/gcc.target/powerpc/bmi2-check.h index fa7d4c02a45..ab032eaa7ca 100644 --- a/gcc/testsuite/gcc.target/powerpc/bmi2-check.h +++ b/gcc/testsuite/gcc.target/powerpc/bmi2-check.h @@ -13,6 +13,7 @@ do_test (void) int main () { +#ifdef __BUILTIN_CPU_SUPPORTS__ /* The BMI2 test for pext test requires the Bit Permute doubleword (bpermd) instruction added in PowerISA 2.06 along with the VSX facility. So we can test for arch_2_06. */ @@ -27,7 +28,7 @@ main () else printf ("SKIPPED\n"); #endif - +#endif /* __BUILTIN_CPU_SUPPORTS__ */ return 0; } diff --git a/gcc/testsuite/gcc.target/powerpc/bmi2-mulx32-1.c b/gcc/testsuite/gcc.target/powerpc/bmi2-mulx32-1.c index eda74690589..870679c779f 100644 --- a/gcc/testsuite/gcc.target/powerpc/bmi2-mulx32-1.c +++ b/gcc/testsuite/gcc.target/powerpc/bmi2-mulx32-1.c @@ -1,6 +1,7 @@ /* { dg-do run } */ /* { dg-options "-O3" } */ /* { dg-require-effective-target lp64 } */ +/* { dg-require-effective-target ppc_cpu_supports_hw } */ #define NO_WARN_X86_INTRINSICS 1 #include "bmi2-check.h" diff --git a/gcc/testsuite/gcc.target/powerpc/bmi2-mulx32-2.c b/gcc/testsuite/gcc.target/powerpc/bmi2-mulx32-2.c index a6fc38cbf55..b8327741c3a 100644 --- a/gcc/testsuite/gcc.target/powerpc/bmi2-mulx32-2.c +++ b/gcc/testsuite/gcc.target/powerpc/bmi2-mulx32-2.c @@ -1,6 +1,7 @@ /* { dg-do run } */ /* { dg-options "-O3" } */ /* { dg-require-effective-target lp64 } */ +/* { dg-require-effective-target ppc_cpu_supports_hw } */ #define NO_WARN_X86_INTRINSICS 1 #include <x86intrin.h> diff --git a/gcc/testsuite/gcc.target/powerpc/bmi2-mulx64-1.c b/gcc/testsuite/gcc.target/powerpc/bmi2-mulx64-1.c index 5334de20fc5..b1e4a13c2af 100644 --- a/gcc/testsuite/gcc.target/powerpc/bmi2-mulx64-1.c +++ b/gcc/testsuite/gcc.target/powerpc/bmi2-mulx64-1.c @@ -1,6 +1,7 @@ /* { dg-do run } */ /* { dg-options "-O3" } */ /* { dg-require-effective-target lp64 } */ +/* { dg-require-effective-target ppc_cpu_supports_hw } */ #define NO_WARN_X86_INTRINSICS 1 #include "bmi2-check.h" diff --git a/gcc/testsuite/gcc.target/powerpc/bmi2-mulx64-2.c b/gcc/testsuite/gcc.target/powerpc/bmi2-mulx64-2.c index ff119262c64..d57f05503c5 100644 --- a/gcc/testsuite/gcc.target/powerpc/bmi2-mulx64-2.c +++ b/gcc/testsuite/gcc.target/powerpc/bmi2-mulx64-2.c @@ -1,6 +1,7 @@ /* { dg-do run } */ /* { dg-options "-O3" } */ /* { dg-require-effective-target lp64 } */ +/* { dg-require-effective-target ppc_cpu_supports_hw } */ #define NO_WARN_X86_INTRINSICS 1 #include <x86intrin.h> diff --git a/gcc/testsuite/gcc.target/powerpc/bmi2-pdep32-1.c b/gcc/testsuite/gcc.target/powerpc/bmi2-pdep32-1.c index 12cf92eec2c..a07567389d0 100644 --- a/gcc/testsuite/gcc.target/powerpc/bmi2-pdep32-1.c +++ b/gcc/testsuite/gcc.target/powerpc/bmi2-pdep32-1.c @@ -3,6 +3,7 @@ /* { dg-require-effective-target lp64 } */ /* { dg-require-effective-target vsx_hw } */ /* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power7" } } */ +/* { dg-require-effective-target ppc_cpu_supports_hw } */ #define NO_WARN_X86_INTRINSICS 1 #include <x86intrin.h> diff --git a/gcc/testsuite/gcc.target/powerpc/bmi2-pdep64-1.c b/gcc/testsuite/gcc.target/powerpc/bmi2-pdep64-1.c index 01e1fdaf538..1268239e61f 100644 --- a/gcc/testsuite/gcc.target/powerpc/bmi2-pdep64-1.c +++ b/gcc/testsuite/gcc.target/powerpc/bmi2-pdep64-1.c @@ -3,6 +3,7 @@ /* { dg-require-effective-target lp64 } */ /* { dg-require-effective-target vsx_hw } */ /* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power7" } } */ +/* { dg-require-effective-target ppc_cpu_supports_hw } */ #define NO_WARN_X86_INTRINSICS 1 #include <x86intrin.h> diff --git a/gcc/testsuite/gcc.target/powerpc/bmi2-pext32-1.c b/gcc/testsuite/gcc.target/powerpc/bmi2-pext32-1.c index 9450ef56aed..762ed1b0325 100644 --- a/gcc/testsuite/gcc.target/powerpc/bmi2-pext32-1.c +++ b/gcc/testsuite/gcc.target/powerpc/bmi2-pext32-1.c @@ -3,6 +3,7 @@ /* { dg-require-effective-target lp64 } */ /* { dg-require-effective-target vsx_hw } */ /* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power7" } } */ +/* { dg-require-effective-target ppc_cpu_supports_hw } */ #define NO_WARN_X86_INTRINSICS 1 #include <x86intrin.h> diff --git a/gcc/testsuite/gcc.target/powerpc/bmi2-pext64-1.c b/gcc/testsuite/gcc.target/powerpc/bmi2-pext64-1.c index b76ae81b5bc..5e269ec47de 100644 --- a/gcc/testsuite/gcc.target/powerpc/bmi2-pext64-1.c +++ b/gcc/testsuite/gcc.target/powerpc/bmi2-pext64-1.c @@ -3,6 +3,7 @@ /* { dg-require-effective-target lp64 } */ /* { dg-require-effective-target vsx_hw } */ /* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power7" } } */ +/* { dg-require-effective-target ppc_cpu_supports_hw } */ #define NO_WARN_X86_INTRINSICS 1 #include <x86intrin.h> diff --git a/gcc/testsuite/gcc.target/powerpc/builtins-1-p9-runnable.c b/gcc/testsuite/gcc.target/powerpc/builtins-1-p9-runnable.c new file mode 100644 index 00000000000..acaebb60f1c --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/builtins-1-p9-runnable.c @@ -0,0 +1,26 @@ +/* { dg-do run { target { powerpc*-*-linux* && { lp64 && p9vector_hw } } } } */ +/* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-options "-O2 -mcpu=power9" } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ + +#include <altivec.h> + +void abort (void); + +int main() { + int i; + vector float vfa, vfb; + vector unsigned short vur, vuexpt; + + vfa = (vector float){3.4, 5.0, 20.0, 50.9 }; + vfb = (vector float){10.0, 40.0, 70.0, 100.0 }; + vuexpt = (vector unsigned short){ 3, 5, 20, 50, + 10, 40, 70, 100}; + + vur = vec_pack_to_short_fp32 (vfa, vfb); + + for(i = 0; i< 8; i++) { + if (vur[i] != vuexpt[i]) + abort(); + } +} diff --git a/gcc/testsuite/gcc.target/powerpc/builtins-2-p9-runnable.c b/gcc/testsuite/gcc.target/powerpc/builtins-2-p9-runnable.c new file mode 100644 index 00000000000..2f317077fcb --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/builtins-2-p9-runnable.c @@ -0,0 +1,72 @@ +/* { dg-do run { target { powerpc64*-*-* && { lp64 && p9vector_hw } } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ +/* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-options "-mcpu=power9 -O2" } */ + +#include <altivec.h> // vector + +void abort (void); + +int main() { + int i; + vector int vsia; + vector unsigned int vsir, vsiexpt; + vector unsigned int vuia, vuir, vuiexpt; + vector signed long long vslla; + vector unsigned long long vsllr, vsllexpt; + vector unsigned long long vulla, vullr, vullexpt; + vector __int128_t vs128a; + vector __uint128_t vs128r, vs128expt; + vector __uint128_t vu128a, vu128r, vu128expt; + + /* Returns a vector with each element containing the parity of the low-order + bit of each of the bytes in that element. Note results are always + returned in an unsinged type, per the ABI spec. */ + vsia = (vector int) {0x10101010, 0x10101011, 0x10101111, 0x10111111}; + vsiexpt = (vector unsigned int){0x0, 0x1, 0x0, 0x1}; + + vuia = (vector unsigned int) {0x000010000, 0x00010001, + 0x10100000, 0x000010101}; + vuiexpt = (vector unsigned int){0x1, 0x0, 0x0, 0x1}; + + vslla = (vector long long) {0x0000000000010000, 0x0001000100010000}; + vsllexpt = (vector unsigned long long){0x1, 0x1}; + + vulla = (vector unsigned long long) {0x0000000000000001, + 0x0001000000000001}; + vullexpt = (vector unsigned long long){0x1, 0x0}; + + vs128a = (vector __int128_t) {0x0000000000001}; + vs128expt = (vector __uint128_t) {0x1}; + vu128a = (vector __uint128_t) {0x1000000000001}; + vu128expt = (vector __uint128_t) {0x0}; + + vsir = vec_parity_lsbb(vsia); + vuir = vec_parity_lsbb(vuia); + vsllr = vec_parity_lsbb(vslla); + vullr = vec_parity_lsbb(vulla); + vs128r = vec_parity_lsbb(vs128a); + vu128r = vec_parity_lsbb(vu128a); + + for(i = 0; i< 4; i++) { + if (vsir[i] != vsiexpt[i]) + abort(); + + if (vuir[i] != vuiexpt[i]) + abort(); + } + + for(i = 0; i< 2; i++) { + if (vsllr[i] != vsllexpt[i]) + abort(); + + if (vullr[i] != vullexpt[i]) + abort(); + } + + if (vs128r[0] != vs128expt[0]) + abort(); + + if (vu128r[0] != vu128expt[0]) + abort(); +} diff --git a/gcc/testsuite/gcc.target/powerpc/builtins-3-p9-runnable.c b/gcc/testsuite/gcc.target/powerpc/builtins-3-p9-runnable.c new file mode 100644 index 00000000000..24589b55639 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/builtins-3-p9-runnable.c @@ -0,0 +1,35 @@ +/* { dg-do run { target { powerpc64*-*-* && { lp64 && p9vector_hw } } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ +/* { dg-options "-mcpu=power9 -O2 -mupper-regs-di" } */ + +#include <altivec.h> // vector + +void abort (void); + +int main() { + int i; + vector float vfr, vfexpt; + vector unsigned short vusha; + + /* 1.0, -2.0, 0.0, 8.5, 1.5, 0.5, 1.25, -0.25 */ + vusha = (vector unsigned short){0B011110000000000, 0B1100000000000000, + 0B000000000000000, 0B0100100001000000, + 0B011111000000000, 0B0011100000000000, + 0B011110100000000, 0B1011010000000000}; + + vfexpt = (vector float){1.0, -2.0, 0.0, 8.5}; + vfr = vec_extract_fp_from_shorth(vusha); + + for (i=0; i<4; i++) { + if (vfr[i] != vfexpt[i]) + abort(); + } + + vfexpt = (vector float){1.5, 0.5, 1.25, -0.25}; + vfr = vec_extract_fp_from_shortl(vusha); + + for (i=0; i<4; i++) { + if (vfr[i] != vfexpt[i]) + abort(); + } +} diff --git a/gcc/testsuite/gcc.target/powerpc/builtins-3-runnable.c b/gcc/testsuite/gcc.target/powerpc/builtins-3-runnable.c index 08b7a5395d2..17bb9b3225b 100644 --- a/gcc/testsuite/gcc.target/powerpc/builtins-3-runnable.c +++ b/gcc/testsuite/gcc.target/powerpc/builtins-3-runnable.c @@ -5,53 +5,181 @@ #include <altivec.h> // vector +#ifdef DEBUG +#include <stdio.h> +#endif + #define ALL 1 #define EVEN 2 #define ODD 3 void abort (void); -void test_result_sp(int check, vector float vec_result, vector float vec_expected) +void test_int_result(int check, vector int vec_result, vector int vec_expected) { int i; - for(i = 0; i<4; i++) { - switch (check) { - case ALL: - break; - case EVEN: - if (i%2 == 0) + for (i = 0; i < 4; i++) { + switch (check) { + case ALL: break; - else - continue; - case ODD: - if (i%2 != 0) + case EVEN: + if (i%2 == 0) + break; + else + continue; + case ODD: + if (i%2 != 0) + break; + else + continue; + } + + if (vec_result[i] != vec_expected[i]) { +#ifdef DEBUG + printf("Test_int_result: "); + printf("vec_result[%d] (%d) != vec_expected[%d] (%d)\n", + i, vec_result[i], i, vec_expected[i]); +#else + abort(); +#endif + } + } +} + +void test_unsigned_int_result(int check, vector unsigned int vec_result, + vector unsigned int vec_expected) +{ + int i; + + for (i = 0; i < 4; i++) { + switch (check) { + case ALL: break; - else - continue; + case EVEN: + if (i%2 == 0) + break; + else + continue; + case ODD: + if (i%2 != 0) + break; + else + continue; + } + + if (vec_result[i] != vec_expected[i]) { +#ifdef DEBUG + printf("Test_unsigned int_result: "); + printf("vec_result[%d] (%d) != vec_expected[%d] (%d)\n", + i, vec_result[i], i, vec_expected[i]); +#else + abort(); +#endif + } + } +} - if (vec_result[i] != vec_expected[i]) - abort(); +void test_ll_int_result(vector long long int vec_result, + vector long long int vec_expected) +{ + int i; + + for (i = 0; i < 2; i++) + if (vec_result[i] != vec_expected[i]) { +#ifdef DEBUG + printf("Test_ll_int_result: "); + printf("vec_result[%d] (%lld) != vec_expected[%d] (%lld)\n", + i, vec_result[i], i, vec_expected[i]); +#else + abort(); +#endif + } +} + +void test_ll_unsigned_int_result(vector long long unsigned int vec_result, + vector long long unsigned int vec_expected) +{ + int i; + + for (i = 0; i < 2; i++) + if (vec_result[i] != vec_expected[i]) { +#ifdef DEBUG + printf("Test_ll_unsigned_int_result: "); + printf("vec_result[%d] (%lld) != vec_expected[%d] (%lld)\n", + i, vec_result[i], i, vec_expected[i]); +#else + abort(); +#endif + } +} + +void test_result_sp(int check, vector float vec_result, + vector float vec_expected) +{ + int i; + for(i = 0; i<4; i++) { + + switch (check) { + case ALL: + break; + case EVEN: + if (i%2 == 0) + break; + else + continue; + case ODD: + if (i%2 != 0) + break; + else + continue; + } + + if (vec_result[i] != vec_expected[i]) { +#ifdef DEBUG + printf("Test_result_sp: "); + printf("vec_result[%d] (%lld) != vec_expected[%d] (%lld)\n", + i, vec_result[i], i, vec_expected[i]); +#else + abort(); +#endif + } } } void test_result_dp(vector double vec_result, vector double vec_expected) { - if (vec_result[0] != vec_expected[0]) + if (vec_result[0] != vec_expected[0]) { +#ifdef DEBUG + printf("Test_result_dp: "); + printf("vec_result[0] (%lld) != vec_expected[0] (%lld)\n", + vec_result[0], vec_expected[0]); +#else abort(); +#endif + } - if (vec_result[1] != vec_expected[1]) + if (vec_result[1] != vec_expected[1]) { +#ifdef DEBUG + printf("Test_result_dp: "); + printf("vec_result[1] (%lld) != vec_expected[1] (%lld)\n", + vec_result[1], vec_expected[1]); +#else abort(); +#endif + } } int main() { int i; - vector unsigned int vec_unint; - vector signed int vec_int; + vector unsigned int vec_unint, vec_uns_int_expected, vec_uns_int_result; + vector signed int vec_int, vec_int_expected, vec_int_result; vector long long int vec_ll_int0, vec_ll_int1; + vector long long int vec_ll_int_expected, vec_ll_int_result; vector long long unsigned int vec_ll_uns_int0, vec_ll_uns_int1; + vector long long unsigned int vec_ll_uns_int_expected, vec_ll_uns_int_result; vector float vec_flt, vec_flt_result, vec_flt_expected; vector double vec_dble0, vec_dble1, vec_dble_result, vec_dble_expected; @@ -163,4 +291,67 @@ int main() vec_flt_expected = (vector float){0.00, 34.00, 0.00, 97.00}; vec_flt_result = vec_floato (vec_dble0); test_result_sp(ODD, vec_flt_result, vec_flt_expected); + + /* Convert single precision float to int */ + vec_flt = (vector float){-14.30, 34.00, 22.00, 97.00}; + vec_int_expected = (vector signed int){-14, 34, 22, 97}; + vec_int_result = vec_signed (vec_flt); + test_int_result (ALL, vec_int_result, vec_int_expected); + + /* Convert double precision float to long long int */ + vec_dble0 = (vector double){-124.930, 81234.49}; + vec_ll_int_expected = (vector long long signed int){-124, 81234}; + vec_ll_int_result = vec_signed (vec_dble0); + test_ll_int_result (vec_ll_int_result, vec_ll_int_expected); + + /* Convert two double precision vector float to vector int */ + vec_dble0 = (vector double){-124.930, 81234.49}; + vec_dble1 = (vector double){-24.370, 8354.99}; + vec_int_expected = (vector signed int){-124, 81234, -24, 8354}; + vec_int_result = vec_signed2 (vec_dble0, vec_dble1); + test_int_result (ALL, vec_int_result, vec_int_expected); + + /* Convert double precision vector float to vector int, even words */ + vec_dble0 = (vector double){-124.930, 81234.49}; + vec_int_expected = (vector signed int){-124, 0, 81234, 0}; + vec_int_result = vec_signede (vec_dble0); + test_int_result (EVEN, vec_int_result, vec_int_expected); + + /* Convert double precision vector float to vector int, odd words */ + vec_dble0 = (vector double){-124.930, 81234.49}; + vec_int_expected = (vector signed int){0, -124, 0, 81234}; + vec_int_result = vec_signedo (vec_dble0); + test_int_result (ODD, vec_int_result, vec_int_expected); + + /* Convert double precision float to long long unsigned int */ + vec_dble0 = (vector double){124.930, 8134.49}; + vec_ll_uns_int_expected = (vector long long unsigned int){124, 8134}; + vec_ll_uns_int_result = vec_unsigned (vec_dble0); + test_ll_unsigned_int_result (vec_ll_uns_int_result, + vec_ll_uns_int_expected); + + /* Convert two double precision vector float to vector unsigned int */ + vec_dble0 = (vector double){124.930, 8134.49}; + vec_dble1 = (vector double){24.370, 834.99}; + vec_uns_int_expected = (vector unsigned int){124, 8134, 24, 834}; + vec_uns_int_result = vec_unsigned2 (vec_dble0, vec_dble1); + test_unsigned_int_result (ALL, vec_uns_int_result, + vec_uns_int_expected); + + /* Convert double precision vector float to vector unsigned int, + even words */ + vec_dble0 = (vector double){3124.930, 8234.49}; + vec_uns_int_expected = (vector unsigned int){3124, 0, 8234, 0}; + vec_uns_int_result = vec_unsignede (vec_dble0); + test_unsigned_int_result (EVEN, vec_uns_int_result, + vec_uns_int_expected); + + /* Convert double precision vector float to vector unsigned int, + odd words */ + vec_dble0 = (vector double){1924.930, 81234.49}; + vec_uns_int_expected = (vector unsigned int){0, 1924, 0, 81234}; + vec_uns_int_result = vec_unsignedo (vec_dble0); + test_unsigned_int_result (ODD, vec_uns_int_result, + vec_uns_int_expected); } + diff --git a/gcc/testsuite/gcc.target/powerpc/builtins-3-vec_reve-runnable.c b/gcc/testsuite/gcc.target/powerpc/builtins-3-vec_reve-runnable.c new file mode 100644 index 00000000000..f7c3c3d9138 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/builtins-3-vec_reve-runnable.c @@ -0,0 +1,393 @@ +/* { dg-do run { target { powerpc*-*-linux* } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power7" } } */ +/* { dg-options "-O2 -mvsx -mcpu=power7" } */ + +#include <altivec.h> // vector + +#ifdef DEBUG +#include <stdio.h> +#endif + +#define VBC 0 +#define VSC 1 +#define VUC 2 +#define VBS 3 +#define VSS 4 +#define VUS 5 +#define VBI 6 +#define VI 7 +#define VUI 8 +#define VLLB 9 +#define VLLI 10 +#define VLLUI 11 +#define VF 12 +#define VD 13 + +union vector_value +{ + vector bool char vbc; + vector signed char vsc; + vector unsigned char vuc; + vector bool short vbs; + vector signed short vss; + vector unsigned short vus; + vector bool int vbi; + vector signed int vi; + vector unsigned int vui; + vector bool long long vllb; + vector long long signed int vlli; + vector long long unsigned int vllui; + vector float vf; + vector double vd; +} vec_element; + +struct vector_struct +{ + int vector_id; + int element_size; // element size in bytes + union vector_value vec; +} vec; + +void abort (void); + +void test_results(struct vector_struct *vec_result, + struct vector_struct *vec_expected) +{ + int i; + int num_elements; + if (vec_result->element_size != vec_expected->element_size) +#ifdef DEBUG + printf("vec_result->element_size != vec_expected->element_size\n"); +#else + abort(); +#endif + + if (vec_result->vector_id != vec_expected->vector_id) +#ifdef DEBUG + printf("vec_result->vector_id != vec_expected->vector_id\n"); +#else + abort(); +#endif + + num_elements = 16 / vec_result->element_size; + + for (i = 0; i<num_elements; i++) { + switch (vec_result->vector_id) { + case VBC: + if (vec_result->vec.vbc[i] != vec_expected->vec.vbc[i]) + { +#ifdef DEBUG + printf("vec_result->vec.vbc[%d] (%d) != ", + i, vec_result->vec.vbc[i]); + printf("vec_expected->vec.vbc[%d] (%d)\n", + i, vec_expected->vec.vbc[i]); +#else + abort(); +#endif + } + break; + + case VSC: + if (vec_result->vec.vsc[i] != vec_expected->vec.vsc[i]) + { +#ifdef DEBUG + printf("vec_result->vec.vsc[%d] (%d) != ", + i, vec_result->vec.vsc[i]); + printf("vec_expected->vec.vsc[%d] (%d)\n", + i, vec_expected->vec.vsc[i]); +#else + abort(); +#endif + } + break; + + case VUC: + if (vec_result->vec.vuc[i] != vec_expected->vec.vuc[i]) + { +#ifdef DEBUG + printf("vec_result->vec.vuc[%d] (%d) != ", + i, vec_result->vec.vuc[i]); + printf("vec_expected->vec.vuc[%d] (%d)\n", + i, vec_expected->vec.vuc[i]); +#else + abort(); +#endif + } + break; + + case VBS: + if (vec_result->vec.vbs[i] != vec_expected->vec.vbs[i]) + { +#ifdef DEBUG + printf("vec_result->vec.vbs[%d] (%d) != ", + i, vec_result->vec.vbs[i]); + printf("vec_expected->vec.vbs[%d] (%d)\n", + i, vec_expected->vec.vbs[i]); +#else + abort(); +#endif + } + break; + + case VSS: + if (vec_result->vec.vss[i] != vec_expected->vec.vss[i]) + { +#ifdef DEBUG + printf("vec_result->vec.vss[%d] (%d) != ", + i, vec_result->vec.vss[i]); + printf("vec_expected->vec.vss[%d] (%d)\n", + i, vec_expected->vec.vss[i]); +#else + abort(); +#endif + } + break; + + case VUS: + if (vec_result->vec.vus[i] != vec_expected->vec.vus[i]) + { +#ifdef DEBUG + printf("vec_result->vec.vus[%d] (%d) != ", + i, vec_expected->vec.vus[i]); + printf("vec_expected->vec.vus[%d] (%d)\n", + i, vec_expected->vec.vus[i]); +#else + abort(); +#endif + } + break; + + case VBI: + if (vec_result->vec.vbi[i] != vec_expected->vec.vbi[i]) + { +#ifdef DEBUG + printf("vec_result->vec.vbi[%d] (%d) != ", + i, vec_result->vec.vbi[i]); + printf("vec_expected->vec.vbi[%d] (%d)\n", + i, vec_expected->vec.vbi[i]); +#else + abort(); +#endif + } + break; + + case VI: + if (vec_result->vec.vi[i] != vec_expected->vec.vi[i]) + { +#ifdef DEBUG + printf("vec_result->vec.vi[%d] (%d) != ", + i, vec_result->vec.vi[i]); + printf("vec_expected->vec.vi[%d] (%d)\n", + i, vec_expected->vec.vi[i]); +#else + abort(); +#endif + } + break; + + case VUI: + if (vec_result->vec.vui[i] != vec_expected->vec.vui[i]) + { +#ifdef DEBUG + printf("vec_result->vec.vui[%d] (%u) != ", + i, vec_result->vec.vui[i]); + printf("vec_expected->vec.vui[%u] (%d)\n", + i, vec_expected->vec.vui[i]); +#else + abort(); +#endif + } + break; + + case VLLB: + if (vec_result->vec.vllb[i] != vec_expected->vec.vllb[i]) + { +#ifdef DEBUG + printf("vec_result->vec.vllb[%d] (%lld != ", + i, vec_result->vec.vllb[i]); + printf("vec_expected->vec.vllb[%lld] (%d)\n", + i, vec_expected->vec.vllb[i]); +#else + abort(); +#endif + } + break; + + case VLLI: + if (vec_result->vec.vlli[i] != vec_expected->vec.vlli[i]) + { +#ifdef DEBUG + printf("vec_result->vec.vlli[%d] (%d) != ", + i, vec_result->vec.vlli[i]); + printf("vec_expected->vec.vlli[%d] (%d)\n", + i, vec_expected->vec.vlli[i]); +#else + abort(); +#endif + } + break; + + case VLLUI: + if (vec_result->vec.vllui[i] != vec_expected->vec.vllui[i]) + { +#ifdef DEBUG + printf("vec_result->vec.vllui[%d] (%llu) != ", + i, vec_result->vec.vllui[i]); + printf("vec_expected->vec.vllui[%d] (%llu)\n", + i, vec_expected->vec.vllui[i]); +#else + abort(); +#endif + } + break; + + case VF: + if (vec_result->vec.vf[i] != vec_expected->vec.vf[i]) + { +#ifdef DEBUG + printf("vec_result->vec.vf[%d] (%f) != ", + i, vec_result->vec.vf[i]); + printf("vec_expected->vec.vf[%d] (%f)\n", + i, vec_expected->vec.vf[i]); +#else + abort(); +#endif + } + break; + + case VD: + if (vec_result->vec.vd[i] != vec_expected->vec.vd[i]) + { +#ifdef DEBUG + printf("vec_result->vec.vd[%d] (%f) != ", + i, vec_result->vec.vd[i]); + printf("vec_expected->vec.vd[%d] (%f)\n", + i, vec_expected->vec.vd[i]); +#else + abort(); +#endif + } + break; + + default: +#ifdef DEBUG + printf("Unknown case.\n"); +#else + abort(); +#endif + } + } +} + +int main() +{ + int i; + struct vector_struct vec_src, vec_expected, vec_result; + + vec_src.vec.vbc = (vector bool char){ 0, 1, 0, 0, 1, 1, 0, 0, + 0, 1, 1, 1, 0, 0, 0, 0 }; + vec_expected.vec.vbc = (vector bool char){ 0, 0, 0, 0, 1, 1, 1, 0, + 0, 0, 1, 1, 0, 0, 1, 0 }; + vec_result.element_size = vec_expected.element_size = 1; + vec_result.vector_id = vec_expected.vector_id = VBC; + vec_result.vec.vbc = vec_reve (vec_src.vec.vbc); + test_results(&vec_result, &vec_expected); + + vec_src.vec.vsc = (vector signed char){ 0, 1, -2, -3, 4, 5, -6, -7, 8, + 9, -10, -11, 12, 13, -14, -15 }; + vec_expected.vec.vsc = (vector signed char){ -15, -14, 13, 12, -11, -10, + 9, 8, -7, -6, 5, 4, -3, -2, + 1, 0 }; + vec_result.element_size = vec_expected.element_size = 1; + vec_result.vector_id = vec_expected.vector_id = VSC; + vec_result.vec.vsc = vec_reve (vec_src.vec.vsc); + test_results (&vec_result, &vec_expected); + + vec_src.vec.vuc = (vector unsigned char){ 10, 11, 12, 13, 14, 15, 16, 17, + 18, 19, 20, 21, 22, 23, 24, 25 }; + vec_expected.vec.vuc = (vector unsigned char){ 25, 24, 23, 22, 21, 20, + 19, 18, 17, 16, 15, 14, 13, + 12, 11, 10 }; + vec_result.element_size = vec_expected.element_size = 1; + vec_result.vector_id = vec_expected.vector_id = VUC; + vec_result.vec.vuc = vec_reve (vec_src.vec.vuc); + test_results (&vec_result, &vec_expected); + + vec_src.vec.vbs = (vector bool short){ 0, 0, 1, 1, 0, 1, 0, 1 }; + vec_expected.vec.vbs = (vector bool short){ 1, 0, 1, 0, 1, 1, 0, 0 }; + vec_result.element_size = vec_expected.element_size = 2; + vec_result.vector_id = vec_expected.vector_id = VBS; + vec_result.vec.vbs = vec_reve (vec_src.vec.vbs); + test_results (&vec_result, &vec_expected); + + vec_src.vec.vss = (vector signed short){ -1, -2, 3, 4, -5, -6, 7, 8 }; + vec_expected.vec.vss = (vector signed short){ 8, 7, -6, -5, 4, 3, -2, -1 }; + vec_result.element_size = vec_expected.element_size = 2; + vec_result.vector_id = vec_expected.vector_id = VSS; + vec_result.vec.vss = vec_reve (vec_src.vec.vss); + test_results (&vec_result, &vec_expected); + + vec_src.vec.vus = (vector unsigned short){ 11, 22, 33, 44, 55, 66, 77, 88 }; + vec_expected.vec.vus = (vector unsigned short){ 88, 77, 66, 55, + 44, 33, 22, 11 }; + vec_result.element_size = vec_expected.element_size = 2; + vec_result.vector_id = vec_expected.vector_id = VUS; + vec_result.vec.vus = vec_reve (vec_src.vec.vus); + test_results (&vec_result, &vec_expected); + + vec_src.vec.vbi = (vector bool int){ 0, 1, 1, 1 }; + vec_expected.vec.vbi = (vector bool int){ 1, 1, 1, 0 }; + vec_result.element_size = vec_expected.element_size = 4; + vec_result.vector_id = vec_expected.vector_id = VBI; + vec_result.vec.vbi = vec_reve (vec_src.vec.vbi); + test_results (&vec_result, &vec_expected); + + vec_src.vec.vi = (vector signed int){ -1, 3, -5, 1234567 }; + vec_expected.vec.vi = (vector signed int){1234567, -5, 3, -1}; + vec_result.element_size = vec_expected.element_size = 4; + vec_result.vector_id = vec_expected.vector_id = VI; + vec_result.vec.vi = vec_reve (vec_src.vec.vi); + test_results (&vec_result, &vec_expected); + + vec_src.vec.vui = (vector unsigned int){ 9, 11, 15, 2468013579 }; + vec_expected.vec.vui = (vector unsigned int){2468013579, 15, 11, 9}; + vec_result.element_size = vec_expected.element_size = 4; + vec_result.vector_id = vec_expected.vector_id = VUI; + vec_result.vec.vui = vec_reve (vec_src.vec.vui); + test_results (&vec_result, &vec_expected); + + vec_src.vec.vllb = (vector bool long long ){ 0, 1 }; + vec_expected.vec.vllb = (vector bool long long){1, 0}; + vec_result.element_size = vec_expected.element_size = 8; + vec_result.vector_id = vec_expected.vector_id = VLLB; + vec_result.vec.vllb = vec_reve (vec_src.vec.vllb); + test_results (&vec_result, &vec_expected); + + vec_src.vec.vlli = (vector long long int){ -12, -12345678901234 }; + vec_expected.vec.vlli = (vector long long int){-12345678901234, -12}; + vec_result.element_size = vec_expected.element_size = 8; + vec_result.vector_id = vec_expected.vector_id = VLLI; + vec_result.vec.vlli = vec_reve (vec_src.vec.vlli); + test_results (&vec_result, &vec_expected); + + vec_src.vec.vllui = (vector unsigned long long int){ 102, 9753108642 }; + vec_expected.vec.vllui = (vector unsigned long long int){9753108642, 102}; + vec_result.element_size = vec_expected.element_size = 8; + vec_result.vector_id = vec_expected.vector_id = VLLUI; + vec_result.vec.vllui = vec_reve (vec_src.vec.vllui); + test_results (&vec_result, &vec_expected); + + vec_src.vec.vf = (vector float){ -21., 3.5, -53., 78. }; + vec_expected.vec.vf = (vector float){78., -53, 3.5, -21}; + vec_result.element_size = vec_expected.element_size = 4; + vec_result.vector_id = vec_expected.vector_id = VF; + vec_result.vec.vf = vec_reve (vec_src.vec.vf); + test_results (&vec_result, &vec_expected); + + vec_src.vec.vd = (vector double){ 34.0, 97.0 }; + vec_expected.vec.vd = (vector double){97.0, 34.0}; + vec_result.element_size = vec_expected.element_size = 8; + vec_result.vector_id = vec_expected.vector_id = VD; + vec_result.vec.vd = vec_reve (vec_src.vec.vd); + test_results (&vec_result, &vec_expected); +} diff --git a/gcc/testsuite/gcc.target/powerpc/builtins-4-p9-runnable.c b/gcc/testsuite/gcc.target/powerpc/builtins-4-p9-runnable.c new file mode 100644 index 00000000000..8e8fcabbe82 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/builtins-4-p9-runnable.c @@ -0,0 +1,95 @@ +/* { dg-do run { target { powerpc*-*-* && { p9vector_hw } } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ +/* { dg-options "-mcpu=power9 -O2 " } */ + +#include <altivec.h> // vector + +void abort (void); + +int main() { + int i; + + vector signed char vsca, vscr, vscexpt; + vector unsigned char vuca, vucr, vucexpt; + vector signed short int vssa, vssr, vssexpt; + vector unsigned short int vusa, vusr, vusexpt; + vector signed int vsia, vsir, vsiexpt; + vector unsigned int vuia, vuir, vuiexpt; + vector signed long long vslla, vsllr, vsllexpt; + vector unsigned long long vulla, vullr, vullexpt; + + vsca = (vector signed char) {0, 1, 2, 3, 4, 5, 6, 7, + 8, 9, 10, 11, 12, 13, 14, 15}; + + vscexpt = (vector signed char) {8, 0, 1, 0, 2, 0, 1, 0, + 3, 0, 1, 0, 2, 0, 1, 0}; + + vuca = (vector unsigned char) {'0', '3', '6', '9', 'A', 'B', 'E', 'F', + 'G', 'H', 'I', 'J', 'K', 'L', 'M', 'N'}; + + vucexpt = (vector unsigned char) {4, 0, 1, 0, 0, 1, 0, 1, + 0, 3, 0, 1, 0, 2, 0, 1}; + + vssa = (vector short int) {0x1, 0x10, 0x100, 0x1000, + 0x2, 0x20, 0x200, 0x2000}; + + vssexpt = (vector short int) {0, 4, 8, 12, 1, 5, 9, 13}; + + vusa = (vector unsigned short int) {0x4, 0x40, 0x400, 0x4000, + 0x8, 0x80, 0x800, 0x8000}; + vusexpt = (vector unsigned short int) {2, 6, 10, 14, 3, 7, 11, 15}; + + vsia = (vector int) {0x10000, 0x100000, 0x1000000, 0x10000000}; + vsiexpt = (vector int){16, 20, 24, 28}; + + vuia = (vector unsigned int) {0x2, 0x20, 0x200, 0x2000}; + vuiexpt = (vector unsigned int){1, 5, 9, 13}; + + vslla = (vector long long) {0x0000000000010000LL, 0x0001000100010000LL}; + vsllexpt = (vector long long){16, 16}; + + vulla = (vector unsigned long long) {0x0000400000000000LL, 0x0080000000000000ULL}; + + vullexpt = (vector unsigned long long) {46, 55}; + + vscr = vec_cnttz (vsca); + vucr = vec_cnttz (vuca); + vssr = vec_cnttz (vssa); + vusr = vec_cnttz (vusa); + vsir = vec_cnttz (vsia); + vuir = vec_cnttz (vuia); + vsllr = vec_cnttz (vslla); + vullr = vec_cnttz (vulla); + + for (i=0; i<16; i++) { + if (vscr[i] != vscexpt[i]) + abort(); + + if (vucr[i] != vucexpt[i]) + abort(); + } + + for (i=0; i<8; i++) { + if (vssr[i] != vssexpt[i]) + abort(); + + if (vusr[i] != vusexpt[i]) + abort(); + } + + for (i=0; i<4; i++) { + if (vsir[i] != vsiexpt[i]) + abort(); + + if (vuir[i] != vuiexpt[i]) + abort(); + } + + for (i=0; i<2; i++) { + if (vsllr[i] != vsllexpt[i]) + abort(); + + if (vullr[i] != vullexpt[i]) + abort(); + } +} diff --git a/gcc/testsuite/gcc.target/powerpc/clone1.c b/gcc/testsuite/gcc.target/powerpc/clone1.c index 5c69db8e217..eb13a7b2dbd 100644 --- a/gcc/testsuite/gcc.target/powerpc/clone1.c +++ b/gcc/testsuite/gcc.target/powerpc/clone1.c @@ -2,6 +2,7 @@ /* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power8" } } */ /* { dg-options "-mcpu=power8 -O2" } */ /* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-require-effective-target ppc_cpu_supports_hw } */ /* Power9 (aka, ISA 3.0) has a MODSD instruction to do modulus, while Power8 (aka, ISA 2.07) has to do modulus with divide and multiply. Make sure diff --git a/gcc/testsuite/gcc.target/powerpc/clone2.c b/gcc/testsuite/gcc.target/powerpc/clone2.c new file mode 100644 index 00000000000..ecad5eb8e29 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/clone2.c @@ -0,0 +1,31 @@ +/* { dg-do run { target { powerpc*-*-linux* } } } */ +/* { dg-options "-mvsx -O2" } */ +/* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-require-effective-target ppc_cpu_supports_hw } */ + +#include <stddef.h> +#include <stdlib.h> + +/* Power9 (aka, ISA 3.0) has a MODSD instruction to do modulus, while Power8 + (aka, ISA 2.07) has to do modulus with divide and multiply. Make sure that + the basic support for target_clones runs. + + Restrict ourselves to Linux, since IFUNC might not be supported in other + operating systems. */ + +__attribute__((__target_clones__("cpu=power9,default"))) +long mod_func (long a, long b) +{ + return a % b; +} + +#define X 53L +#define Y 7L +int +main (void) +{ + if (mod_func (X, Y) != (X % Y)) + abort (); + + return 0; +} diff --git a/gcc/testsuite/gcc.target/powerpc/cpu-builtin-1.c b/gcc/testsuite/gcc.target/powerpc/cpu-builtin-1.c index 684c0f6d17d..c190f246231 100644 --- a/gcc/testsuite/gcc.target/powerpc/cpu-builtin-1.c +++ b/gcc/testsuite/gcc.target/powerpc/cpu-builtin-1.c @@ -4,6 +4,11 @@ void use_cpu_is_builtins (unsigned int *p) { + /* If GCC was configured to use an old GLIBC (before 2.23), the + __builtin_cpu_is and __builtin_cpu_supports built-in functions return 0, + and the compiler issues a warning that you need a newer glibc to use them. + Use #ifdef to avoid the warning. */ +#ifdef __BUILTIN_CPU_SUPPORTS__ p[0] = __builtin_cpu_is ("power9"); p[1] = __builtin_cpu_is ("power8"); p[2] = __builtin_cpu_is ("power7"); @@ -19,11 +24,15 @@ use_cpu_is_builtins (unsigned int *p) p[12] = __builtin_cpu_is ("ppc440"); p[13] = __builtin_cpu_is ("ppc405"); p[14] = __builtin_cpu_is ("ppc-cell-be"); +#else + p[0] = 0; +#endif } void use_cpu_supports_builtins (unsigned int *p) { +#ifdef __BUILTIN_CPU_SUPPORTS__ p[0] = __builtin_cpu_supports ("4xxmac"); p[1] = __builtin_cpu_supports ("altivec"); p[2] = __builtin_cpu_supports ("arch_2_05"); @@ -62,4 +71,9 @@ use_cpu_supports_builtins (unsigned int *p) p[35] = __builtin_cpu_supports ("ucache"); p[36] = __builtin_cpu_supports ("vcrypto"); p[37] = __builtin_cpu_supports ("vsx"); + p[38] = __builtin_cpu_supports ("darn"); + p[39] = __builtin_cpu_supports ("scv"); +#else + p[0] = 0; +#endif } diff --git a/gcc/testsuite/gcc.target/powerpc/dform-1.c b/gcc/testsuite/gcc.target/powerpc/dform-1.c index 12623f20262..37a30d1c92f 100644 --- a/gcc/testsuite/gcc.target/powerpc/dform-1.c +++ b/gcc/testsuite/gcc.target/powerpc/dform-1.c @@ -1,7 +1,7 @@ /* { dg-do compile { target { powerpc*-*-* && lp64 } } } */ /* { dg-require-effective-target powerpc_p9vector_ok } */ /* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ -/* { dg-options "-mcpu=power9 -mpower9-dform -O2 -mlra" } */ +/* { dg-options "-mcpu=power9 -mpower9-dform -O2" } */ #ifndef TYPE #define TYPE double diff --git a/gcc/testsuite/gcc.target/powerpc/dform-2.c b/gcc/testsuite/gcc.target/powerpc/dform-2.c index 86d65b5b1fd..b4c4199c0b3 100644 --- a/gcc/testsuite/gcc.target/powerpc/dform-2.c +++ b/gcc/testsuite/gcc.target/powerpc/dform-2.c @@ -1,7 +1,7 @@ /* { dg-do compile { target { powerpc*-*-* && lp64 } } } */ /* { dg-require-effective-target powerpc_p9vector_ok } */ /* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ -/* { dg-options "-mcpu=power9 -mpower9-dform -O2 -mlra" } */ +/* { dg-options "-mcpu=power9 -mpower9-dform -O2" } */ #ifndef TYPE #define TYPE float diff --git a/gcc/testsuite/gcc.target/powerpc/dform-3.c b/gcc/testsuite/gcc.target/powerpc/dform-3.c index b1c481fbf6d..c261c4e6f5d 100644 --- a/gcc/testsuite/gcc.target/powerpc/dform-3.c +++ b/gcc/testsuite/gcc.target/powerpc/dform-3.c @@ -1,7 +1,7 @@ /* { dg-do compile { target { powerpc*-*-* && lp64 } } } */ /* { dg-require-effective-target powerpc_p9vector_ok } */ /* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ -/* { dg-options "-mcpu=power9 -mpower9-dform -O2 -mlra" } */ +/* { dg-options "-mcpu=power9 -mpower9-dform -O2" } */ #ifndef TYPE #define TYPE vector double diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-missing-lhs.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-missing-lhs.c new file mode 100644 index 00000000000..6add9038288 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-missing-lhs.c @@ -0,0 +1,24 @@ +/* This test is meant to verify that the gimple-folding does not + occur when the LHS portion of an expression is missing. + The intent of this test is to verify that we do not generate an ICE. + This was noticed during debug of PR81317. */ + +/* { dg-do compile } */ +/* { dg-require-effective-target powerpc_altivec_ok } */ +/* { dg-options "-maltivec" } */ + +#include <altivec.h> + +vector signed short +test1_nolhs (vector bool short x, vector signed short y) +{ + vec_add (x, y); + return vec_add (x, y); +} + +vector signed short +test2_nolhs (vector signed short x, vector bool short y) +{ + vec_add (x, y); + return vec_add (x, y); +} diff --git a/gcc/testsuite/gcc.target/powerpc/mmx-check.h b/gcc/testsuite/gcc.target/powerpc/mmx-check.h new file mode 100644 index 00000000000..e08077f6d80 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/mmx-check.h @@ -0,0 +1,35 @@ +#include <stdio.h> +#include <stdlib.h> + +static void mmx_test (void); + +static void +__attribute__ ((noinline)) +do_test (void) +{ + mmx_test (); +} + +int +main () + { +#ifdef __BUILTIN_CPU_SUPPORTS__ + /* Many MMX intrinsics are simpler / faster to implement by + transferring the __m64 (long int) to vector registers for SIMD + operations. To be efficient we also need the direct register + transfer instructions from POWER8. So we can test for + arch_2_07. */ + if ( __builtin_cpu_supports ("arch_2_07") ) + { + do_test (); +#ifdef DEBUG + printf ("PASSED\n"); +#endif + } +#ifdef DEBUG + else + printf ("SKIPPED\n"); +#endif +#endif /* __BUILTIN_CPU_SUPPORTS__ */ + return 0; + } diff --git a/gcc/testsuite/gcc.target/powerpc/mmx-packs.c b/gcc/testsuite/gcc.target/powerpc/mmx-packs.c new file mode 100644 index 00000000000..18faa5a18eb --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/mmx-packs.c @@ -0,0 +1,91 @@ +/* { dg-do run } */ +/* { dg-options "-O3 -mpower8-vector" } */ +/* { dg-require-effective-target lp64 } */ +/* { dg-require-effective-target p8vector_hw } */ + +#define NO_WARN_X86_INTRINSICS 1 +#include <mmintrin.h> +#include "mmx-check.h" + +#ifndef TEST +#define TEST mmx_test +#endif + +static void +__attribute__ ((noinline)) +check_packs_pu16 (unsigned long long int src1, unsigned long long int src2, + unsigned long long int res_ref) +{ + unsigned long long int res; + + res = (unsigned long long int) _mm_packs_pu16 ((__m64 ) src1, (__m64 ) src2); + + if (res != res_ref) + abort (); +} + +static void +__attribute__ ((noinline)) +check_packs_pi16 (unsigned long long int src1, unsigned long long int src2, + unsigned long long int res_ref) +{ + unsigned long long int res; + + res = (unsigned long long int) _mm_packs_pi16 ((__m64 ) src1, (__m64 ) src2); + + + if (res != res_ref) + abort (); +} + +static void +__attribute__ ((noinline)) +check_packs_pi32 (unsigned long long int src1, unsigned long long int src2, + unsigned long long int res_ref) +{ + unsigned long long int res; + + res = (unsigned long long int) _mm_packs_pi32 ((__m64 ) src1, (__m64 ) src2); + + if (res != res_ref) + abort (); +} + +static unsigned long long int src1[] = + { 0xffff0000fffe0000UL, 0x0001000000020000UL, 0xfffffffffffffffeUL, + 0x0000000100000002UL, 0x0001000200030004UL, 0xfffffffefffdfffcUL, + 0x0100020003000400UL, 0xff00fe01fe02fe03UL }; + +static unsigned long long int src2[] = + { 0xfffffffdfffffffcUL, 0x0000000200000003UL, 0xfffffffdfffffffcUL, + 0x0000000300000004UL, 0x0005000600070008UL, 0xfffbfffafff9fff8UL, + 0x0005000600070008UL, 0xfffbfffafff9fff8UL }; + +static unsigned long long int res_pi16[] = + { 0xfffdfffcff00fe00UL, 0x0002000301000200UL, 0xfffdfffcfffffffeUL, + 0x0003000400010002UL, 0x0506070801020304UL, 0xfbfaf9f8fffefdfcUL, + 0x050607087f7f7f7fUL, 0xfbfaf9f880808080UL }; + +static unsigned long long int res_pi32[] = + { 0xfffdfffc80008000UL, 0x000200037fff7fffUL, 0xfffdfffcfffffffeUL, + 0x0003000400010002UL, 0x7fff7fff7fff7fffUL, 0x80008000fffe8000UL, + 0x7fff7fff7fff7fffUL, 0x8000800080008000UL }; + +static unsigned long long int res_pu16[] = + { 0x0000000000000000UL, 0x0002000301000200UL, 0x0000000000000000UL, + 0x0003000400010002UL, 0x0506070801020304UL, 0x000000000000000UL, + 0x5060708ffffffffUL, 0x0000000000000000UL }; + +static void +TEST () +{ + long i; + + for (i = 0; i < 8; i++) + { + check_packs_pu16 (src1[i], src2[i], res_pu16[i]); + check_packs_pi16 (src1[i], src2[i], res_pi16[i]); + check_packs_pi32 (src1[i], src2[i], res_pi32[i]); + } +} + diff --git a/gcc/testsuite/gcc.target/powerpc/mmx-packssdw-1.c b/gcc/testsuite/gcc.target/powerpc/mmx-packssdw-1.c new file mode 100644 index 00000000000..8698d55f012 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/mmx-packssdw-1.c @@ -0,0 +1,60 @@ +/* { dg-do run } */ +/* { dg-options "-O3 -mpower8-vector" } */ +/* { dg-require-effective-target lp64 } */ +/* { dg-require-effective-target p8vector_hw } */ + +#define NO_WARN_X86_INTRINSICS 1 +#ifndef CHECK_H +#define CHECK_H "mmx-check.h" +#endif + +#ifndef TEST +#define TEST mmx_test +#endif + +#include CHECK_H + +#include <mmintrin.h> + +static __m64 +__attribute__((noinline, unused)) +test (__m64 s1, __m64 s2) +{ + return _mm_packs_pi32 (s1, s2); +} + +static void +TEST (void) +{ + __m64_union s1, s2; + __m64_union u; + __m64_union e; + int i; + + s1.as_m64 = _mm_set_pi32 (2134, -128); + s2.as_m64 = _mm_set_pi32 (41124, 234); + u.as_m64 = test (s1.as_m64, s2.as_m64); + + for (i = 0; i < 2; i++) + { + if (s1.as_int[i] > 32767) + e.as_short[i] = 32767; + else if (s1.as_int[i] < -32768) + e.as_short[i] = -32768; + else + e.as_short[i] = s1.as_int[i]; + } + + for (i = 0; i < 2; i++) + { + if (s2.as_int[i] > 32767) + e.as_short[i+2] = 32767; + else if (s2.as_int[i] < -32768) + e.as_short[i+2] = -32768; + else + e.as_short[i+2] = s2.as_int[i]; + } + + if (u.as_m64 != e.as_m64) + abort (); +} diff --git a/gcc/testsuite/gcc.target/powerpc/mmx-packsswb-1.c b/gcc/testsuite/gcc.target/powerpc/mmx-packsswb-1.c new file mode 100644 index 00000000000..96bea7b81ab --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/mmx-packsswb-1.c @@ -0,0 +1,60 @@ +/* { dg-do run } */ +/* { dg-options "-O3 -mpower8-vector" } */ +/* { dg-require-effective-target lp64 } */ +/* { dg-require-effective-target p8vector_hw } */ + +#define NO_WARN_X86_INTRINSICS 1 +#ifndef CHECK_H +#define CHECK_H "mmx-check.h" +#endif + +#ifndef TEST +#define TEST mmx_test +#endif + +#include CHECK_H + +#include <mmintrin.h> + +static __m64 +__attribute__((noinline, unused)) +test (__m64 s1, __m64 s2) +{ + return _mm_packs_pi16 (s1, s2); +} + +static void +TEST (void) +{ + __m64_union s1, s2; + __m64_union u; + __m64_union e; + int i; + + s1.as_m64 = _mm_set_pi16 (2134, -128, 1234, 6354); + s2.as_m64 = _mm_set_pi16 (41124, 234, 2344, 2354); + u.as_m64 = test (s1.as_m64, s2.as_m64); + + for (i = 0; i < 4; i++) + { + if (s1.as_short[i] > 127) + e.as_char[i] = 127; + else if (s1.as_short[i] < -128) + e.as_char[i] = -128; + else + e.as_char[i] = s1.as_short[i]; + } + + for (i = 0; i < 4; i++) + { + if (s2.as_short[i] > 127) + e.as_char[i+4] = 127; + else if (s2.as_short[i] < -128) + e.as_char[i+4] = -128; + else + e.as_char[i+4] = s2.as_short[i]; + } + + if (u.as_m64 != e.as_m64) + abort (); +} diff --git a/gcc/testsuite/gcc.target/powerpc/mmx-packuswb-1.c b/gcc/testsuite/gcc.target/powerpc/mmx-packuswb-1.c new file mode 100644 index 00000000000..029d5687d71 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/mmx-packuswb-1.c @@ -0,0 +1,50 @@ +/* { dg-do run } */ +/* { dg-options "-O3" } */ +/* { dg-require-effective-target lp64 } */ +/* { dg-require-effective-target p8vector_hw } */ + +#ifndef CHECK_H +#define CHECK_H "mmx-check.h" +#endif + +#ifndef TEST +#define TEST mmx_test +#endif + +#include CHECK_H + +#include <mmintrin.h> + +static __m64 +__attribute__((noinline, unused)) +test (__m64 s1, __m64 s2) +{ + return _mm_packs_pu16 (s1, s2); +} + +static void +TEST (void) +{ + __m64_union s1, s2; + __m64_union u; + __m64_union e; + int i, tmp; + + s1.as_m64 = _mm_set_pi16 (1, 2, 3, 4); + s2.as_m64 = _mm_set_pi16 (-9, -10, -11, -12); + u.as_m64 = test (s1.as_m64, s2.as_m64); + + for (i=0; i<4; i++) + { + tmp = s1.as_short[i]<0 ? 0 : s1.as_short[i]; + tmp = tmp>255 ? 255 : tmp; + e.as_char[i] = tmp; + + tmp = s2.as_short[i]<0 ? 0 : s2.as_short[i]; + tmp = tmp>255 ? 255 : tmp; + e.as_char[i+4] = tmp; + } + + if (u.as_m64 != e.as_m64) + abort (); +} diff --git a/gcc/testsuite/gcc.target/powerpc/mmx-paddb-1.c b/gcc/testsuite/gcc.target/powerpc/mmx-paddb-1.c new file mode 100644 index 00000000000..46b0584549e --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/mmx-paddb-1.c @@ -0,0 +1,42 @@ +/* { dg-do run } */ +/* { dg-options "-O3 -mpower8-vector" } */ +/* { dg-require-effective-target lp64 } */ +/* { dg-require-effective-target p8vector_hw } */ + +#define NO_WARN_X86_INTRINSICS 1 +#ifndef CHECK_H +#define CHECK_H "mmx-check.h" +#endif + +#ifndef TEST +#define TEST mmx_test +#endif + +#include CHECK_H + +#include <mmintrin.h> + +static __m64 +__attribute__((noinline, unused)) +test (__m64 s1, __m64 s2) +{ + return _mm_add_pi8 (s1, s2); +} + +static void +TEST (void) +{ + __m64_union u, s1, s2; + __m64_union e; + int i; + + s1.as_m64 = _mm_set_pi8 (1, 2, 3, 4, 10, 20, 30, 90); + s2.as_m64 = _mm_set_pi8 (88, 44, 33, 22, 11, 98, 76, -100); + u.as_m64 = test (s1.as_m64, s2.as_m64); + + for (i = 0; i < 8; i++) + e.as_char[i] = s1.as_char[i] + s2.as_char[i]; + + if (u.as_m64 != e.as_m64) + abort (); +} diff --git a/gcc/testsuite/gcc.target/powerpc/mmx-paddd-1.c b/gcc/testsuite/gcc.target/powerpc/mmx-paddd-1.c new file mode 100644 index 00000000000..a006dda0ee4 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/mmx-paddd-1.c @@ -0,0 +1,42 @@ +/* { dg-do run } */ +/* { dg-options "-O3 -mpower8-vector" } */ +/* { dg-require-effective-target lp64 } */ +/* { dg-require-effective-target p8vector_hw } */ + +#define NO_WARN_X86_INTRINSICS 1 +#ifndef CHECK_H +#define CHECK_H "mmx-check.h" +#endif + +#ifndef TEST +#define TEST mmx_test +#endif + +#include CHECK_H + +#include <mmintrin.h> + +static __m64 +__attribute__((noinline, unused)) +test (__m64 s1, __m64 s2) +{ + return _mm_add_pi32 (s1, s2); +} + +static void +TEST (void) +{ + __m64_union u, s1, s2; + __m64_union e; + int i; + + s1.as_m64 = _mm_set_pi32 (30, 90); + s2.as_m64 = _mm_set_pi32 (76, -100); + u.as_m64 = test (s1.as_m64, s2.as_m64); + + for (i = 0; i < 2; i++) + e.as_int[i] = s1.as_int[i] + s2.as_int[i]; + + if (u.as_m64 != e.as_m64) + abort (); +} diff --git a/gcc/testsuite/gcc.target/powerpc/mmx-paddsb-1.c b/gcc/testsuite/gcc.target/powerpc/mmx-paddsb-1.c new file mode 100644 index 00000000000..5722302095e --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/mmx-paddsb-1.c @@ -0,0 +1,51 @@ +/* { dg-do run } */ +/* { dg-options "-O3 -mpower8-vector" } */ +/* { dg-require-effective-target lp64 } */ +/* { dg-require-effective-target p8vector_hw } */ + +#define NO_WARN_X86_INTRINSICS 1 +#ifndef CHECK_H +#define CHECK_H "mmx-check.h" +#endif + +#ifndef TEST +#define TEST mmx_test +#endif + +#include CHECK_H + +#include <mmintrin.h> + +static __m64 +__attribute__((noinline, unused)) +test (__m64 s1, __m64 s2) +{ + return _mm_adds_pi8 (s1, s2); +} + +static void +TEST (void) +{ + __m64_union u, s1, s2; + __m64_union e; + int i, tmp; + + s1.as_m64 = _mm_set_pi8 (1, 2, 3, 4, 10, 20, 30, 90); + s2.as_m64 = _mm_set_pi8 (88, 44, 33, 22, 11, 98, 76, -100); + u.as_m64 = test (s1.as_m64, s2.as_m64); + + for (i = 0; i < 8; i++) + { + tmp = s1.as_signed_char[i] + s2.as_signed_char[i]; + + if (tmp > 127) + tmp = 127; + if (tmp < -128) + tmp = -128; + + e.as_signed_char[i] = tmp; + } + + if (u.as_m64 != e.as_m64) + abort (); +} diff --git a/gcc/testsuite/gcc.target/powerpc/mmx-paddsw-1.c b/gcc/testsuite/gcc.target/powerpc/mmx-paddsw-1.c new file mode 100644 index 00000000000..f7518b4dbae --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/mmx-paddsw-1.c @@ -0,0 +1,51 @@ +/* { dg-do run } */ +/* { dg-options "-O3 -mpower8-vector" } */ +/* { dg-require-effective-target lp64 } */ +/* { dg-require-effective-target p8vector_hw } */ + +#define NO_WARN_X86_INTRINSICS 1 +#ifndef CHECK_H +#define CHECK_H "mmx-check.h" +#endif + +#ifndef TEST +#define TEST mmx_test +#endif + +#include CHECK_H + +#include <mmintrin.h> + +static __m64 +__attribute__((noinline, unused)) +test (__m64 s1, __m64 s2) +{ + return _mm_adds_pi16 (s1, s2); +} + +static void +TEST (void) +{ + __m64_union u, s1, s2; + __m64_union e; + int i, tmp; + + s1.as_m64 = _mm_set_pi16 (1, 2, 3, 4); + s2.as_m64 = _mm_set_pi16 (11, 98, 76, -100); + u.as_m64 = test (s1.as_m64, s2.as_m64); + + for (i = 0; i < 4; i++) + { + tmp = s1.as_short[i] + s2.as_short[i]; + + if (tmp > 32767) + tmp = 32767; + if (tmp < -32768) + tmp = -32768; + + e.as_short[i] = tmp; + } + + if (u.as_m64 != e.as_m64) + abort (); +} diff --git a/gcc/testsuite/gcc.target/powerpc/mmx-paddusb-1.c b/gcc/testsuite/gcc.target/powerpc/mmx-paddusb-1.c new file mode 100644 index 00000000000..a209e3e30dd --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/mmx-paddusb-1.c @@ -0,0 +1,51 @@ +/* { dg-do run } */ +/* { dg-options "-O3 -mpower8-vector" } */ +/* { dg-require-effective-target lp64 } */ +/* { dg-require-effective-target p8vector_hw } */ + +#define NO_WARN_X86_INTRINSICS 1 +#ifndef CHECK_H +#define CHECK_H "mmx-check.h" +#endif + +#ifndef TEST +#define TEST mmx_test +#endif + +#include CHECK_H + +#include <mmintrin.h> + +static __m64 +__attribute__((noinline, unused)) +test (__m64 s1, __m64 s2) +{ + return _mm_adds_pu8 (s1, s2); +} + +static void +TEST (void) +{ + __m64_union u, s1, s2; + __m64_union e; + int i, tmp; + + s1.as_m64 = _mm_set_pi8 (30, 2, 3, 4, 10, 20, 30, 90); + s2.as_m64 = _mm_set_pi8 (88, 44, 33, 22, 11, 98, 76, 100); + u.as_m64 = test (s1.as_m64, s2.as_m64); + + for (i = 0; i < 8; i++) + { + tmp = s1.as_char[i] + s2.as_char[i]; + + if (tmp > 255) + tmp = -1; + if (tmp < 0) + tmp = 0; + + e.as_char[i] = tmp; + } + + if (u.as_m64 != e.as_m64) + abort (); +} diff --git a/gcc/testsuite/gcc.target/powerpc/mmx-paddusw-1.c b/gcc/testsuite/gcc.target/powerpc/mmx-paddusw-1.c new file mode 100644 index 00000000000..b46b7f636bb --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/mmx-paddusw-1.c @@ -0,0 +1,52 @@ +/* { dg-do run } */ +/* { dg-options "-O3 -mpower8-vector" } */ +/* { dg-require-effective-target lp64 } */ +/* { dg-require-effective-target p8vector_hw } */ + +#define NO_WARN_X86_INTRINSICS 1 +#ifndef CHECK_H +#define CHECK_H "mmx-check.h" +#endif + +#ifndef TEST +#define TEST mmx_test +#endif + +#include CHECK_H + +#include <mmintrin.h> + +static __m64 +__attribute__((noinline, unused)) +test (__m64 s1, __m64 s2) +{ + return _mm_adds_pu16 (s1, s2); +} + +static void +TEST (void) +{ + __m64_union u, s1, s2; + __m64_union e; + int i, tmp; + + s1.as_m64 = _mm_set_pi16 (1, 2, 3, 4); + s2.as_m64 = _mm_set_pi16 (11, 98, 76, 100); + u.as_m64 = test (s1.as_m64, s2.as_m64); + + for (i = 0; i < 4; i++) + { + tmp = (unsigned short)s1.as_short[i] + (unsigned short)s2.as_short[i]; + + if (tmp > 65535) + tmp = -1; + + if (tmp < 0) + tmp = 0; + + e.as_short[i] = tmp; + } + + if (u.as_m64 != e.as_m64) + abort (); +} diff --git a/gcc/testsuite/gcc.target/powerpc/mmx-paddw-1.c b/gcc/testsuite/gcc.target/powerpc/mmx-paddw-1.c new file mode 100644 index 00000000000..748fe2b5703 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/mmx-paddw-1.c @@ -0,0 +1,42 @@ +/* { dg-do run } */ +/* { dg-options "-O3 -mpower8-vector" } */ +/* { dg-require-effective-target lp64 } */ +/* { dg-require-effective-target p8vector_hw } */ + +#define NO_WARN_X86_INTRINSICS 1 +#ifndef CHECK_H +#define CHECK_H "mmx-check.h" +#endif + +#ifndef TEST +#define TEST mmx_test +#endif + +#include CHECK_H + +#include <mmintrin.h> + +static __m64 +__attribute__((noinline, unused)) +test (__m64 s1, __m64 s2) +{ + return _mm_add_pi16 (s1, s2); +} + +static void +TEST (void) +{ + __m64_union u, s1, s2; + __m64_union e; + int i; + + s1.as_m64 = _mm_set_pi16 (10, 20, 30, 90); + s2.as_m64 = _mm_set_pi16 (11, 98, 76, -100); + u.as_m64 = test (s1.as_m64, s2.as_m64); + + for (i = 0; i < 4; i++) + e.as_short[i] = s1.as_short[i] + s2.as_short[i]; + + if (u.as_m64 != e.as_m64) + abort (); +} diff --git a/gcc/testsuite/gcc.target/powerpc/mmx-pcmpeqb-1.c b/gcc/testsuite/gcc.target/powerpc/mmx-pcmpeqb-1.c new file mode 100644 index 00000000000..c779b26e691 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/mmx-pcmpeqb-1.c @@ -0,0 +1,42 @@ +/* { dg-do run } */ +/* { dg-options "-O3 -mpower8-vector" } */ +/* { dg-require-effective-target lp64 } */ +/* { dg-require-effective-target p8vector_hw } */ + +#define NO_WARN_X86_INTRINSICS 1 +#ifndef CHECK_H +#define CHECK_H "mmx-check.h" +#endif + +#ifndef TEST +#define TEST mmx_test +#endif + +#include CHECK_H + +#include <mmintrin.h> + +static __m64 +__attribute__((noinline, unused)) +test (__m64 s1, __m64 s2) +{ + return _mm_cmpeq_pi8 (s1, s2); +} + +static void +TEST (void) +{ + __m64_union u, s1, s2; + __m64_union e; + int i; + + s1.as_m64 = _mm_set_pi8 (1, 2, 3, 4, 10, 20, 30, 90); + s2.as_m64 = _mm_set_pi8 (88, 44, 3, 22, 11, 98, 30, 100); + u.as_m64 = test (s1.as_m64, s2.as_m64); + + for (i = 0; i < 8; i++) + e.as_char[i] = (s1.as_char[i] == s2.as_char[i]) ? -1:0; + + if (u.as_m64 != e.as_m64) + abort (); +} diff --git a/gcc/testsuite/gcc.target/powerpc/mmx-pcmpeqd-1.c b/gcc/testsuite/gcc.target/powerpc/mmx-pcmpeqd-1.c new file mode 100644 index 00000000000..a7807a2fdd9 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/mmx-pcmpeqd-1.c @@ -0,0 +1,42 @@ +/* { dg-do run } */ +/* { dg-options "-O3 -mpower8-vector" } */ +/* { dg-require-effective-target lp64 } */ +/* { dg-require-effective-target p8vector_hw } */ + +#define NO_WARN_X86_INTRINSICS 1 +#ifndef CHECK_H +#define CHECK_H "mmx-check.h" +#endif + +#ifndef TEST +#define TEST mmx_test +#endif + +#include CHECK_H + +#include <mmintrin.h> + +static __m64 +__attribute__((noinline, unused)) +test (__m64 s1, __m64 s2) +{ + return _mm_cmpeq_pi32 (s1, s2); +} + +static void +TEST (void) +{ + __m64_union u, s1, s2; + __m64_union e; + int i; + + s1.as_m64 = _mm_set_pi32 (98, 25); + s2.as_m64 = _mm_set_pi32 (98, -100); + u.as_m64 = test (s1.as_m64, s2.as_m64); + + for (i = 0; i < 2; i++) + e.as_int[i] = (s1.as_int[i] == s2.as_int[i]) ? -1:0; + + if (u.as_m64 != e.as_m64) + abort (); +} diff --git a/gcc/testsuite/gcc.target/powerpc/mmx-pcmpeqw-1.c b/gcc/testsuite/gcc.target/powerpc/mmx-pcmpeqw-1.c new file mode 100644 index 00000000000..e25fd54c6b5 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/mmx-pcmpeqw-1.c @@ -0,0 +1,42 @@ +/* { dg-do run } */ +/* { dg-options "-O3 -mpower8-vector" } */ +/* { dg-require-effective-target lp64 } */ +/* { dg-require-effective-target p8vector_hw } */ + +#define NO_WARN_X86_INTRINSICS 1 +#ifndef CHECK_H +#define CHECK_H "mmx-check.h" +#endif + +#ifndef TEST +#define TEST mmx_test +#endif + +#include CHECK_H + +#include <mmintrin.h> + +static __m64 +__attribute__((noinline, unused)) +test (__m64 s1, __m64 s2) +{ + return _mm_cmpeq_pi16 (s1, s2); +} + +static void +TEST (void) +{ + __m64_union u, s1, s2; + __m64_union e; + int i; + + s1.as_m64 = _mm_set_pi16 (20, 30, 90, 80); + s2.as_m64 = _mm_set_pi16 (34, 78, 90, 6); + u.as_m64 = test (s1.as_m64, s2.as_m64); + + for (i = 0; i < 4; i++) + e.as_short[i] = (s1.as_short[i] == s2.as_short[i]) ? -1:0; + + if (u.as_m64 != e.as_m64) + abort (); +} diff --git a/gcc/testsuite/gcc.target/powerpc/mmx-pcmpgtb-1.c b/gcc/testsuite/gcc.target/powerpc/mmx-pcmpgtb-1.c new file mode 100644 index 00000000000..7f841b0b26e --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/mmx-pcmpgtb-1.c @@ -0,0 +1,42 @@ +/* { dg-do run } */ +/* { dg-options "-O3 -mpower8-vector" } */ +/* { dg-require-effective-target lp64 } */ +/* { dg-require-effective-target p8vector_hw } */ + +#define NO_WARN_X86_INTRINSICS 1 +#ifndef CHECK_H +#define CHECK_H "mmx-check.h" +#endif + +#ifndef TEST +#define TEST mmx_test +#endif + +#include CHECK_H + +#include <mmintrin.h> + +static __m64 +__attribute__((noinline, unused)) +test (__m64 s1, __m64 s2) +{ + return _mm_cmpgt_pi8 (s1, s2); +} + +static void +TEST (void) +{ + __m64_union u, s1, s2; + __m64_union e; + int i; + + s1.as_m64 = _mm_set_pi8 (1, 2, 3, 4, 10, 20, 30, 90); + s2.as_m64 = _mm_set_pi8 (88, 44, 3, 22, 11, 98, 28, 100); + u.as_m64 = test (s1.as_m64, s2.as_m64); + + for (i = 0; i < 8; i++) + e.as_char[i] = (s1.as_char[i] > s2.as_char[i]) ? -1 : 0; + + if (u.as_m64 != e.as_m64) + abort (); +} diff --git a/gcc/testsuite/gcc.target/powerpc/mmx-pcmpgtd-1.c b/gcc/testsuite/gcc.target/powerpc/mmx-pcmpgtd-1.c new file mode 100644 index 00000000000..9f503b5ec9e --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/mmx-pcmpgtd-1.c @@ -0,0 +1,42 @@ +/* { dg-do run } */ +/* { dg-options "-O3 -mpower8-vector" } */ +/* { dg-require-effective-target lp64 } */ +/* { dg-require-effective-target p8vector_hw } */ + +#define NO_WARN_X86_INTRINSICS 1 +#ifndef CHECK_H +#define CHECK_H "mmx-check.h" +#endif + +#ifndef TEST +#define TEST mmx_test +#endif + +#include CHECK_H + +#include <mmintrin.h> + +static __m64 +__attribute__((noinline, unused)) +test (__m64 s1, __m64 s2) +{ + return _mm_cmpgt_pi32 (s1, s2); +} + +static void +TEST (void) +{ + __m64_union u, s1, s2; + __m64_union e; + int i; + + s1.as_m64 = _mm_set_pi32 (99, 25); + s2.as_m64 = _mm_set_pi32 (98, -100); + u.as_m64 = test (s1.as_m64, s2.as_m64); + + for (i = 0; i < 2; i++) + e.as_int[i] = (s1.as_int[i] > s2.as_int[i]) ? -1:0; + + if (u.as_m64 != e.as_m64) + abort (); +} diff --git a/gcc/testsuite/gcc.target/powerpc/mmx-pcmpgtw-1.c b/gcc/testsuite/gcc.target/powerpc/mmx-pcmpgtw-1.c new file mode 100644 index 00000000000..85716937e0d --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/mmx-pcmpgtw-1.c @@ -0,0 +1,42 @@ +/* { dg-do run } */ +/* { dg-options "-O3 -mpower8-vector" } */ +/* { dg-require-effective-target lp64 } */ +/* { dg-require-effective-target p8vector_hw } */ + +#define NO_WARN_X86_INTRINSICS 1 +#ifndef CHECK_H +#define CHECK_H "mmx-check.h" +#endif + +#ifndef TEST +#define TEST mmx_test +#endif + +#include CHECK_H + +#include <mmintrin.h> + +static __m64 +__attribute__((noinline, unused)) +test (__m64 s1, __m64 s2) +{ + return _mm_cmpgt_pi16 (s1, s2); +} + +static void +TEST (void) +{ + __m64_union u, s1, s2; + __m64_union e; + int i; + + s1.as_m64 = _mm_set_pi16 (20, 30, 90, 80); + s2.as_m64 = _mm_set_pi16 (34, 78, 90, 6); + u.as_m64 = test (s1.as_m64, s2.as_m64); + + for (i = 0; i < 4; i++) + e.as_short[i] = (s1.as_short[i] > s2.as_short[i]) ? -1:0; + + if (u.as_m64 != e.as_m64) + abort (); +} diff --git a/gcc/testsuite/gcc.target/powerpc/mmx-pmaddwd-1.c b/gcc/testsuite/gcc.target/powerpc/mmx-pmaddwd-1.c new file mode 100644 index 00000000000..220b4f65209 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/mmx-pmaddwd-1.c @@ -0,0 +1,43 @@ +/* { dg-do run } */ +/* { dg-options "-O3 -mpower8-vector" } */ +/* { dg-require-effective-target lp64 } */ +/* { dg-require-effective-target p8vector_hw } */ + +#define NO_WARN_X86_INTRINSICS 1 +#ifndef CHECK_H +#define CHECK_H "mmx-check.h" +#endif + +#ifndef TEST +#define TEST mmx_test +#endif + +#include CHECK_H + +#include <mmintrin.h> + +static __m64 +__attribute__((noinline, unused)) +test (__m64 s1, __m64 s2) +{ + return _mm_madd_pi16 (s1, s2); +} + +static void +TEST (void) +{ + __m64_union u, s1, s2; + __m64_union e; + int i; + + s1.as_m64 = _mm_set_pi16 (2134, 3334, 1234, 6354); + s2.as_m64 = _mm_set_pi16 (1, 3, 4, 5); + u.as_m64 = test (s1.as_m64, s2.as_m64); + + for (i = 0; i < 2; i++) + e.as_int[i] = (s1.as_short[i * 2] * s2.as_short[i * 2]) + + (s1.as_short[(i * 2) + 1] * s2.as_short[(i * 2) + 1]); + + if (u.as_m64 != e.as_m64) + abort (); +} diff --git a/gcc/testsuite/gcc.target/powerpc/mmx-pmulhw-1.c b/gcc/testsuite/gcc.target/powerpc/mmx-pmulhw-1.c new file mode 100644 index 00000000000..79b7c7b1838 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/mmx-pmulhw-1.c @@ -0,0 +1,46 @@ +/* { dg-do run } */ +/* { dg-options "-O3 -mpower8-vector" } */ +/* { dg-require-effective-target lp64 } */ +/* { dg-require-effective-target p8vector_hw } */ + +#define NO_WARN_X86_INTRINSICS 1 +#ifndef CHECK_H +#define CHECK_H "mmx-check.h" +#endif + +#ifndef TEST +#define TEST mmx_test +#endif + +#include CHECK_H + +#include <mmintrin.h> + +static __m64 +__attribute__((noinline, unused)) +test (__m64 s1, __m64 s2) +{ + return _mm_mulhi_pi16 (s1, s2); +} + +static void +TEST (void) +{ + __m64_union u, s1, s2; + __m64_union e; + int i, tmp; + + s1.as_m64 = _mm_set_pi16 (10, 2067, -3033, 90); + s2.as_m64 = _mm_set_pi16 (11, 9834, 7444, -10222); + u.as_m64 = test (s1.as_m64, s2.as_m64); + + for (i = 0; i < 4; i++) + { + tmp = s1.as_short[i] * s2.as_short[i]; + + e.as_short[i] = (tmp & 0xffff0000)>>16; + } + + if (u.as_m64 != e.as_m64) + abort (); +} diff --git a/gcc/testsuite/gcc.target/powerpc/mmx-pmullw-1.c b/gcc/testsuite/gcc.target/powerpc/mmx-pmullw-1.c new file mode 100644 index 00000000000..6d041691772 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/mmx-pmullw-1.c @@ -0,0 +1,46 @@ +/* { dg-do run } */ +/* { dg-options "-O3 -mpower8-vector" } */ +/* { dg-require-effective-target lp64 } */ +/* { dg-require-effective-target p8vector_hw } */ + +#define NO_WARN_X86_INTRINSICS 1 +#ifndef CHECK_H +#define CHECK_H "mmx-check.h" +#endif + +#ifndef TEST +#define TEST mmx_test +#endif + +#include CHECK_H + +#include <mmintrin.h> + +static __m64 +__attribute__((noinline, unused)) +test (__m64 s1, __m64 s2) +{ + return _mm_mullo_pi16 (s1, s2); +} + +static void +TEST (void) +{ + __m64_union u, s1, s2; + __m64_union e; + int i, tmp; + + s1.as_m64 = _mm_set_pi16 (10, 2067, -3033, 90); + s2.as_m64 = _mm_set_pi16 (11, 9834, 7444, -10222); + u.as_m64 = test (s1.as_m64, s2.as_m64); + + for (i = 0; i < 4; i++) + { + tmp = s1.as_short[i] * s2.as_short[i]; + + e.as_short[i] = tmp; + } + + if (u.as_m64 != e.as_m64) + abort (); +} diff --git a/gcc/testsuite/gcc.target/powerpc/mmx-pslld-1.c b/gcc/testsuite/gcc.target/powerpc/mmx-pslld-1.c new file mode 100644 index 00000000000..af687cd1e96 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/mmx-pslld-1.c @@ -0,0 +1,45 @@ +/* { dg-do run } */ +/* { dg-options "-O3 -mpower8-vector" } */ +/* { dg-require-effective-target lp64 } */ +/* { dg-require-effective-target p8vector_hw } */ + +#define NO_WARN_X86_INTRINSICS 1 +#ifndef CHECK_H +#define CHECK_H "mmx-check.h" +#endif + +#ifndef TEST +#define TEST mmx_test +#endif + +#define N 0xb + +#include CHECK_H + +#include <mmintrin.h> + +static __m64 +__attribute__((noinline, unused)) +test (__m64 s1) +{ + return _mm_sll_pi32 (s1, N); +} + +static void +TEST (void) +{ + __m64_union u, s1; + __m64_union e; + int i; + + s1.as_m64 = _mm_setr_pi32 (1, -2); + u.as_m64 = test (s1.as_m64); + + + if (N < 16) + for (i = 0; i < 2; i++) + e.as_int[i] = s1.as_int[i] << N; + + if (u.as_m64 != e.as_m64) + abort (); +} diff --git a/gcc/testsuite/gcc.target/powerpc/mmx-psllw-1.c b/gcc/testsuite/gcc.target/powerpc/mmx-psllw-1.c new file mode 100644 index 00000000000..415f6a84176 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/mmx-psllw-1.c @@ -0,0 +1,45 @@ +/* { dg-do run } */ +/* { dg-options "-O3 -mpower8-vector" } */ +/* { dg-require-effective-target lp64 } */ +/* { dg-require-effective-target p8vector_hw } */ + +#define NO_WARN_X86_INTRINSICS 1 +#ifndef CHECK_H +#define CHECK_H "mmx-check.h" +#endif + +#ifndef TEST +#define TEST mmx_test +#endif + +#define N 0xb + +#include CHECK_H + +#include <mmintrin.h> + +static __m64 +__attribute__((noinline, unused)) +test (__m64 s1) +{ + return _mm_sll_pi16 (s1, N); +} + +static void +TEST (void) +{ + __m64_union u, s1; + __m64_union e; + int i; + + s1.as_m64 = _mm_setr_pi16 (1, 2, 0x7000, 0x9000); + u.as_m64 = test (s1.as_m64); + + + if (N < 16) + for (i = 0; i < 4; i++) + e.as_short[i] = s1.as_short[i] << N; + + if (u.as_m64 != e.as_m64) + abort (); +} diff --git a/gcc/testsuite/gcc.target/powerpc/mmx-psrad-1.c b/gcc/testsuite/gcc.target/powerpc/mmx-psrad-1.c new file mode 100644 index 00000000000..eaaf214292e --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/mmx-psrad-1.c @@ -0,0 +1,44 @@ +/* { dg-do run } */ +/* { dg-options "-O3 -mpower8-vector" } */ +/* { dg-require-effective-target lp64 } */ +/* { dg-require-effective-target p8vector_hw } */ + +#define NO_WARN_X86_INTRINSICS 1 +#ifndef CHECK_H +#define CHECK_H "mmx-check.h" +#endif + +#ifndef TEST +#define TEST mmx_test +#endif + +#define N 0xb + +#include CHECK_H + +#include <mmintrin.h> + +static __m64 +__attribute__((noinline, unused)) +test (__m64 s1) +{ + return _mm_sra_pi32 (s1, N); +} + +static void +TEST (void) +{ + __m64_union u, s1; + __m64_union e; + int i; + + s1.as_m64 = _mm_setr_pi32 (1000, -20000); + u.as_m64 = test (s1.as_m64); + + if (N < 16) + for (i = 0; i < 2; i++) + e.as_int[i] = s1.as_int[i] >> N; + + if (u.as_m64 != e.as_m64) + abort (); +} diff --git a/gcc/testsuite/gcc.target/powerpc/mmx-psraw-1.c b/gcc/testsuite/gcc.target/powerpc/mmx-psraw-1.c new file mode 100644 index 00000000000..eb7c3aec150 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/mmx-psraw-1.c @@ -0,0 +1,44 @@ +/* { dg-do run } */ +/* { dg-options "-O3 -mpower8-vector" } */ +/* { dg-require-effective-target lp64 } */ +/* { dg-require-effective-target p8vector_hw } */ + +#define NO_WARN_X86_INTRINSICS 1 +#ifndef CHECK_H +#define CHECK_H "mmx-check.h" +#endif + +#ifndef TEST +#define TEST mmx_test +#endif + +#define N 0xb + +#include CHECK_H + +#include <mmintrin.h> + +static __m64 +__attribute__((noinline, unused)) +test (__m64 s1) +{ + return _mm_sra_pi16 (s1, N); +} + +static void +TEST (void) +{ + __m64_union u, s1; + __m64_union e; + int i; + + s1.as_m64 = _mm_setr_pi16 (1, -2, 0x7000, 0x9000); + u.as_m64 = test (s1.as_m64); + + if (N < 16) + for (i = 0; i < 4; i++) + e.as_short[i] = s1.as_short[i] >> N; + + if (u.as_m64 != e.as_m64) + abort (); +} diff --git a/gcc/testsuite/gcc.target/powerpc/mmx-psrld-1.c b/gcc/testsuite/gcc.target/powerpc/mmx-psrld-1.c new file mode 100644 index 00000000000..1eb9d2897a7 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/mmx-psrld-1.c @@ -0,0 +1,44 @@ +/* { dg-do run } */ +/* { dg-options "-O3 -mpower8-vector" } */ +/* { dg-require-effective-target lp64 } */ +/* { dg-require-effective-target p8vector_hw } */ + +#define NO_WARN_X86_INTRINSICS 1 +#ifndef CHECK_H +#define CHECK_H "mmx-check.h" +#endif + +#ifndef TEST +#define TEST mmx_test +#endif + +#define N 0xb + +#include CHECK_H + +#include <mmintrin.h> + +static __m64 +__attribute__((noinline, unused)) +test (__m64 s1) +{ + return _mm_srl_pi32 (s1, N); +} + +static void +TEST (void) +{ + __m64_union u, s1; + __m64_union e; + int i; + + s1.as_m64 = _mm_setr_pi32 (1000, -20000); + u.as_m64 = test (s1.as_m64); + + if (N < 16) + for (i = 0; i < 2; i++) + e.as_int[i] = (unsigned int)s1.as_int[i] >> N; + + if (u.as_m64 != e.as_m64) + abort (); +} diff --git a/gcc/testsuite/gcc.target/powerpc/mmx-psrlw-1.c b/gcc/testsuite/gcc.target/powerpc/mmx-psrlw-1.c new file mode 100644 index 00000000000..d066159e8eb --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/mmx-psrlw-1.c @@ -0,0 +1,44 @@ +/* { dg-do run } */ +/* { dg-options "-O3 -mpower8-vector" } */ +/* { dg-require-effective-target lp64 } */ +/* { dg-require-effective-target p8vector_hw } */ + +#define NO_WARN_X86_INTRINSICS 1 +#ifndef CHECK_H +#define CHECK_H "mmx-check.h" +#endif + +#ifndef TEST +#define TEST mmx_test +#endif + +#define N 0xb + +#include CHECK_H + +#include <mmintrin.h> + +static __m64 +__attribute__((noinline, unused)) +test (__m64 s1) +{ + return _mm_srl_pi16 (s1, N); +} + +static void +TEST (void) +{ + __m64_union u, s1; + __m64_union e; + int i; + + s1.as_m64 = _mm_setr_pi16 (1, -2, 0x7000, 0x9000); + u.as_m64 = test (s1.as_m64); + + if (N < 16) + for (i = 0; i < 4; i++) + e.as_short[i] = (unsigned short)s1.as_short[i] >> N; + + if (u.as_m64 != e.as_m64) + abort (); +} diff --git a/gcc/testsuite/gcc.target/powerpc/mmx-psubb-2.c b/gcc/testsuite/gcc.target/powerpc/mmx-psubb-2.c new file mode 100644 index 00000000000..c64204afa41 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/mmx-psubb-2.c @@ -0,0 +1,42 @@ +/* { dg-do run } */ +/* { dg-options "-O3 -mpower8-vector" } */ +/* { dg-require-effective-target lp64 } */ +/* { dg-require-effective-target p8vector_hw } */ + +#define NO_WARN_X86_INTRINSICS 1 +#ifndef CHECK_H +#define CHECK_H "mmx-check.h" +#endif + +#ifndef TEST +#define TEST mmx_test +#endif + +#include CHECK_H + +#include <mmintrin.h> + +static __m64 +__attribute__((noinline, unused)) +test (__m64 s1, __m64 s2) +{ + return _mm_sub_pi8 (s1, s2); +} + +static void +TEST (void) +{ + __m64_union u, s1, s2; + __m64_union e; + int i; + + s1.as_m64 = _mm_set_pi8 (1, 2, 3, 4, 10, 20, 30, 90); + s2.as_m64 = _mm_set_pi8 (88, 44, 3, 22, 11, 98, 76, -100); + u.as_m64 = test (s1.as_m64, s2.as_m64); + + for (i = 0; i < 8; i++) + e.as_char[i] = s1.as_char[i] - s2.as_char[i]; + + if (u.as_m64 != e.as_m64) + abort (); +} diff --git a/gcc/testsuite/gcc.target/powerpc/mmx-psubd-2.c b/gcc/testsuite/gcc.target/powerpc/mmx-psubd-2.c new file mode 100644 index 00000000000..3260f611748 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/mmx-psubd-2.c @@ -0,0 +1,42 @@ +/* { dg-do run } */ +/* { dg-options "-O3 -mpower8-vector" } */ +/* { dg-require-effective-target lp64 } */ +/* { dg-require-effective-target p8vector_hw } */ + +#define NO_WARN_X86_INTRINSICS 1 +#ifndef CHECK_H +#define CHECK_H "mmx-check.h" +#endif + +#ifndef TEST +#define TEST mmx_test +#endif + +#include CHECK_H + +#include <mmintrin.h> + +static __m64 +__attribute__((noinline, unused)) +test (__m64 s1, __m64 s2) +{ + return _mm_sub_pi32 (s1, s2); +} + +static void +TEST (void) +{ + __m64_union u, s1, s2; + __m64_union e; + int i; + + s1.as_m64 = _mm_setr_pi32 (30, 90); + s2.as_m64 = _mm_setr_pi32 (76, -100); + u.as_m64 = test (s1.as_m64, s2.as_m64); + + for (i = 0; i < 2; i++) + e.as_int[i] = s1.as_int[i] - s2.as_int[i]; + + if (u.as_m64 != e.as_m64) + abort (); +} diff --git a/gcc/testsuite/gcc.target/powerpc/mmx-psubsb-1.c b/gcc/testsuite/gcc.target/powerpc/mmx-psubsb-1.c new file mode 100644 index 00000000000..3f0fb2af899 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/mmx-psubsb-1.c @@ -0,0 +1,51 @@ +/* { dg-do run } */ +/* { dg-options "-O3 -mpower8-vector" } */ +/* { dg-require-effective-target lp64 } */ +/* { dg-require-effective-target p8vector_hw } */ + +#define NO_WARN_X86_INTRINSICS 1 +#ifndef CHECK_H +#define CHECK_H "mmx-check.h" +#endif + +#ifndef TEST +#define TEST mmx_test +#endif + +#include CHECK_H + +#include <mmintrin.h> + +static __m64 +__attribute__((noinline, unused)) +test (__m64 s1, __m64 s2) +{ + return _mm_subs_pi8 (s1, s2); +} + +static void +TEST (void) +{ + __m64_union u, s1, s2; + __m64_union e; + int i, tmp; + + s1.as_m64 = _mm_set_pi8 (1, 2, 3, 4, 10, 20, 30, 90); + s2.as_m64 = _mm_set_pi8 (88, 44, 3, 22, 11, 98, 76, -100); + u.as_m64 = test (s1.as_m64, s2.as_m64); + + for (i = 0; i < 8; i++) + { + tmp = s1.as_signed_char[i] - s2.as_signed_char[i]; + + if (tmp > 127) + tmp = 127; + if (tmp < -128) + tmp = -128; + + e.as_signed_char[i] = tmp; + } + + if (u.as_m64 != e.as_m64) + abort (); +} diff --git a/gcc/testsuite/gcc.target/powerpc/mmx-psubsw-1.c b/gcc/testsuite/gcc.target/powerpc/mmx-psubsw-1.c new file mode 100644 index 00000000000..ae819e19c25 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/mmx-psubsw-1.c @@ -0,0 +1,51 @@ +/* { dg-do run } */ +/* { dg-options "-O3 -mpower8-vector" } */ +/* { dg-require-effective-target lp64 } */ +/* { dg-require-effective-target p8vector_hw } */ + +#define NO_WARN_X86_INTRINSICS 1 +#ifndef CHECK_H +#define CHECK_H "mmx-check.h" +#endif + +#ifndef TEST +#define TEST mmx_test +#endif + +#include CHECK_H + +#include <mmintrin.h> + +static __m64 +__attribute__((noinline, unused)) +test (__m64 s1, __m64 s2) +{ + return _mm_subs_pi16 (s1, s2); +} + +static void +TEST (void) +{ + __m64_union u, s1, s2; + __m64_union e; + int i, tmp; + + s1.as_m64 = _mm_set_pi16 (10, 20, 30, 00); + s2.as_m64 = _mm_set_pi16 (11, 98, 76, -100); + u.as_m64 = test (s1.as_m64, s2.as_m64); + + for (i = 0; i < 4; i++) + { + tmp = s1.as_short[i] - s2.as_short[i]; + + if (tmp > 32767) + tmp = 32767; + if (tmp < -32768) + tmp = -32768; + + e.as_short[i] = tmp; + } + + if (u.as_m64 != e.as_m64) + abort (); +} diff --git a/gcc/testsuite/gcc.target/powerpc/mmx-psubusb-1.c b/gcc/testsuite/gcc.target/powerpc/mmx-psubusb-1.c new file mode 100644 index 00000000000..bbdc0977109 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/mmx-psubusb-1.c @@ -0,0 +1,51 @@ +/* { dg-do run } */ +/* { dg-options "-O3 -mpower8-vector" } */ +/* { dg-require-effective-target lp64 } */ +/* { dg-require-effective-target p8vector_hw } */ + +#define NO_WARN_X86_INTRINSICS 1 +#ifndef CHECK_H +#define CHECK_H "mmx-check.h" +#endif + +#ifndef TEST +#define TEST mmx_test +#endif + +#include CHECK_H + +#include <mmintrin.h> + +static __m64 +__attribute__((noinline, unused)) +test (__m64 s1, __m64 s2) +{ + return _mm_subs_pu8 (s1, s2); +} + +static void +TEST (void) +{ + __m64_union u, s1, s2; + __m64_union e; + int i, tmp; + + s1.as_m64 = _mm_set_pi8 (30, 2, 3, 4, 10, 20, 30, 90); + s2.as_m64 = _mm_set_pi8 (88, 44, 3, 22, 11, 98, 76, 100); + u.as_m64 = test (s1.as_m64, s2.as_m64); + + for (i = 0; i < 8; i++) + { + tmp = s1.as_char[i] - s2.as_char[i]; + + if (tmp > 255) + tmp = -1; + if (tmp < 0) + tmp = 0; + + e.as_char[i] = tmp; + } + + if (u.as_m64 != e.as_m64) + abort (); +} diff --git a/gcc/testsuite/gcc.target/powerpc/mmx-psubusw-1.c b/gcc/testsuite/gcc.target/powerpc/mmx-psubusw-1.c new file mode 100644 index 00000000000..e26c380daee --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/mmx-psubusw-1.c @@ -0,0 +1,52 @@ +/* { dg-do run } */ +/* { dg-options "-O3 -mpower8-vector" } */ +/* { dg-require-effective-target lp64 } */ +/* { dg-require-effective-target p8vector_hw } */ + +#define NO_WARN_X86_INTRINSICS 1 +#ifndef CHECK_H +#define CHECK_H "mmx-check.h" +#endif + +#ifndef TEST +#define TEST mmx_test +#endif + +#include CHECK_H + +#include <mmintrin.h> + +static __m64 +__attribute__((noinline, unused)) +test (__m64 s1, __m64 s2) +{ + return _mm_subs_pu16 (s1, s2); +} + +static void +TEST (void) +{ + __m64_union u, s1, s2; + __m64_union e; + int i, tmp; + + s1.as_m64 = _mm_set_pi16 (10, 20, 30, 40); + s2.as_m64 = _mm_set_pi16 (11, 98, 76, 100); + u.as_m64 = test (s1.as_m64, s2.as_m64); + + for (i = 0; i < 4; i++) + { + tmp = (unsigned short)s1.as_short[i] - (unsigned short)s2.as_short[i]; + + if (tmp > 65535) + tmp = -1; + + if (tmp < 0) + tmp = 0; + + e.as_short[i] = tmp; + } + + if (u.as_m64 != e.as_m64) + abort (); +} diff --git a/gcc/testsuite/gcc.target/powerpc/mmx-psubw-2.c b/gcc/testsuite/gcc.target/powerpc/mmx-psubw-2.c new file mode 100644 index 00000000000..39e4cdea04a --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/mmx-psubw-2.c @@ -0,0 +1,42 @@ +/* { dg-do run } */ +/* { dg-options "-O3 -mpower8-vector" } */ +/* { dg-require-effective-target lp64 } */ +/* { dg-require-effective-target p8vector_hw } */ + +#define NO_WARN_X86_INTRINSICS 1 +#ifndef CHECK_H +#define CHECK_H "mmx-check.h" +#endif + +#ifndef TEST +#define TEST mmx_test +#endif + +#include CHECK_H + +#include <mmintrin.h> + +static __m64 +__attribute__((noinline, unused)) +test (__m64 s1, __m64 s2) +{ + return _mm_sub_pi16 (s1, s2); +} + +static void +TEST (void) +{ + __m64_union u, s1, s2; + __m64_union e; + int i; + + s1.as_m64 = _mm_set_pi16 (10, 20, 30, 90); + s2.as_m64 = _mm_set_pi16 (11, 98, 76, -100); + u.as_m64 = test (s1.as_m64, s2.as_m64); + + for (i = 0; i < 4; i++) + e.as_short[i] = s1.as_short[i] - s2.as_short[i]; + + if (u.as_m64 != e.as_m64) + abort (); +} diff --git a/gcc/testsuite/gcc.target/powerpc/mmx-punpckhbw-1.c b/gcc/testsuite/gcc.target/powerpc/mmx-punpckhbw-1.c new file mode 100644 index 00000000000..dba56ca205b --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/mmx-punpckhbw-1.c @@ -0,0 +1,44 @@ +/* { dg-do run } */ +/* { dg-options "-O3 -mpower8-vector" } */ +/* { dg-require-effective-target lp64 } */ +/* { dg-require-effective-target p8vector_hw } */ + +#define NO_WARN_X86_INTRINSICS 1 +#ifndef CHECK_H +#define CHECK_H "mmx-check.h" +#endif + +#ifndef TEST +#define TEST mmx_test +#endif + +#include CHECK_H + +#include <mmintrin.h> + +static __m64 +__attribute__((noinline, unused)) +test (__m64 s1, __m64 s2) +{ + return _mm_unpackhi_pi8 (s1, s2); +} + +static void +TEST (void) +{ + __m64_union u, s1, s2, e; + int i; + + s1.as_m64 = 0x0706050403020100UL; + s2.as_m64 = 0x1716151413121110UL; + u.as_m64 = test (s1.as_m64, s2.as_m64); + + for (i = 0; i < 4; i++) + { + e.as_char[2*i] = s1.as_char[4+i]; + e.as_char[2*i + 1] = s2.as_char[4+i]; + } + + if (u.as_m64 != e.as_m64) + abort (); +} diff --git a/gcc/testsuite/gcc.target/powerpc/mmx-punpckhdq-1.c b/gcc/testsuite/gcc.target/powerpc/mmx-punpckhdq-1.c new file mode 100644 index 00000000000..f2f53c434c5 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/mmx-punpckhdq-1.c @@ -0,0 +1,40 @@ +/* { dg-do run } */ +/* { dg-options "-O3 -mpower8-vector" } */ +/* { dg-require-effective-target lp64 } */ +/* { dg-require-effective-target p8vector_hw } */ + +#define NO_WARN_X86_INTRINSICS 1 +#ifndef CHECK_H +#define CHECK_H "mmx-check.h" +#endif + +#ifndef TEST +#define TEST mmx_test +#endif + +#include CHECK_H + +#include <mmintrin.h> + +static __m64 +__attribute__((noinline, unused)) +test (__m64 s1, __m64 s2) +{ + return _mm_unpackhi_pi32 (s1, s2); +} + +static void +TEST (void) +{ + __m64_union u, s1, s2, e; + + s1.as_m64 = 0x0706050403020100UL; + s2.as_m64 = 0x1716151413121110UL; + u.as_m64 = test (s1.as_m64, s2.as_m64); + + e.as_int[0] = s1.as_int[1]; + e.as_int[1] = s2.as_int[1]; + + if (u.as_m64 != e.as_m64) + abort (); +} diff --git a/gcc/testsuite/gcc.target/powerpc/mmx-punpckhwd-1.c b/gcc/testsuite/gcc.target/powerpc/mmx-punpckhwd-1.c new file mode 100644 index 00000000000..f0264463a81 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/mmx-punpckhwd-1.c @@ -0,0 +1,44 @@ +/* { dg-do run } */ +/* { dg-options "-O3 -mpower8-vector" } */ +/* { dg-require-effective-target lp64 } */ +/* { dg-require-effective-target p8vector_hw } */ + +#define NO_WARN_X86_INTRINSICS 1 +#ifndef CHECK_H +#define CHECK_H "mmx-check.h" +#endif + +#ifndef TEST +#define TEST mmx_test +#endif + +#include CHECK_H + +#include <mmintrin.h> + +static __m64 +__attribute__((noinline, unused)) +test (__m64 s1, __m64 s2) +{ + return _mm_unpackhi_pi16 (s1, s2); +} + +static void +TEST (void) +{ + __m64_union u, s1, s2, e; + int i; + + s1.as_m64 = 0x0706050403020100UL; + s2.as_m64 = 0x1716151413121110UL; + u.as_m64 = test (s1.as_m64, s2.as_m64); + + for (i = 0; i < 2; i++) + { + e.as_short[2*i] = s1.as_short[2+i]; + e.as_short[2*i + 1] = s2.as_short[2+i]; + } + + if (u.as_m64 != e.as_m64) + abort (); +} diff --git a/gcc/testsuite/gcc.target/powerpc/mmx-punpcklbw-1.c b/gcc/testsuite/gcc.target/powerpc/mmx-punpcklbw-1.c new file mode 100644 index 00000000000..36cf241ab19 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/mmx-punpcklbw-1.c @@ -0,0 +1,44 @@ +/* { dg-do run } */ +/* { dg-options "-O3 -mpower8-vector" } */ +/* { dg-require-effective-target lp64 } */ +/* { dg-require-effective-target p8vector_hw } */ + +#define NO_WARN_X86_INTRINSICS 1 +#ifndef CHECK_H +#define CHECK_H "mmx-check.h" +#endif + +#ifndef TEST +#define TEST mmx_test +#endif + +#include CHECK_H + +#include <mmintrin.h> + +static __m64 +__attribute__((noinline, unused)) +test (__m64 s1, __m64 s2) +{ + return _mm_unpacklo_pi8 (s1, s2); +} + +static void +TEST (void) +{ + __m64_union u, s1, s2, e; + int i; + + s1.as_m64 = 0x0706050403020100UL; + s2.as_m64 = 0x1716151413121110UL; + u.as_m64 = test (s1.as_m64, s2.as_m64); + + for (i = 0; i < 4; i++) + { + e.as_char[2*i] = s1.as_char[i]; + e.as_char[2*i + 1] = s2.as_char[i]; + } + + if (u.as_m64 != e.as_m64) + abort (); +} diff --git a/gcc/testsuite/gcc.target/powerpc/mmx-punpckldq-1.c b/gcc/testsuite/gcc.target/powerpc/mmx-punpckldq-1.c new file mode 100644 index 00000000000..8fb0251560a --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/mmx-punpckldq-1.c @@ -0,0 +1,40 @@ +/* { dg-do run } */ +/* { dg-options "-O3 -mpower8-vector" } */ +/* { dg-require-effective-target lp64 } */ +/* { dg-require-effective-target p8vector_hw } */ + +#define NO_WARN_X86_INTRINSICS 1 +#ifndef CHECK_H +#define CHECK_H "mmx-check.h" +#endif + +#ifndef TEST +#define TEST mmx_test +#endif + +#include CHECK_H + +#include <mmintrin.h> + +static __m64 +__attribute__((noinline, unused)) +test (__m64 s1, __m64 s2) +{ + return _mm_unpacklo_pi32 (s1, s2); +} + +static void +TEST (void) +{ + __m64_union u, s1, s2, e; + + s1.as_m64 = 0x0706050403020100UL; + s2.as_m64 = 0x1716151413121110UL; + u.as_m64 = test (s1.as_m64, s2.as_m64); + + e.as_int[0] = s1.as_int[0]; + e.as_int[1] = s2.as_int[0]; + + if (u.as_m64 != e.as_m64) + abort (); +} diff --git a/gcc/testsuite/gcc.target/powerpc/mmx-punpcklwd-1.c b/gcc/testsuite/gcc.target/powerpc/mmx-punpcklwd-1.c new file mode 100644 index 00000000000..37b6b6ff8c6 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/mmx-punpcklwd-1.c @@ -0,0 +1,44 @@ +/* { dg-do run } */ +/* { dg-options "-O3 -mpower8-vector" } */ +/* { dg-require-effective-target lp64 } */ +/* { dg-require-effective-target p8vector_hw } */ + +#define NO_WARN_X86_INTRINSICS 1 +#ifndef CHECK_H +#define CHECK_H "mmx-check.h" +#endif + +#ifndef TEST +#define TEST mmx_test +#endif + +#include CHECK_H + +#include <mmintrin.h> + +static __m64 +__attribute__((noinline, unused)) +test (__m64 s1, __m64 s2) +{ + return _mm_unpacklo_pi16 (s1, s2); +} + +static void +TEST (void) +{ + __m64_union u, s1, s2, e; + int i; + + s1.as_m64 = 0x0706050403020100UL; + s2.as_m64 = 0x1716151413121110UL; + u.as_m64 = test (s1.as_m64, s2.as_m64); + + for (i = 0; i < 2; i++) + { + e.as_short[2*i] = s1.as_short[i]; + e.as_short[2*i + 1] = s2.as_short[i]; + } + + if (u.as_m64 != e.as_m64) + abort (); +} diff --git a/gcc/testsuite/gcc.target/powerpc/p8vector-builtin-8.c b/gcc/testsuite/gcc.target/powerpc/p8vector-builtin-8.c index 33347740d0c..4b0370bb863 100644 --- a/gcc/testsuite/gcc.target/powerpc/p8vector-builtin-8.c +++ b/gcc/testsuite/gcc.target/powerpc/p8vector-builtin-8.c @@ -11,7 +11,8 @@ vector unsigned char vuca, vucb, vucc; vector bool char vbca, vbcb; vector unsigned short vusa, vusb; vector bool short vbsa, vbsb; -vector unsigned int vuia, vuib; +vector signed int vsia, vsib, vsic; +vector unsigned int vuia, vuib, vuic; vector bool int vbia, vbib; vector signed long long vsla, vslb; vector unsigned long long vula, vulb, vulc; @@ -24,6 +25,7 @@ void foo (vector unsigned char *vucr, vector bool char *vbcr, vector unsigned short *vusr, vector bool short *vbsr, + vector signed int *vsir, vector unsigned int *vuir, vector bool int *vbir, vector unsigned long long *vulr, @@ -32,10 +34,16 @@ void foo (vector unsigned char *vucr, vector unsigned __int128 *vuxr, vector double *vdr) { + *vsir++ = vec_addc (vsia, vsib); + *vuir++ = vec_addc (vuia, vuib); *vsxr++ = vec_addc (vsxa, vsxb); *vuxr++ = vec_addc (vuxa, vuxb); + *vsir++ = vec_adde (vsia, vsib, vsic); + *vuir++ = vec_adde (vuia, vuib, vuic); *vsxr++ = vec_adde (vsxa, vsxb, vsxc); *vuxr++ = vec_adde (vuxa, vuxb, vuxc); + *vsir++ = vec_addec (vsia, vsib, vsic); + *vuir++ = vec_addec (vuia, vuib, vuic); *vsxr++ = vec_addec (vsxa, vsxb, vsxc); *vuxr++ = vec_addec (vuxa, vuxb, vuxc); *vucr++ = vec_bperm (vuca, vucb); @@ -60,11 +68,30 @@ void foo (vector unsigned char *vucr, *vuxr++ = vec_pmsum_be (vula, vulb); *vuir++ = vec_shasigma_be (vuia, 0, 1); *vulr++ = vec_shasigma_be (vula, 0, 1); + *vsir++ = vec_subc (vsia, vsib); + *vuir++ = vec_subc (vuia, vuib); + *vsxr++ = vec_subc (vsxa, vsxb); + *vuxr++ = vec_subc (vuxa, vuxb); + *vsir++ = vec_sube (vsia, vsib, vsic); + *vuir++ = vec_sube (vuia, vuib, vuic); + *vsxr++ = vec_sube (vsxa, vsxb, vsxc); + *vuxr++ = vec_sube (vuxa, vuxb, vuxc); + *vsir++ = vec_subec (vsia, vsib, vsic); + *vuir++ = vec_subec (vuia, vuib, vuic); + *vsxr++ = vec_subec (vsxa, vsxb, vsxc); + *vuxr++ = vec_subec (vuxa, vuxb, vuxc); } /* { dg-final { scan-assembler-times "vaddcuq" 2 } } */ /* { dg-final { scan-assembler-times "vaddeuqm" 2 } } */ /* { dg-final { scan-assembler-times "vaddecuq" 2 } } */ +/* { dg-final { scan-assembler-times "vaddcuw" 6 } } */ +/* { dg-final { scan-assembler-times "vadduwm" 4 } } */ +/* { dg-final { scan-assembler-times "vsubcuq" 2 } } */ +/* { dg-final { scan-assembler-times "vsubeuqm" 2 } } */ +/* { dg-final { scan-assembler-times "vsubecuq" 2 } } */ +/* { dg-final { scan-assembler-times "vsubcuw" 4 } } */ +/* { dg-final { scan-assembler-times "vsubuwm" 4 } } */ /* { dg-final { scan-assembler-times "vbpermq" 2 } } */ /* { dg-final { scan-assembler-times "xxleqv" 4 } } */ /* { dg-final { scan-assembler-times "vgbbd" 1 } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/p8vector-fp.c b/gcc/testsuite/gcc.target/powerpc/p8vector-fp.c index 17b73bbc7b3..7b30e4c4e23 100644 --- a/gcc/testsuite/gcc.target/powerpc/p8vector-fp.c +++ b/gcc/testsuite/gcc.target/powerpc/p8vector-fp.c @@ -2,7 +2,7 @@ /* { dg-skip-if "" { powerpc*-*-darwin* } } */ /* { dg-require-effective-target powerpc_p8vector_ok } */ /* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power8" } } */ -/* { dg-options "-mcpu=power8 -O2 -mupper-regs-df -mupper-regs-sf -fno-math-errno" } */ +/* { dg-options "-mcpu=power8 -O2 -fno-math-errno" } */ float abs_sf (float *p) { diff --git a/gcc/testsuite/gcc.target/powerpc/p8vector-int128-1.c b/gcc/testsuite/gcc.target/powerpc/p8vector-int128-1.c index 23663b96da6..992ed225d5f 100644 --- a/gcc/testsuite/gcc.target/powerpc/p8vector-int128-1.c +++ b/gcc/testsuite/gcc.target/powerpc/p8vector-int128-1.c @@ -2,7 +2,7 @@ /* { dg-skip-if "" { powerpc*-*-darwin* } } */ /* { dg-require-effective-target powerpc_p8vector_ok } */ /* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power8" } } */ -/* { dg-options "-mcpu=power8 -O3 -mvsx-timode -mlra" } */ +/* { dg-options "-mcpu=power8 -O3 -mvsx-timode" } */ #include <altivec.h> diff --git a/gcc/testsuite/gcc.target/powerpc/p8vector-ldst.c b/gcc/testsuite/gcc.target/powerpc/p8vector-ldst.c index 58e1f4485be..e683d614d62 100644 --- a/gcc/testsuite/gcc.target/powerpc/p8vector-ldst.c +++ b/gcc/testsuite/gcc.target/powerpc/p8vector-ldst.c @@ -2,7 +2,7 @@ /* { dg-skip-if "" { powerpc*-*-darwin* } } */ /* { dg-require-effective-target powerpc_p8vector_ok } */ /* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power8" } } */ -/* { dg-options "-mcpu=power8 -O2 -mupper-regs-df -mupper-regs-sf" } */ +/* { dg-options "-mcpu=power8 -O2" } */ float load_store_sf (unsigned long num, diff --git a/gcc/testsuite/gcc.target/powerpc/p9-dimode1.c b/gcc/testsuite/gcc.target/powerpc/p9-dimode1.c index c29b69d3e9e..64f0e31fb00 100644 --- a/gcc/testsuite/gcc.target/powerpc/p9-dimode1.c +++ b/gcc/testsuite/gcc.target/powerpc/p9-dimode1.c @@ -1,7 +1,7 @@ /* { dg-do compile { target { powerpc64*-*-* && lp64 } } } */ /* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ /* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-mcpu=power9 -O2 -mupper-regs-di" } */ +/* { dg-options "-mcpu=power9 -O2" } */ /* Verify P9 changes to allow DImode into Altivec registers, and generate constants using XXSPLTIB. */ @@ -43,8 +43,8 @@ p9_minus_1 (void) return ret; } -/* { dg-final { scan-assembler "\[ \t\]xxspltib" } } */ -/* { dg-final { scan-assembler-not "\[ \t\]mtvsrd" } } */ -/* { dg-final { scan-assembler-not "\[ \t\]lfd" } } */ -/* { dg-final { scan-assembler-not "\[ \t\]ld" } } */ -/* { dg-final { scan-assembler-not "\[ \t\]lxsd" } } */ +/* { dg-final { scan-assembler {\mxxspltib\M} } } */ +/* { dg-final { scan-assembler-not {\mmtvsrd\M} } } */ +/* { dg-final { scan-assembler-not {\mlfd\M} } } */ +/* { dg-final { scan-assembler-not {\mld\M} } } */ +/* { dg-final { scan-assembler-not {\mlxsd\M} } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/p9-dimode2.c b/gcc/testsuite/gcc.target/powerpc/p9-dimode2.c index f33d18c6078..9e27936d748 100644 --- a/gcc/testsuite/gcc.target/powerpc/p9-dimode2.c +++ b/gcc/testsuite/gcc.target/powerpc/p9-dimode2.c @@ -1,7 +1,7 @@ /* { dg-do compile { target { powerpc64*-*-* && lp64 } } } */ /* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ /* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-mcpu=power9 -O2 -mupper-regs-di" } */ +/* { dg-options "-mcpu=power9 -O2" } */ /* Verify that large integer constants are loaded via direct move instead of being loaded from memory. */ @@ -21,7 +21,7 @@ p9_large (void) return ret; } -/* { dg-final { scan-assembler "\[ \t\]mtvsrd" } } */ -/* { dg-final { scan-assembler-not "\[ \t\]ld" } } */ -/* { dg-final { scan-assembler-not "\[ \t\]lfd" } } */ -/* { dg-final { scan-assembler-not "\[ \t\]lxsd" } } */ +/* { dg-final { scan-assembler {\mmtvsrd\M} } } */ +/* { dg-final { scan-assembler-not {\mld\M} } } */ +/* { dg-final { scan-assembler-not {\mlfd\M} } } */ +/* { dg-final { scan-assembler-not {\mlxsd\M} } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/p9-vparity.c b/gcc/testsuite/gcc.target/powerpc/p9-vparity.c index af5b5905a6f..6e49606fe0b 100644 --- a/gcc/testsuite/gcc.target/powerpc/p9-vparity.c +++ b/gcc/testsuite/gcc.target/powerpc/p9-vparity.c @@ -2,7 +2,7 @@ /* { dg-skip-if "" { powerpc*-*-darwin* } } */ /* { dg-require-effective-target powerpc_p9vector_ok } */ /* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ -/* { dg-options "-mcpu=power9 -O2 -mlra -mvsx-timode" } */ +/* { dg-options "-mcpu=power9 -O2 -mvsx-timode" } */ #include <altivec.h> diff --git a/gcc/testsuite/gcc.target/powerpc/p9-xxbr-1.c b/gcc/testsuite/gcc.target/powerpc/p9-xxbr-1.c index cd4ba7384de..164f11f6ea3 100644 --- a/gcc/testsuite/gcc.target/powerpc/p9-xxbr-1.c +++ b/gcc/testsuite/gcc.target/powerpc/p9-xxbr-1.c @@ -13,6 +13,12 @@ rev_char (vector char a) return vec_revb (a); /* XXBRQ. */ } +vector bool char +rev_bool_char (vector bool char a) +{ + return vec_revb (a); /* XXBRQ. */ +} + vector signed char rev_schar (vector signed char a) { @@ -31,6 +37,12 @@ rev_short (vector short a) return vec_revb (a); /* XXBRH. */ } +vector bool short +rev_bool_short (vector bool short a) +{ + return vec_revb (a); /* XXBRH. */ +} + vector unsigned short rev_ushort (vector unsigned short a) { @@ -43,6 +55,12 @@ rev_int (vector int a) return vec_revb (a); /* XXBRW. */ } +vector bool int +rev_bool_int (vector bool int a) +{ + return vec_revb (a); /* XXBRW. */ +} + vector unsigned int rev_uint (vector unsigned int a) { @@ -62,6 +80,6 @@ rev_double (vector double a) } /* { dg-final { scan-assembler-times "xxbrd" 1 } } */ -/* { dg-final { scan-assembler-times "xxbrh" 2 } } */ -/* { dg-final { scan-assembler-times "xxbrq" 3 } } */ -/* { dg-final { scan-assembler-times "xxbrw" 3 } } */ +/* { dg-final { scan-assembler-times "xxbrh" 3 } } */ +/* { dg-final { scan-assembler-times "xxbrq" 4 } } */ +/* { dg-final { scan-assembler-times "xxbrw" 4 } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/p9-xxbr-2.c b/gcc/testsuite/gcc.target/powerpc/p9-xxbr-2.c index 97f6186bf91..a4a19390d7b 100644 --- a/gcc/testsuite/gcc.target/powerpc/p9-xxbr-2.c +++ b/gcc/testsuite/gcc.target/powerpc/p9-xxbr-2.c @@ -20,6 +20,18 @@ rev_ulong (vector unsigned long a) return vec_revb (a); /* XXBRD. */ } +vector long long +rev_long_long (vector long long a) +{ + return vec_revb (a); /* XXBRD. */ +} + +vector unsigned long long +rev_ulong_ulong (vector unsigned long long a) +{ + return vec_revb (a); /* XXBRD. */ +} + vector __int128_t rev_int128 (vector __int128_t a) { @@ -32,5 +44,5 @@ rev_uint128 (vector __uint128_t a) return vec_revb (a); /* XXBRQ. */ } -/* { dg-final { scan-assembler-times "xxbrd" 2 } } */ +/* { dg-final { scan-assembler-times "xxbrd" 4 } } */ /* { dg-final { scan-assembler-times "xxbrq" 2 } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/ppc-fpconv-1.c b/gcc/testsuite/gcc.target/powerpc/ppc-fpconv-1.c index 2efa952a239..de508b784c9 100644 --- a/gcc/testsuite/gcc.target/powerpc/ppc-fpconv-1.c +++ b/gcc/testsuite/gcc.target/powerpc/ppc-fpconv-1.c @@ -2,15 +2,13 @@ /* { dg-skip-if "" { powerpc*-*-darwin* } } */ /* { dg-require-effective-target powerpc_vsx_ok } */ /* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power7" } } */ -/* { dg-options "-O2 -mcpu=power7 -ffast-math -mno-upper-regs-df" } */ -/* { dg-final { scan-assembler-times "lfiwax" 2 } } */ -/* { dg-final { scan-assembler-times "lfiwzx" 2 } } */ -/* { dg-final { scan-assembler-times "fcfids " 3 } } */ -/* { dg-final { scan-assembler-times "fcfidus " 1 } } */ -/* { dg-final { scan-assembler-times "fcfid " 3 } } */ -/* { dg-final { scan-assembler-times "fcfidu " 1 } } */ -/* { dg-final { scan-assembler-not "xscvdpsxds" } } */ -/* { dg-final { scan-assembler-not "xscvdpuxds" } } */ +/* { dg-options "-O2 -mcpu=power7 -ffast-math" } */ +/* { dg-final { scan-assembler-times {\mlfiwax\M|\mlxsiwax\M} 2 } } */ +/* { dg-final { scan-assembler-times {\mlfiwzx\M|\mlxsiwzx\M} 2 } } */ +/* { dg-final { scan-assembler-times {\mfcfids\M|\mxscvsxdsp\M} 3 } } */ +/* { dg-final { scan-assembler-times {\mfcfidus\M|\mxscvuxdsp\M} 1 } } */ +/* { dg-final { scan-assembler-times {\mfcfid\M|\mxscvsxddp\M} 3 } } */ +/* { dg-final { scan-assembler-times {\mfcfidu\M|\mxscvuxddp\M} 1 } } */ void int_to_float (float *dest, int *src) { diff --git a/gcc/testsuite/gcc.target/powerpc/ppc-fpconv-10.c b/gcc/testsuite/gcc.target/powerpc/ppc-fpconv-10.c index 9e192d13398..cb6dea41b06 100644 --- a/gcc/testsuite/gcc.target/powerpc/ppc-fpconv-10.c +++ b/gcc/testsuite/gcc.target/powerpc/ppc-fpconv-10.c @@ -2,8 +2,8 @@ /* { dg-skip-if "" { powerpc*-*-darwin* } } */ /* { dg-require-effective-target powerpc_vsx_ok } */ /* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power7" } } */ -/* { dg-options "-O2 -mcpu=power7 -ffast-math -mno-upper-regs-df" } */ -/* { dg-final { scan-assembler "friz" } } */ +/* { dg-options "-O2 -mcpu=power7 -ffast-math" } */ +/* { dg-final { scan-assembler {\mfriz\M|\mxsrdpiz\M} } } */ double round_double_llong (double a) { diff --git a/gcc/testsuite/gcc.target/powerpc/ppc-fpconv-5.c b/gcc/testsuite/gcc.target/powerpc/ppc-fpconv-5.c index b59cac3a5bb..6bffa164fcd 100644 --- a/gcc/testsuite/gcc.target/powerpc/ppc-fpconv-5.c +++ b/gcc/testsuite/gcc.target/powerpc/ppc-fpconv-5.c @@ -2,13 +2,11 @@ /* { dg-skip-if "" { powerpc*-*-darwin* } } */ /* { dg-require-effective-target powerpc_vsx_ok } */ /* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power7" } } */ -/* { dg-options "-O3 -mcpu=power7 -ffast-math -mno-upper-regs-df" } */ -/* { dg-final { scan-assembler-times "fctiwz " 2 } } */ -/* { dg-final { scan-assembler-times "fctiwuz " 2 } } */ -/* { dg-final { scan-assembler-times "fctidz " 2 } } */ -/* { dg-final { scan-assembler-times "fctiduz " 2 } } */ -/* { dg-final { scan-assembler-not "xscvdpsxds" } } */ -/* { dg-final { scan-assembler-not "xscvdpuxds" } } */ +/* { dg-options "-O3 -mcpu=power7 -ffast-math" } */ +/* { dg-final { scan-assembler-times {\mfctiwz\M|\mxscvdpsxws\M} 2 } } */ +/* { dg-final { scan-assembler-times {\mfctiwuz\M|\mxscvdpuxws\M} 2 } } */ +/* { dg-final { scan-assembler-times {\mfctidz\M|\mxscvdpsxds\M} 2 } } */ +/* { dg-final { scan-assembler-times {\mfctiduz\M|\mxscvdpuxds\M} 2 } } */ void float_to_int (int *dest, float src) { *dest = (int) src; } void double_to_int (int *dest, double src) { *dest = (int) src; } diff --git a/gcc/testsuite/gcc.target/powerpc/ppc-fpconv-9.c b/gcc/testsuite/gcc.target/powerpc/ppc-fpconv-9.c index 372b2334686..d376936a750 100644 --- a/gcc/testsuite/gcc.target/powerpc/ppc-fpconv-9.c +++ b/gcc/testsuite/gcc.target/powerpc/ppc-fpconv-9.c @@ -2,12 +2,12 @@ /* { dg-skip-if "" { powerpc*-*-darwin* } } */ /* { dg-require-effective-target powerpc_vsx_ok } */ /* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power7" } } */ -/* { dg-options "-O3 -mcpu=power7 -ffast-math -mno-upper-regs-df" } */ -/* { dg-final { scan-assembler-times "fctidz" 2 } } */ -/* { dg-final { scan-assembler-not "lwz" } } */ -/* { dg-final { scan-assembler-not "stw" } } */ -/* { dg-final { scan-assembler-not "ld " } } */ -/* { dg-final { scan-assembler-not "std" } } */ +/* { dg-options "-O3 -mcpu=power7 -ffast-math" } */ +/* { dg-final { scan-assembler-times {\mfctidz\M|\mxscvdpsxds\M} 2 } } */ +/* { dg-final { scan-assembler-not {\mlwz\M} } } */ +/* { dg-final { scan-assembler-not {\mstw\M} } } */ +/* { dg-final { scan-assembler-not {\mld\M} } } */ +/* { dg-final { scan-assembler-not {\mstd\M} } } */ void float_to_llong (long long *dest, float src) { *dest = (long long) src; } void double_to_llong (long long *dest, double src) { *dest = (long long) src; } diff --git a/gcc/testsuite/gcc.target/powerpc/ppc-round.c b/gcc/testsuite/gcc.target/powerpc/ppc-round.c index 0cfa0da2a72..50ab078f55a 100644 --- a/gcc/testsuite/gcc.target/powerpc/ppc-round.c +++ b/gcc/testsuite/gcc.target/powerpc/ppc-round.c @@ -2,15 +2,15 @@ /* { dg-skip-if "" { powerpc*-*-darwin* } } */ /* { dg-require-effective-target powerpc_vsx_ok } */ /* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power7" } } */ -/* { dg-options "-O2 -mcpu=power7 -mno-upper-regs-df" } */ -/* { dg-final { scan-assembler-times "stfiwx" 4 } } */ -/* { dg-final { scan-assembler-times "lfiwax" 2 } } */ -/* { dg-final { scan-assembler-times "lfiwzx" 2 } } */ -/* { dg-final { scan-assembler-times "fctiwz " 2 } } */ -/* { dg-final { scan-assembler-times "fctiwuz " 2 } } */ -/* { dg-final { scan-assembler-times "fcfids " 2 } } */ -/* { dg-final { scan-assembler-not "lwz" } } */ -/* { dg-final { scan-assembler-not "stw" } } */ +/* { dg-options "-O2 -mcpu=power7" } */ +/* { dg-final { scan-assembler-times {\mstfiwx\M|\mstxsiwx\M} 4 } } */ +/* { dg-final { scan-assembler-times {\mlfiwax\M|\mlxsiwax\M} 2 } } */ +/* { dg-final { scan-assembler-times {\mlfiwzx\M|\mlxsiwzx\M} 2 } } */ +/* { dg-final { scan-assembler-times {\mfctiwz\M|\mxscvdpsxws\M} 2 } } */ +/* { dg-final { scan-assembler-times {\mfctiwuz\M|\mxscvdpuxws\M} 2 } } */ +/* { dg-final { scan-assembler-times {\mfcfids\M|\mxscvsxdsp\M} 2 } } */ +/* { dg-final { scan-assembler-not {\mlwz\M} } } */ +/* { dg-final { scan-assembler-not {\mstw\M} } } */ /* Make sure we don't have loads/stores to the GPR unit. */ double diff --git a/gcc/testsuite/gcc.target/powerpc/pr63491.c b/gcc/testsuite/gcc.target/powerpc/pr63491.c index a1518912308..be6a40eb32d 100644 --- a/gcc/testsuite/gcc.target/powerpc/pr63491.c +++ b/gcc/testsuite/gcc.target/powerpc/pr63491.c @@ -1,5 +1,5 @@ /* { dg-do compile { target { powerpc*-*-* && lp64 } } } */ -/* { dg-options "-O1 -mcpu=power8 -mlra" } */ +/* { dg-options "-O1 -mcpu=power8" } */ typedef __int128_t __attribute__((__vector_size__(16))) vector_128_t; typedef unsigned long long scalar_64_t; diff --git a/gcc/testsuite/gcc.target/powerpc/pr65849-1.c b/gcc/testsuite/gcc.target/powerpc/pr65849-1.c deleted file mode 100644 index 288fdeed2ca..00000000000 --- a/gcc/testsuite/gcc.target/powerpc/pr65849-1.c +++ /dev/null @@ -1,728 +0,0 @@ -/* { dg-do compile { target { powerpc*-*-* } } } */ -/* { dg-require-effective-target powerpc_vsx_ok } */ -/* { dg-skip-if "" { powerpc*-*-darwin* } } */ -/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power7" } } */ -/* { dg-options "-mcpu=power7 -O2 -mno-upper-regs-df" } */ - -/* Test whether we can enable the -mupper-regs-df with target pragmas. Make - sure double values are allocated to the Altivec registers as well as the - traditional FPR registers. */ - -#ifndef TYPE -#define TYPE double -#endif - -#ifndef MASK_TYPE -#define MASK_TYPE unsigned long long -#endif - -#define MASK_ONE ((MASK_TYPE)1) -#define ZERO ((TYPE) 0.0) - -#pragma GCC target ("upper-regs-df") -TYPE -test_add (const MASK_TYPE *add_mask, const TYPE *add_values, - const MASK_TYPE *sub_mask, const TYPE *sub_values, - const MASK_TYPE *mul_mask, const TYPE *mul_values, - const MASK_TYPE *div_mask, const TYPE *div_values, - const MASK_TYPE *eq0_mask, int *eq0_ptr) -{ - TYPE value; - TYPE value00 = ZERO; - TYPE value01 = ZERO; - TYPE value02 = ZERO; - TYPE value03 = ZERO; - TYPE value04 = ZERO; - TYPE value05 = ZERO; - TYPE value06 = ZERO; - TYPE value07 = ZERO; - TYPE value08 = ZERO; - TYPE value09 = ZERO; - TYPE value10 = ZERO; - TYPE value11 = ZERO; - TYPE value12 = ZERO; - TYPE value13 = ZERO; - TYPE value14 = ZERO; - TYPE value15 = ZERO; - TYPE value16 = ZERO; - TYPE value17 = ZERO; - TYPE value18 = ZERO; - TYPE value19 = ZERO; - TYPE value20 = ZERO; - TYPE value21 = ZERO; - TYPE value22 = ZERO; - TYPE value23 = ZERO; - TYPE value24 = ZERO; - TYPE value25 = ZERO; - TYPE value26 = ZERO; - TYPE value27 = ZERO; - TYPE value28 = ZERO; - TYPE value29 = ZERO; - TYPE value30 = ZERO; - TYPE value31 = ZERO; - TYPE value32 = ZERO; - TYPE value33 = ZERO; - TYPE value34 = ZERO; - TYPE value35 = ZERO; - TYPE value36 = ZERO; - TYPE value37 = ZERO; - TYPE value38 = ZERO; - TYPE value39 = ZERO; - MASK_TYPE mask; - int eq0; - - while ((mask = *add_mask++) != 0) - { - value = *add_values++; - - __asm__ (" #reg %0" : "+d" (value)); - - if ((mask & (MASK_ONE << 0)) != 0) - value00 += value; - - if ((mask & (MASK_ONE << 1)) != 0) - value01 += value; - - if ((mask & (MASK_ONE << 2)) != 0) - value02 += value; - - if ((mask & (MASK_ONE << 3)) != 0) - value03 += value; - - if ((mask & (MASK_ONE << 4)) != 0) - value04 += value; - - if ((mask & (MASK_ONE << 5)) != 0) - value05 += value; - - if ((mask & (MASK_ONE << 6)) != 0) - value06 += value; - - if ((mask & (MASK_ONE << 7)) != 0) - value07 += value; - - if ((mask & (MASK_ONE << 8)) != 0) - value08 += value; - - if ((mask & (MASK_ONE << 9)) != 0) - value09 += value; - - if ((mask & (MASK_ONE << 10)) != 0) - value10 += value; - - if ((mask & (MASK_ONE << 11)) != 0) - value11 += value; - - if ((mask & (MASK_ONE << 12)) != 0) - value12 += value; - - if ((mask & (MASK_ONE << 13)) != 0) - value13 += value; - - if ((mask & (MASK_ONE << 14)) != 0) - value14 += value; - - if ((mask & (MASK_ONE << 15)) != 0) - value15 += value; - - if ((mask & (MASK_ONE << 16)) != 0) - value16 += value; - - if ((mask & (MASK_ONE << 17)) != 0) - value17 += value; - - if ((mask & (MASK_ONE << 18)) != 0) - value18 += value; - - if ((mask & (MASK_ONE << 19)) != 0) - value19 += value; - - if ((mask & (MASK_ONE << 20)) != 0) - value20 += value; - - if ((mask & (MASK_ONE << 21)) != 0) - value21 += value; - - if ((mask & (MASK_ONE << 22)) != 0) - value22 += value; - - if ((mask & (MASK_ONE << 23)) != 0) - value23 += value; - - if ((mask & (MASK_ONE << 24)) != 0) - value24 += value; - - if ((mask & (MASK_ONE << 25)) != 0) - value25 += value; - - if ((mask & (MASK_ONE << 26)) != 0) - value26 += value; - - if ((mask & (MASK_ONE << 27)) != 0) - value27 += value; - - if ((mask & (MASK_ONE << 28)) != 0) - value28 += value; - - if ((mask & (MASK_ONE << 29)) != 0) - value29 += value; - - if ((mask & (MASK_ONE << 30)) != 0) - value30 += value; - - if ((mask & (MASK_ONE << 31)) != 0) - value31 += value; - - if ((mask & (MASK_ONE << 32)) != 0) - value32 += value; - - if ((mask & (MASK_ONE << 33)) != 0) - value33 += value; - - if ((mask & (MASK_ONE << 34)) != 0) - value34 += value; - - if ((mask & (MASK_ONE << 35)) != 0) - value35 += value; - - if ((mask & (MASK_ONE << 36)) != 0) - value36 += value; - - if ((mask & (MASK_ONE << 37)) != 0) - value37 += value; - - if ((mask & (MASK_ONE << 38)) != 0) - value38 += value; - - if ((mask & (MASK_ONE << 39)) != 0) - value39 += value; - } - - while ((mask = *sub_mask++) != 0) - { - value = *sub_values++; - - __asm__ (" #reg %0" : "+d" (value)); - - if ((mask & (MASK_ONE << 0)) != 0) - value00 -= value; - - if ((mask & (MASK_ONE << 1)) != 0) - value01 -= value; - - if ((mask & (MASK_ONE << 2)) != 0) - value02 -= value; - - if ((mask & (MASK_ONE << 3)) != 0) - value03 -= value; - - if ((mask & (MASK_ONE << 4)) != 0) - value04 -= value; - - if ((mask & (MASK_ONE << 5)) != 0) - value05 -= value; - - if ((mask & (MASK_ONE << 6)) != 0) - value06 -= value; - - if ((mask & (MASK_ONE << 7)) != 0) - value07 -= value; - - if ((mask & (MASK_ONE << 8)) != 0) - value08 -= value; - - if ((mask & (MASK_ONE << 9)) != 0) - value09 -= value; - - if ((mask & (MASK_ONE << 10)) != 0) - value10 -= value; - - if ((mask & (MASK_ONE << 11)) != 0) - value11 -= value; - - if ((mask & (MASK_ONE << 12)) != 0) - value12 -= value; - - if ((mask & (MASK_ONE << 13)) != 0) - value13 -= value; - - if ((mask & (MASK_ONE << 14)) != 0) - value14 -= value; - - if ((mask & (MASK_ONE << 15)) != 0) - value15 -= value; - - if ((mask & (MASK_ONE << 16)) != 0) - value16 -= value; - - if ((mask & (MASK_ONE << 17)) != 0) - value17 -= value; - - if ((mask & (MASK_ONE << 18)) != 0) - value18 -= value; - - if ((mask & (MASK_ONE << 19)) != 0) - value19 -= value; - - if ((mask & (MASK_ONE << 20)) != 0) - value20 -= value; - - if ((mask & (MASK_ONE << 21)) != 0) - value21 -= value; - - if ((mask & (MASK_ONE << 22)) != 0) - value22 -= value; - - if ((mask & (MASK_ONE << 23)) != 0) - value23 -= value; - - if ((mask & (MASK_ONE << 24)) != 0) - value24 -= value; - - if ((mask & (MASK_ONE << 25)) != 0) - value25 -= value; - - if ((mask & (MASK_ONE << 26)) != 0) - value26 -= value; - - if ((mask & (MASK_ONE << 27)) != 0) - value27 -= value; - - if ((mask & (MASK_ONE << 28)) != 0) - value28 -= value; - - if ((mask & (MASK_ONE << 29)) != 0) - value29 -= value; - - if ((mask & (MASK_ONE << 30)) != 0) - value30 -= value; - - if ((mask & (MASK_ONE << 31)) != 0) - value31 -= value; - - if ((mask & (MASK_ONE << 32)) != 0) - value32 -= value; - - if ((mask & (MASK_ONE << 33)) != 0) - value33 -= value; - - if ((mask & (MASK_ONE << 34)) != 0) - value34 -= value; - - if ((mask & (MASK_ONE << 35)) != 0) - value35 -= value; - - if ((mask & (MASK_ONE << 36)) != 0) - value36 -= value; - - if ((mask & (MASK_ONE << 37)) != 0) - value37 -= value; - - if ((mask & (MASK_ONE << 38)) != 0) - value38 -= value; - - if ((mask & (MASK_ONE << 39)) != 0) - value39 -= value; - } - - while ((mask = *mul_mask++) != 0) - { - value = *mul_values++; - - __asm__ (" #reg %0" : "+d" (value)); - - if ((mask & (MASK_ONE << 0)) != 0) - value00 *= value; - - if ((mask & (MASK_ONE << 1)) != 0) - value01 *= value; - - if ((mask & (MASK_ONE << 2)) != 0) - value02 *= value; - - if ((mask & (MASK_ONE << 3)) != 0) - value03 *= value; - - if ((mask & (MASK_ONE << 4)) != 0) - value04 *= value; - - if ((mask & (MASK_ONE << 5)) != 0) - value05 *= value; - - if ((mask & (MASK_ONE << 6)) != 0) - value06 *= value; - - if ((mask & (MASK_ONE << 7)) != 0) - value07 *= value; - - if ((mask & (MASK_ONE << 8)) != 0) - value08 *= value; - - if ((mask & (MASK_ONE << 9)) != 0) - value09 *= value; - - if ((mask & (MASK_ONE << 10)) != 0) - value10 *= value; - - if ((mask & (MASK_ONE << 11)) != 0) - value11 *= value; - - if ((mask & (MASK_ONE << 12)) != 0) - value12 *= value; - - if ((mask & (MASK_ONE << 13)) != 0) - value13 *= value; - - if ((mask & (MASK_ONE << 14)) != 0) - value14 *= value; - - if ((mask & (MASK_ONE << 15)) != 0) - value15 *= value; - - if ((mask & (MASK_ONE << 16)) != 0) - value16 *= value; - - if ((mask & (MASK_ONE << 17)) != 0) - value17 *= value; - - if ((mask & (MASK_ONE << 18)) != 0) - value18 *= value; - - if ((mask & (MASK_ONE << 19)) != 0) - value19 *= value; - - if ((mask & (MASK_ONE << 20)) != 0) - value20 *= value; - - if ((mask & (MASK_ONE << 21)) != 0) - value21 *= value; - - if ((mask & (MASK_ONE << 22)) != 0) - value22 *= value; - - if ((mask & (MASK_ONE << 23)) != 0) - value23 *= value; - - if ((mask & (MASK_ONE << 24)) != 0) - value24 *= value; - - if ((mask & (MASK_ONE << 25)) != 0) - value25 *= value; - - if ((mask & (MASK_ONE << 26)) != 0) - value26 *= value; - - if ((mask & (MASK_ONE << 27)) != 0) - value27 *= value; - - if ((mask & (MASK_ONE << 28)) != 0) - value28 *= value; - - if ((mask & (MASK_ONE << 29)) != 0) - value29 *= value; - - if ((mask & (MASK_ONE << 30)) != 0) - value30 *= value; - - if ((mask & (MASK_ONE << 31)) != 0) - value31 *= value; - - if ((mask & (MASK_ONE << 32)) != 0) - value32 *= value; - - if ((mask & (MASK_ONE << 33)) != 0) - value33 *= value; - - if ((mask & (MASK_ONE << 34)) != 0) - value34 *= value; - - if ((mask & (MASK_ONE << 35)) != 0) - value35 *= value; - - if ((mask & (MASK_ONE << 36)) != 0) - value36 *= value; - - if ((mask & (MASK_ONE << 37)) != 0) - value37 *= value; - - if ((mask & (MASK_ONE << 38)) != 0) - value38 *= value; - - if ((mask & (MASK_ONE << 39)) != 0) - value39 *= value; - } - - while ((mask = *div_mask++) != 0) - { - value = *div_values++; - - __asm__ (" #reg %0" : "+d" (value)); - - if ((mask & (MASK_ONE << 0)) != 0) - value00 /= value; - - if ((mask & (MASK_ONE << 1)) != 0) - value01 /= value; - - if ((mask & (MASK_ONE << 2)) != 0) - value02 /= value; - - if ((mask & (MASK_ONE << 3)) != 0) - value03 /= value; - - if ((mask & (MASK_ONE << 4)) != 0) - value04 /= value; - - if ((mask & (MASK_ONE << 5)) != 0) - value05 /= value; - - if ((mask & (MASK_ONE << 6)) != 0) - value06 /= value; - - if ((mask & (MASK_ONE << 7)) != 0) - value07 /= value; - - if ((mask & (MASK_ONE << 8)) != 0) - value08 /= value; - - if ((mask & (MASK_ONE << 9)) != 0) - value09 /= value; - - if ((mask & (MASK_ONE << 10)) != 0) - value10 /= value; - - if ((mask & (MASK_ONE << 11)) != 0) - value11 /= value; - - if ((mask & (MASK_ONE << 12)) != 0) - value12 /= value; - - if ((mask & (MASK_ONE << 13)) != 0) - value13 /= value; - - if ((mask & (MASK_ONE << 14)) != 0) - value14 /= value; - - if ((mask & (MASK_ONE << 15)) != 0) - value15 /= value; - - if ((mask & (MASK_ONE << 16)) != 0) - value16 /= value; - - if ((mask & (MASK_ONE << 17)) != 0) - value17 /= value; - - if ((mask & (MASK_ONE << 18)) != 0) - value18 /= value; - - if ((mask & (MASK_ONE << 19)) != 0) - value19 /= value; - - if ((mask & (MASK_ONE << 20)) != 0) - value20 /= value; - - if ((mask & (MASK_ONE << 21)) != 0) - value21 /= value; - - if ((mask & (MASK_ONE << 22)) != 0) - value22 /= value; - - if ((mask & (MASK_ONE << 23)) != 0) - value23 /= value; - - if ((mask & (MASK_ONE << 24)) != 0) - value24 /= value; - - if ((mask & (MASK_ONE << 25)) != 0) - value25 /= value; - - if ((mask & (MASK_ONE << 26)) != 0) - value26 /= value; - - if ((mask & (MASK_ONE << 27)) != 0) - value27 /= value; - - if ((mask & (MASK_ONE << 28)) != 0) - value28 /= value; - - if ((mask & (MASK_ONE << 29)) != 0) - value29 /= value; - - if ((mask & (MASK_ONE << 30)) != 0) - value30 /= value; - - if ((mask & (MASK_ONE << 31)) != 0) - value31 /= value; - - if ((mask & (MASK_ONE << 32)) != 0) - value32 /= value; - - if ((mask & (MASK_ONE << 33)) != 0) - value33 /= value; - - if ((mask & (MASK_ONE << 34)) != 0) - value34 /= value; - - if ((mask & (MASK_ONE << 35)) != 0) - value35 /= value; - - if ((mask & (MASK_ONE << 36)) != 0) - value36 /= value; - - if ((mask & (MASK_ONE << 37)) != 0) - value37 /= value; - - if ((mask & (MASK_ONE << 38)) != 0) - value38 /= value; - - if ((mask & (MASK_ONE << 39)) != 0) - value39 /= value; - } - - while ((mask = *eq0_mask++) != 0) - { - eq0 = 0; - - if ((mask & (MASK_ONE << 0)) != 0) - eq0 |= (value00 == ZERO); - - if ((mask & (MASK_ONE << 1)) != 0) - eq0 |= (value01 == ZERO); - - if ((mask & (MASK_ONE << 2)) != 0) - eq0 |= (value02 == ZERO); - - if ((mask & (MASK_ONE << 3)) != 0) - eq0 |= (value03 == ZERO); - - if ((mask & (MASK_ONE << 4)) != 0) - eq0 |= (value04 == ZERO); - - if ((mask & (MASK_ONE << 5)) != 0) - eq0 |= (value05 == ZERO); - - if ((mask & (MASK_ONE << 6)) != 0) - eq0 |= (value06 == ZERO); - - if ((mask & (MASK_ONE << 7)) != 0) - eq0 |= (value07 == ZERO); - - if ((mask & (MASK_ONE << 8)) != 0) - eq0 |= (value08 == ZERO); - - if ((mask & (MASK_ONE << 9)) != 0) - eq0 |= (value09 == ZERO); - - if ((mask & (MASK_ONE << 10)) != 0) - eq0 |= (value10 == ZERO); - - if ((mask & (MASK_ONE << 11)) != 0) - eq0 |= (value11 == ZERO); - - if ((mask & (MASK_ONE << 12)) != 0) - eq0 |= (value12 == ZERO); - - if ((mask & (MASK_ONE << 13)) != 0) - eq0 |= (value13 == ZERO); - - if ((mask & (MASK_ONE << 14)) != 0) - eq0 |= (value14 == ZERO); - - if ((mask & (MASK_ONE << 15)) != 0) - eq0 |= (value15 == ZERO); - - if ((mask & (MASK_ONE << 16)) != 0) - eq0 |= (value16 == ZERO); - - if ((mask & (MASK_ONE << 17)) != 0) - eq0 |= (value17 == ZERO); - - if ((mask & (MASK_ONE << 18)) != 0) - eq0 |= (value18 == ZERO); - - if ((mask & (MASK_ONE << 19)) != 0) - eq0 |= (value19 == ZERO); - - if ((mask & (MASK_ONE << 20)) != 0) - eq0 |= (value20 == ZERO); - - if ((mask & (MASK_ONE << 21)) != 0) - eq0 |= (value21 == ZERO); - - if ((mask & (MASK_ONE << 22)) != 0) - eq0 |= (value22 == ZERO); - - if ((mask & (MASK_ONE << 23)) != 0) - eq0 |= (value23 == ZERO); - - if ((mask & (MASK_ONE << 24)) != 0) - eq0 |= (value24 == ZERO); - - if ((mask & (MASK_ONE << 25)) != 0) - eq0 |= (value25 == ZERO); - - if ((mask & (MASK_ONE << 26)) != 0) - eq0 |= (value26 == ZERO); - - if ((mask & (MASK_ONE << 27)) != 0) - eq0 |= (value27 == ZERO); - - if ((mask & (MASK_ONE << 28)) != 0) - eq0 |= (value28 == ZERO); - - if ((mask & (MASK_ONE << 29)) != 0) - eq0 |= (value29 == ZERO); - - if ((mask & (MASK_ONE << 30)) != 0) - eq0 |= (value30 == ZERO); - - if ((mask & (MASK_ONE << 31)) != 0) - eq0 |= (value31 == ZERO); - - if ((mask & (MASK_ONE << 32)) != 0) - eq0 |= (value32 == ZERO); - - if ((mask & (MASK_ONE << 33)) != 0) - eq0 |= (value33 == ZERO); - - if ((mask & (MASK_ONE << 34)) != 0) - eq0 |= (value34 == ZERO); - - if ((mask & (MASK_ONE << 35)) != 0) - eq0 |= (value35 == ZERO); - - if ((mask & (MASK_ONE << 36)) != 0) - eq0 |= (value36 == ZERO); - - if ((mask & (MASK_ONE << 37)) != 0) - eq0 |= (value37 == ZERO); - - if ((mask & (MASK_ONE << 38)) != 0) - eq0 |= (value38 == ZERO); - - if ((mask & (MASK_ONE << 39)) != 0) - eq0 |= (value39 == ZERO); - - *eq0_ptr++ = eq0; - } - - return ( value00 + value01 + value02 + value03 + value04 - + value05 + value06 + value07 + value08 + value09 - + value10 + value11 + value12 + value13 + value14 - + value15 + value16 + value17 + value18 + value19 - + value20 + value21 + value22 + value23 + value24 - + value25 + value26 + value27 + value28 + value29 - + value30 + value31 + value32 + value33 + value34 - + value35 + value36 + value37 + value38 + value39); -} - -/* { dg-final { scan-assembler "fadd" } } */ -/* { dg-final { scan-assembler "fsub" } } */ -/* { dg-final { scan-assembler "fmul" } } */ -/* { dg-final { scan-assembler "fdiv" } } */ -/* { dg-final { scan-assembler "fcmpu" } } */ -/* { dg-final { scan-assembler "xsadddp" } } */ -/* { dg-final { scan-assembler "xssubdp" } } */ -/* { dg-final { scan-assembler "xsmuldp" } } */ -/* { dg-final { scan-assembler "xsdivdp" } } */ -/* { dg-final { scan-assembler "xscmpudp" } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/pr65849-2.c b/gcc/testsuite/gcc.target/powerpc/pr65849-2.c deleted file mode 100644 index 0af6a4a51c7..00000000000 --- a/gcc/testsuite/gcc.target/powerpc/pr65849-2.c +++ /dev/null @@ -1,728 +0,0 @@ -/* { dg-do compile { target { powerpc*-*-* } } } */ -/* { dg-require-effective-target powerpc_p8vector_ok } */ -/* { dg-skip-if "" { powerpc*-*-darwin* } } */ -/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power8" } } */ -/* { dg-options "-mcpu=power8 -O2 -mno-upper-regs-sf" } */ - -/* Test whether we can enable the -mupper-regs-sf with target pragmas. Make - sure float values are allocated to the Altivec registers as well as the - traditional FPR registers. */ - -#ifndef TYPE -#define TYPE float -#endif - -#ifndef MASK_TYPE -#define MASK_TYPE unsigned long long -#endif - -#define MASK_ONE ((MASK_TYPE)1) -#define ZERO ((TYPE) 0.0) - -#pragma GCC target ("upper-regs-sf") -TYPE -test_add (const MASK_TYPE *add_mask, const TYPE *add_values, - const MASK_TYPE *sub_mask, const TYPE *sub_values, - const MASK_TYPE *mul_mask, const TYPE *mul_values, - const MASK_TYPE *div_mask, const TYPE *div_values, - const MASK_TYPE *eq0_mask, int *eq0_ptr) -{ - TYPE value; - TYPE value00 = ZERO; - TYPE value01 = ZERO; - TYPE value02 = ZERO; - TYPE value03 = ZERO; - TYPE value04 = ZERO; - TYPE value05 = ZERO; - TYPE value06 = ZERO; - TYPE value07 = ZERO; - TYPE value08 = ZERO; - TYPE value09 = ZERO; - TYPE value10 = ZERO; - TYPE value11 = ZERO; - TYPE value12 = ZERO; - TYPE value13 = ZERO; - TYPE value14 = ZERO; - TYPE value15 = ZERO; - TYPE value16 = ZERO; - TYPE value17 = ZERO; - TYPE value18 = ZERO; - TYPE value19 = ZERO; - TYPE value20 = ZERO; - TYPE value21 = ZERO; - TYPE value22 = ZERO; - TYPE value23 = ZERO; - TYPE value24 = ZERO; - TYPE value25 = ZERO; - TYPE value26 = ZERO; - TYPE value27 = ZERO; - TYPE value28 = ZERO; - TYPE value29 = ZERO; - TYPE value30 = ZERO; - TYPE value31 = ZERO; - TYPE value32 = ZERO; - TYPE value33 = ZERO; - TYPE value34 = ZERO; - TYPE value35 = ZERO; - TYPE value36 = ZERO; - TYPE value37 = ZERO; - TYPE value38 = ZERO; - TYPE value39 = ZERO; - MASK_TYPE mask; - int eq0; - - while ((mask = *add_mask++) != 0) - { - value = *add_values++; - - __asm__ (" #reg %0" : "+d" (value)); - - if ((mask & (MASK_ONE << 0)) != 0) - value00 += value; - - if ((mask & (MASK_ONE << 1)) != 0) - value01 += value; - - if ((mask & (MASK_ONE << 2)) != 0) - value02 += value; - - if ((mask & (MASK_ONE << 3)) != 0) - value03 += value; - - if ((mask & (MASK_ONE << 4)) != 0) - value04 += value; - - if ((mask & (MASK_ONE << 5)) != 0) - value05 += value; - - if ((mask & (MASK_ONE << 6)) != 0) - value06 += value; - - if ((mask & (MASK_ONE << 7)) != 0) - value07 += value; - - if ((mask & (MASK_ONE << 8)) != 0) - value08 += value; - - if ((mask & (MASK_ONE << 9)) != 0) - value09 += value; - - if ((mask & (MASK_ONE << 10)) != 0) - value10 += value; - - if ((mask & (MASK_ONE << 11)) != 0) - value11 += value; - - if ((mask & (MASK_ONE << 12)) != 0) - value12 += value; - - if ((mask & (MASK_ONE << 13)) != 0) - value13 += value; - - if ((mask & (MASK_ONE << 14)) != 0) - value14 += value; - - if ((mask & (MASK_ONE << 15)) != 0) - value15 += value; - - if ((mask & (MASK_ONE << 16)) != 0) - value16 += value; - - if ((mask & (MASK_ONE << 17)) != 0) - value17 += value; - - if ((mask & (MASK_ONE << 18)) != 0) - value18 += value; - - if ((mask & (MASK_ONE << 19)) != 0) - value19 += value; - - if ((mask & (MASK_ONE << 20)) != 0) - value20 += value; - - if ((mask & (MASK_ONE << 21)) != 0) - value21 += value; - - if ((mask & (MASK_ONE << 22)) != 0) - value22 += value; - - if ((mask & (MASK_ONE << 23)) != 0) - value23 += value; - - if ((mask & (MASK_ONE << 24)) != 0) - value24 += value; - - if ((mask & (MASK_ONE << 25)) != 0) - value25 += value; - - if ((mask & (MASK_ONE << 26)) != 0) - value26 += value; - - if ((mask & (MASK_ONE << 27)) != 0) - value27 += value; - - if ((mask & (MASK_ONE << 28)) != 0) - value28 += value; - - if ((mask & (MASK_ONE << 29)) != 0) - value29 += value; - - if ((mask & (MASK_ONE << 30)) != 0) - value30 += value; - - if ((mask & (MASK_ONE << 31)) != 0) - value31 += value; - - if ((mask & (MASK_ONE << 32)) != 0) - value32 += value; - - if ((mask & (MASK_ONE << 33)) != 0) - value33 += value; - - if ((mask & (MASK_ONE << 34)) != 0) - value34 += value; - - if ((mask & (MASK_ONE << 35)) != 0) - value35 += value; - - if ((mask & (MASK_ONE << 36)) != 0) - value36 += value; - - if ((mask & (MASK_ONE << 37)) != 0) - value37 += value; - - if ((mask & (MASK_ONE << 38)) != 0) - value38 += value; - - if ((mask & (MASK_ONE << 39)) != 0) - value39 += value; - } - - while ((mask = *sub_mask++) != 0) - { - value = *sub_values++; - - __asm__ (" #reg %0" : "+d" (value)); - - if ((mask & (MASK_ONE << 0)) != 0) - value00 -= value; - - if ((mask & (MASK_ONE << 1)) != 0) - value01 -= value; - - if ((mask & (MASK_ONE << 2)) != 0) - value02 -= value; - - if ((mask & (MASK_ONE << 3)) != 0) - value03 -= value; - - if ((mask & (MASK_ONE << 4)) != 0) - value04 -= value; - - if ((mask & (MASK_ONE << 5)) != 0) - value05 -= value; - - if ((mask & (MASK_ONE << 6)) != 0) - value06 -= value; - - if ((mask & (MASK_ONE << 7)) != 0) - value07 -= value; - - if ((mask & (MASK_ONE << 8)) != 0) - value08 -= value; - - if ((mask & (MASK_ONE << 9)) != 0) - value09 -= value; - - if ((mask & (MASK_ONE << 10)) != 0) - value10 -= value; - - if ((mask & (MASK_ONE << 11)) != 0) - value11 -= value; - - if ((mask & (MASK_ONE << 12)) != 0) - value12 -= value; - - if ((mask & (MASK_ONE << 13)) != 0) - value13 -= value; - - if ((mask & (MASK_ONE << 14)) != 0) - value14 -= value; - - if ((mask & (MASK_ONE << 15)) != 0) - value15 -= value; - - if ((mask & (MASK_ONE << 16)) != 0) - value16 -= value; - - if ((mask & (MASK_ONE << 17)) != 0) - value17 -= value; - - if ((mask & (MASK_ONE << 18)) != 0) - value18 -= value; - - if ((mask & (MASK_ONE << 19)) != 0) - value19 -= value; - - if ((mask & (MASK_ONE << 20)) != 0) - value20 -= value; - - if ((mask & (MASK_ONE << 21)) != 0) - value21 -= value; - - if ((mask & (MASK_ONE << 22)) != 0) - value22 -= value; - - if ((mask & (MASK_ONE << 23)) != 0) - value23 -= value; - - if ((mask & (MASK_ONE << 24)) != 0) - value24 -= value; - - if ((mask & (MASK_ONE << 25)) != 0) - value25 -= value; - - if ((mask & (MASK_ONE << 26)) != 0) - value26 -= value; - - if ((mask & (MASK_ONE << 27)) != 0) - value27 -= value; - - if ((mask & (MASK_ONE << 28)) != 0) - value28 -= value; - - if ((mask & (MASK_ONE << 29)) != 0) - value29 -= value; - - if ((mask & (MASK_ONE << 30)) != 0) - value30 -= value; - - if ((mask & (MASK_ONE << 31)) != 0) - value31 -= value; - - if ((mask & (MASK_ONE << 32)) != 0) - value32 -= value; - - if ((mask & (MASK_ONE << 33)) != 0) - value33 -= value; - - if ((mask & (MASK_ONE << 34)) != 0) - value34 -= value; - - if ((mask & (MASK_ONE << 35)) != 0) - value35 -= value; - - if ((mask & (MASK_ONE << 36)) != 0) - value36 -= value; - - if ((mask & (MASK_ONE << 37)) != 0) - value37 -= value; - - if ((mask & (MASK_ONE << 38)) != 0) - value38 -= value; - - if ((mask & (MASK_ONE << 39)) != 0) - value39 -= value; - } - - while ((mask = *mul_mask++) != 0) - { - value = *mul_values++; - - __asm__ (" #reg %0" : "+d" (value)); - - if ((mask & (MASK_ONE << 0)) != 0) - value00 *= value; - - if ((mask & (MASK_ONE << 1)) != 0) - value01 *= value; - - if ((mask & (MASK_ONE << 2)) != 0) - value02 *= value; - - if ((mask & (MASK_ONE << 3)) != 0) - value03 *= value; - - if ((mask & (MASK_ONE << 4)) != 0) - value04 *= value; - - if ((mask & (MASK_ONE << 5)) != 0) - value05 *= value; - - if ((mask & (MASK_ONE << 6)) != 0) - value06 *= value; - - if ((mask & (MASK_ONE << 7)) != 0) - value07 *= value; - - if ((mask & (MASK_ONE << 8)) != 0) - value08 *= value; - - if ((mask & (MASK_ONE << 9)) != 0) - value09 *= value; - - if ((mask & (MASK_ONE << 10)) != 0) - value10 *= value; - - if ((mask & (MASK_ONE << 11)) != 0) - value11 *= value; - - if ((mask & (MASK_ONE << 12)) != 0) - value12 *= value; - - if ((mask & (MASK_ONE << 13)) != 0) - value13 *= value; - - if ((mask & (MASK_ONE << 14)) != 0) - value14 *= value; - - if ((mask & (MASK_ONE << 15)) != 0) - value15 *= value; - - if ((mask & (MASK_ONE << 16)) != 0) - value16 *= value; - - if ((mask & (MASK_ONE << 17)) != 0) - value17 *= value; - - if ((mask & (MASK_ONE << 18)) != 0) - value18 *= value; - - if ((mask & (MASK_ONE << 19)) != 0) - value19 *= value; - - if ((mask & (MASK_ONE << 20)) != 0) - value20 *= value; - - if ((mask & (MASK_ONE << 21)) != 0) - value21 *= value; - - if ((mask & (MASK_ONE << 22)) != 0) - value22 *= value; - - if ((mask & (MASK_ONE << 23)) != 0) - value23 *= value; - - if ((mask & (MASK_ONE << 24)) != 0) - value24 *= value; - - if ((mask & (MASK_ONE << 25)) != 0) - value25 *= value; - - if ((mask & (MASK_ONE << 26)) != 0) - value26 *= value; - - if ((mask & (MASK_ONE << 27)) != 0) - value27 *= value; - - if ((mask & (MASK_ONE << 28)) != 0) - value28 *= value; - - if ((mask & (MASK_ONE << 29)) != 0) - value29 *= value; - - if ((mask & (MASK_ONE << 30)) != 0) - value30 *= value; - - if ((mask & (MASK_ONE << 31)) != 0) - value31 *= value; - - if ((mask & (MASK_ONE << 32)) != 0) - value32 *= value; - - if ((mask & (MASK_ONE << 33)) != 0) - value33 *= value; - - if ((mask & (MASK_ONE << 34)) != 0) - value34 *= value; - - if ((mask & (MASK_ONE << 35)) != 0) - value35 *= value; - - if ((mask & (MASK_ONE << 36)) != 0) - value36 *= value; - - if ((mask & (MASK_ONE << 37)) != 0) - value37 *= value; - - if ((mask & (MASK_ONE << 38)) != 0) - value38 *= value; - - if ((mask & (MASK_ONE << 39)) != 0) - value39 *= value; - } - - while ((mask = *div_mask++) != 0) - { - value = *div_values++; - - __asm__ (" #reg %0" : "+d" (value)); - - if ((mask & (MASK_ONE << 0)) != 0) - value00 /= value; - - if ((mask & (MASK_ONE << 1)) != 0) - value01 /= value; - - if ((mask & (MASK_ONE << 2)) != 0) - value02 /= value; - - if ((mask & (MASK_ONE << 3)) != 0) - value03 /= value; - - if ((mask & (MASK_ONE << 4)) != 0) - value04 /= value; - - if ((mask & (MASK_ONE << 5)) != 0) - value05 /= value; - - if ((mask & (MASK_ONE << 6)) != 0) - value06 /= value; - - if ((mask & (MASK_ONE << 7)) != 0) - value07 /= value; - - if ((mask & (MASK_ONE << 8)) != 0) - value08 /= value; - - if ((mask & (MASK_ONE << 9)) != 0) - value09 /= value; - - if ((mask & (MASK_ONE << 10)) != 0) - value10 /= value; - - if ((mask & (MASK_ONE << 11)) != 0) - value11 /= value; - - if ((mask & (MASK_ONE << 12)) != 0) - value12 /= value; - - if ((mask & (MASK_ONE << 13)) != 0) - value13 /= value; - - if ((mask & (MASK_ONE << 14)) != 0) - value14 /= value; - - if ((mask & (MASK_ONE << 15)) != 0) - value15 /= value; - - if ((mask & (MASK_ONE << 16)) != 0) - value16 /= value; - - if ((mask & (MASK_ONE << 17)) != 0) - value17 /= value; - - if ((mask & (MASK_ONE << 18)) != 0) - value18 /= value; - - if ((mask & (MASK_ONE << 19)) != 0) - value19 /= value; - - if ((mask & (MASK_ONE << 20)) != 0) - value20 /= value; - - if ((mask & (MASK_ONE << 21)) != 0) - value21 /= value; - - if ((mask & (MASK_ONE << 22)) != 0) - value22 /= value; - - if ((mask & (MASK_ONE << 23)) != 0) - value23 /= value; - - if ((mask & (MASK_ONE << 24)) != 0) - value24 /= value; - - if ((mask & (MASK_ONE << 25)) != 0) - value25 /= value; - - if ((mask & (MASK_ONE << 26)) != 0) - value26 /= value; - - if ((mask & (MASK_ONE << 27)) != 0) - value27 /= value; - - if ((mask & (MASK_ONE << 28)) != 0) - value28 /= value; - - if ((mask & (MASK_ONE << 29)) != 0) - value29 /= value; - - if ((mask & (MASK_ONE << 30)) != 0) - value30 /= value; - - if ((mask & (MASK_ONE << 31)) != 0) - value31 /= value; - - if ((mask & (MASK_ONE << 32)) != 0) - value32 /= value; - - if ((mask & (MASK_ONE << 33)) != 0) - value33 /= value; - - if ((mask & (MASK_ONE << 34)) != 0) - value34 /= value; - - if ((mask & (MASK_ONE << 35)) != 0) - value35 /= value; - - if ((mask & (MASK_ONE << 36)) != 0) - value36 /= value; - - if ((mask & (MASK_ONE << 37)) != 0) - value37 /= value; - - if ((mask & (MASK_ONE << 38)) != 0) - value38 /= value; - - if ((mask & (MASK_ONE << 39)) != 0) - value39 /= value; - } - - while ((mask = *eq0_mask++) != 0) - { - eq0 = 0; - - if ((mask & (MASK_ONE << 0)) != 0) - eq0 |= (value00 == ZERO); - - if ((mask & (MASK_ONE << 1)) != 0) - eq0 |= (value01 == ZERO); - - if ((mask & (MASK_ONE << 2)) != 0) - eq0 |= (value02 == ZERO); - - if ((mask & (MASK_ONE << 3)) != 0) - eq0 |= (value03 == ZERO); - - if ((mask & (MASK_ONE << 4)) != 0) - eq0 |= (value04 == ZERO); - - if ((mask & (MASK_ONE << 5)) != 0) - eq0 |= (value05 == ZERO); - - if ((mask & (MASK_ONE << 6)) != 0) - eq0 |= (value06 == ZERO); - - if ((mask & (MASK_ONE << 7)) != 0) - eq0 |= (value07 == ZERO); - - if ((mask & (MASK_ONE << 8)) != 0) - eq0 |= (value08 == ZERO); - - if ((mask & (MASK_ONE << 9)) != 0) - eq0 |= (value09 == ZERO); - - if ((mask & (MASK_ONE << 10)) != 0) - eq0 |= (value10 == ZERO); - - if ((mask & (MASK_ONE << 11)) != 0) - eq0 |= (value11 == ZERO); - - if ((mask & (MASK_ONE << 12)) != 0) - eq0 |= (value12 == ZERO); - - if ((mask & (MASK_ONE << 13)) != 0) - eq0 |= (value13 == ZERO); - - if ((mask & (MASK_ONE << 14)) != 0) - eq0 |= (value14 == ZERO); - - if ((mask & (MASK_ONE << 15)) != 0) - eq0 |= (value15 == ZERO); - - if ((mask & (MASK_ONE << 16)) != 0) - eq0 |= (value16 == ZERO); - - if ((mask & (MASK_ONE << 17)) != 0) - eq0 |= (value17 == ZERO); - - if ((mask & (MASK_ONE << 18)) != 0) - eq0 |= (value18 == ZERO); - - if ((mask & (MASK_ONE << 19)) != 0) - eq0 |= (value19 == ZERO); - - if ((mask & (MASK_ONE << 20)) != 0) - eq0 |= (value20 == ZERO); - - if ((mask & (MASK_ONE << 21)) != 0) - eq0 |= (value21 == ZERO); - - if ((mask & (MASK_ONE << 22)) != 0) - eq0 |= (value22 == ZERO); - - if ((mask & (MASK_ONE << 23)) != 0) - eq0 |= (value23 == ZERO); - - if ((mask & (MASK_ONE << 24)) != 0) - eq0 |= (value24 == ZERO); - - if ((mask & (MASK_ONE << 25)) != 0) - eq0 |= (value25 == ZERO); - - if ((mask & (MASK_ONE << 26)) != 0) - eq0 |= (value26 == ZERO); - - if ((mask & (MASK_ONE << 27)) != 0) - eq0 |= (value27 == ZERO); - - if ((mask & (MASK_ONE << 28)) != 0) - eq0 |= (value28 == ZERO); - - if ((mask & (MASK_ONE << 29)) != 0) - eq0 |= (value29 == ZERO); - - if ((mask & (MASK_ONE << 30)) != 0) - eq0 |= (value30 == ZERO); - - if ((mask & (MASK_ONE << 31)) != 0) - eq0 |= (value31 == ZERO); - - if ((mask & (MASK_ONE << 32)) != 0) - eq0 |= (value32 == ZERO); - - if ((mask & (MASK_ONE << 33)) != 0) - eq0 |= (value33 == ZERO); - - if ((mask & (MASK_ONE << 34)) != 0) - eq0 |= (value34 == ZERO); - - if ((mask & (MASK_ONE << 35)) != 0) - eq0 |= (value35 == ZERO); - - if ((mask & (MASK_ONE << 36)) != 0) - eq0 |= (value36 == ZERO); - - if ((mask & (MASK_ONE << 37)) != 0) - eq0 |= (value37 == ZERO); - - if ((mask & (MASK_ONE << 38)) != 0) - eq0 |= (value38 == ZERO); - - if ((mask & (MASK_ONE << 39)) != 0) - eq0 |= (value39 == ZERO); - - *eq0_ptr++ = eq0; - } - - return ( value00 + value01 + value02 + value03 + value04 - + value05 + value06 + value07 + value08 + value09 - + value10 + value11 + value12 + value13 + value14 - + value15 + value16 + value17 + value18 + value19 - + value20 + value21 + value22 + value23 + value24 - + value25 + value26 + value27 + value28 + value29 - + value30 + value31 + value32 + value33 + value34 - + value35 + value36 + value37 + value38 + value39); -} - -/* { dg-final { scan-assembler "fadds" } } */ -/* { dg-final { scan-assembler "fsubs" } } */ -/* { dg-final { scan-assembler "fmuls" } } */ -/* { dg-final { scan-assembler "fdivs" } } */ -/* { dg-final { scan-assembler "fcmpu" } } */ -/* { dg-final { scan-assembler "xsaddsp" } } */ -/* { dg-final { scan-assembler "xssubsp" } } */ -/* { dg-final { scan-assembler "xsmulsp" } } */ -/* { dg-final { scan-assembler "xsdivsp" } } */ -/* { dg-final { scan-assembler "xscmpudp" } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/pr67808.c b/gcc/testsuite/gcc.target/powerpc/pr67808.c index 16b309c151e..3ee8003bebc 100644 --- a/gcc/testsuite/gcc.target/powerpc/pr67808.c +++ b/gcc/testsuite/gcc.target/powerpc/pr67808.c @@ -2,7 +2,7 @@ /* { dg-skip-if "" { powerpc*-*-darwin* } } */ /* { dg-require-effective-target powerpc_vsx_ok } */ /* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power7" } } */ -/* { dg-options "-O1 -mvsx -mlra -mcpu=power7 -mlong-double-128" } */ +/* { dg-options "-O1 -mvsx -mcpu=power7 -mlong-double-128" } */ /* PR 67808: LRA ICEs on simple double to long double conversion test case */ diff --git a/gcc/testsuite/gcc.target/powerpc/pr68805.c b/gcc/testsuite/gcc.target/powerpc/pr68805.c index 5510811107d..f4454a9e2d2 100644 --- a/gcc/testsuite/gcc.target/powerpc/pr68805.c +++ b/gcc/testsuite/gcc.target/powerpc/pr68805.c @@ -1,6 +1,6 @@ /* { dg-do compile { target powerpc64le-*-* } } */ /* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power8" } } */ -/* { dg-options "-O2 -mvsx-timode -mcpu=power8 -mlra" } */ +/* { dg-options "-O2 -mvsx-timode -mcpu=power8" } */ typedef struct bar { void *a; diff --git a/gcc/testsuite/gcc.target/powerpc/pr69461.c b/gcc/testsuite/gcc.target/powerpc/pr69461.c index 406e7049d29..f693a5f0146 100644 --- a/gcc/testsuite/gcc.target/powerpc/pr69461.c +++ b/gcc/testsuite/gcc.target/powerpc/pr69461.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-O3 -mlra" } */ +/* { dg-options "-O3" } */ extern void _setjmp (void); typedef struct { diff --git a/gcc/testsuite/gcc.target/powerpc/pr71656-1.c b/gcc/testsuite/gcc.target/powerpc/pr71656-1.c index fa6b4ffb816..1cb809f8b2a 100644 --- a/gcc/testsuite/gcc.target/powerpc/pr71656-1.c +++ b/gcc/testsuite/gcc.target/powerpc/pr71656-1.c @@ -2,7 +2,7 @@ /* { dg-do compile } */ /* { dg-require-effective-target powerpc_p9vector_ok } */ /* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ -/* { dg-options "-O1 -mcpu=power9 -mpower9-dform-vector -mno-lra" } */ +/* { dg-options "-O1 -mcpu=power9 -mpower9-dform-vector" } */ typedef __attribute__((altivec(vector__))) int type_t; type_t diff --git a/gcc/testsuite/gcc.target/powerpc/pr71656-2.c b/gcc/testsuite/gcc.target/powerpc/pr71656-2.c index 99855fa1667..f953ebe4f9e 100644 --- a/gcc/testsuite/gcc.target/powerpc/pr71656-2.c +++ b/gcc/testsuite/gcc.target/powerpc/pr71656-2.c @@ -2,7 +2,7 @@ /* { dg-do compile } */ /* { dg-require-effective-target powerpc_p9vector_ok } */ /* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ -/* { dg-options "-O3 -mcpu=power9 -mpower9-dform-vector -mno-lra -funroll-loops -fno-aggressive-loop-optimizations" } */ +/* { dg-options "-O3 -mcpu=power9 -mpower9-dform-vector -funroll-loops -fno-aggressive-loop-optimizations" } */ typedef double vec[3]; struct vec_t diff --git a/gcc/testsuite/gcc.target/powerpc/pr71680.c b/gcc/testsuite/gcc.target/powerpc/pr71680.c index fe5260f73d9..cdb7b5143ed 100644 --- a/gcc/testsuite/gcc.target/powerpc/pr71680.c +++ b/gcc/testsuite/gcc.target/powerpc/pr71680.c @@ -1,7 +1,7 @@ /* { dg-do compile { target { powerpc*-*-* } } } */ /* { dg-require-effective-target powerpc_vsx_ok } */ /* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power8" } } */ -/* { dg-options "-mcpu=power8 -O1 -mlra" } */ +/* { dg-options "-mcpu=power8 -O1" } */ #pragma pack(1) struct diff --git a/gcc/testsuite/gcc.target/powerpc/pr71698.c b/gcc/testsuite/gcc.target/powerpc/pr71698.c index c752f64e1c7..eba47b0951f 100644 --- a/gcc/testsuite/gcc.target/powerpc/pr71698.c +++ b/gcc/testsuite/gcc.target/powerpc/pr71698.c @@ -3,7 +3,7 @@ /* { dg-require-effective-target powerpc_p9vector_ok } */ /* { dg-require-effective-target dfp } */ /* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ -/* { dg-options "-O1 -mcpu=power9 -mno-lra" } */ +/* { dg-options "-O1 -mcpu=power9" } */ extern void testvad128 (int n, ...); void diff --git a/gcc/testsuite/gcc.target/powerpc/pr71720.c b/gcc/testsuite/gcc.target/powerpc/pr71720.c index a0c330db931..732daf97595 100644 --- a/gcc/testsuite/gcc.target/powerpc/pr71720.c +++ b/gcc/testsuite/gcc.target/powerpc/pr71720.c @@ -1,7 +1,7 @@ /* { dg-do compile { target { powerpc64*-*-* && lp64 } } } */ /* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ /* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-mcpu=power9 -O2 -mupper-regs-di" } */ +/* { dg-options "-mcpu=power9 -O2" } */ /* Verify that we generate xxspltw <reg>,<reg>,0 for V4SFmode splat. */ diff --git a/gcc/testsuite/gcc.target/powerpc/pr72853.c b/gcc/testsuite/gcc.target/powerpc/pr72853.c index 8a086087088..9dc1bd2344c 100644 --- a/gcc/testsuite/gcc.target/powerpc/pr72853.c +++ b/gcc/testsuite/gcc.target/powerpc/pr72853.c @@ -2,7 +2,7 @@ /* { dg-skip-if "" { powerpc*-*-darwin* } } */ /* { dg-require-effective-target powerpc_p9vector_ok } */ /* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ -/* { dg-options "-mcpu=power9 -O3 -mupper-regs-df -mupper-regs-sf -funroll-loops" } */ +/* { dg-options "-mcpu=power9 -O3 -funroll-loops" } */ /* derived from 20021120-1.c, compiled for -mcpu=power9. */ diff --git a/gcc/testsuite/gcc.target/powerpc/pr77289.c b/gcc/testsuite/gcc.target/powerpc/pr77289.c index 295aa27acdc..474bdbf0b16 100644 --- a/gcc/testsuite/gcc.target/powerpc/pr77289.c +++ b/gcc/testsuite/gcc.target/powerpc/pr77289.c @@ -2,7 +2,7 @@ /* { dg-skip-if "" { powerpc*-*-darwin* } } */ /* { dg-require-effective-target powerpc_vsx_ok } */ /* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power7" } } */ -/* { dg-options "-O3 -mcpu=power7 -funroll-loops -ffast-math -mlra -mupdate -fno-auto-inc-dec" } */ +/* { dg-options "-O3 -mcpu=power7 -funroll-loops -ffast-math -mupdate -fno-auto-inc-dec" } */ /* PR 77289: LRA ICEs due to invalid constraint checking. */ diff --git a/gcc/testsuite/gcc.target/powerpc/pr78458.c b/gcc/testsuite/gcc.target/powerpc/pr78458.c index 777ac43bcad..a27876375af 100644 --- a/gcc/testsuite/gcc.target/powerpc/pr78458.c +++ b/gcc/testsuite/gcc.target/powerpc/pr78458.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-mcpu=8548 -mspe -mabi=spe -mlra" } */ +/* { dg-options "-mcpu=8548 -mspe -mabi=spe" } */ /* { dg-skip-if "not an SPE target" { ! powerpc_spe_nocache } } */ extern void bar (void); diff --git a/gcc/testsuite/gcc.target/powerpc/pr78543.c b/gcc/testsuite/gcc.target/powerpc/pr78543.c index 0421344d3ce..13b34e58a0b 100644 --- a/gcc/testsuite/gcc.target/powerpc/pr78543.c +++ b/gcc/testsuite/gcc.target/powerpc/pr78543.c @@ -1,7 +1,7 @@ /* { dg-do compile { target { powerpc64*-*-* && lp64 } } } */ /* { dg-require-effective-target powerpc_p8vector_ok } */ /* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power8" } } */ -/* { dg-options "-mcpu=power8 -O1 -mno-lra" } */ +/* { dg-options "-mcpu=power8 -O1" } */ typedef long a; enum c { e, f, g, h, i, ab } j(); diff --git a/gcc/testsuite/gcc.target/powerpc/pr78953.c b/gcc/testsuite/gcc.target/powerpc/pr78953.c index 34a3083918d..fd26f073499 100644 --- a/gcc/testsuite/gcc.target/powerpc/pr78953.c +++ b/gcc/testsuite/gcc.target/powerpc/pr78953.c @@ -1,7 +1,7 @@ /* { dg-do compile { target { powerpc64*-*-* && lp64 } } } */ /* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ /* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-mcpu=power9 -O2 -mupper-regs-di" } */ +/* { dg-options "-mcpu=power9 -O2" } */ #include <altivec.h> @@ -16,4 +16,4 @@ foo (vector int *vp, int *ip) ip[4] = vec_extract (v, 0); } -/* { dg-final { scan-assembler "xxextractuw\|vextuw\[lr\]x" } } */ +/* { dg-final { scan-assembler {\mxxextractuw\M|\mvextuw[lr]x\M} } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/pr79907.c b/gcc/testsuite/gcc.target/powerpc/pr79907.c index c0e669b3264..240a1f46713 100644 --- a/gcc/testsuite/gcc.target/powerpc/pr79907.c +++ b/gcc/testsuite/gcc.target/powerpc/pr79907.c @@ -1,7 +1,7 @@ /* { dg-do compile { target { powerpc*-*-* } } } */ /* { dg-require-effective-target powerpc_p8vector_ok } */ /* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power8" } } */ -/* { dg-options "-mcpu=power8 -O3 -mno-upper-regs-df" } */ +/* { dg-options "-mcpu=power8 -O3" } */ int foo (short a[], int x) { diff --git a/gcc/testsuite/gcc.target/powerpc/pr80099-1.c b/gcc/testsuite/gcc.target/powerpc/pr80099-1.c deleted file mode 100644 index 9f34c5fbef8..00000000000 --- a/gcc/testsuite/gcc.target/powerpc/pr80099-1.c +++ /dev/null @@ -1,12 +0,0 @@ -/* { dg-do compile { target { powerpc*-*-* && lp64 } } } */ -/* { dg-require-effective-target powerpc_p8vector_ok } */ -/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power8" } } */ -/* { dg-options "-mcpu=power8 -O2 -mno-upper-regs-sf" } */ - -/* PR target/80099: compiler internal error if -mno-upper-regs-sf used. */ - -int a; -int int_from_mem (vector float *c) -{ - return __builtin_vec_extract (*c, a); -} diff --git a/gcc/testsuite/gcc.target/powerpc/pr80099-2.c b/gcc/testsuite/gcc.target/powerpc/pr80099-2.c deleted file mode 100644 index 5800db63212..00000000000 --- a/gcc/testsuite/gcc.target/powerpc/pr80099-2.c +++ /dev/null @@ -1,128 +0,0 @@ -/* { dg-do compile { target { powerpc*-*-* && lp64 } } } */ -/* { dg-require-effective-target powerpc_p8vector_ok } */ -/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power8" } } */ -/* { dg-options "-mcpu=power8 -O2 -mno-upper-regs-sf" } */ - -/* PR target/80099 was an issue with -mno-upper-regs-sf. Test for all variable - extract types with various -mno-upper-regs-* options. */ - -double -d_extract_arg_n (vector double v, unsigned long n) -{ - return __builtin_vec_extract (v, n); -} - -float -f_extract_arg_n (vector float v, unsigned long n) -{ - return __builtin_vec_extract (v, n); -} - -long -sl_extract_arg_n (vector long v, unsigned long n) -{ - return (long) __builtin_vec_extract (v, n); -} - -unsigned long -ul_extract_arg_n (vector unsigned long v, unsigned long n) -{ - return (unsigned long) __builtin_vec_extract (v, n); -} - -long -si_extract_arg_n (vector int v, unsigned long n) -{ - return (int) __builtin_vec_extract (v, n); -} - -unsigned long -ui_extract_arg_n (vector unsigned int v, unsigned long n) -{ - return (unsigned int) __builtin_vec_extract (v, n); -} - -long -ss_extract_arg_n (vector short v, unsigned long n) -{ - return (short) __builtin_vec_extract (v, n); -} - -unsigned long -us_extract_arg_n (vector unsigned short v, unsigned long n) -{ - return (unsigned short) __builtin_vec_extract (v, n); -} - -long -sc_extract_arg_n (vector signed char v, unsigned long n) -{ - return (signed char) __builtin_vec_extract (v, n); -} - -unsigned long -uc_extract_arg_n (vector unsigned char v, unsigned long n) -{ - return (unsigned char) __builtin_vec_extract (v, n); -} - - -double -d_extract_mem_n (vector double *p, unsigned long n) -{ - return __builtin_vec_extract (*p, n); -} - -float -f_extract_mem_n (vector float *p, unsigned long n) -{ - return __builtin_vec_extract (*p, n); -} - -long -sl_extract_mem_n (vector long *p, unsigned long n) -{ - return (long) __builtin_vec_extract (*p, n); -} - -unsigned long -ul_extract_mem_n (vector unsigned long *p, unsigned long n) -{ - return (unsigned long) __builtin_vec_extract (*p, n); -} - -long -si_extract_mem_n (vector int *p, unsigned long n) -{ - return (int) __builtin_vec_extract (*p, n); -} - -unsigned long -ui_extract_mem_n (vector unsigned int *p, unsigned long n) -{ - return (unsigned int) __builtin_vec_extract (*p, n); -} - -long -ss_extract_mem_n (vector short *p, unsigned long n) -{ - return (short) __builtin_vec_extract (*p, n); -} - -unsigned long -us_extract_mem_n (vector unsigned short *p, unsigned long n) -{ - return (unsigned short) __builtin_vec_extract (*p, n); -} - -long -sc_extract_mem_n (vector signed char *p, unsigned long n) -{ - return (signed char) __builtin_vec_extract (*p, n); -} - -unsigned long -uc_extract_mem_n (vector unsigned char *p, unsigned long n) -{ - return (unsigned char) __builtin_vec_extract (*p, n); -} diff --git a/gcc/testsuite/gcc.target/powerpc/pr80099-3.c b/gcc/testsuite/gcc.target/powerpc/pr80099-3.c deleted file mode 100644 index 71c2b40b0d1..00000000000 --- a/gcc/testsuite/gcc.target/powerpc/pr80099-3.c +++ /dev/null @@ -1,128 +0,0 @@ -/* { dg-do compile { target { powerpc*-*-* && lp64 } } } */ -/* { dg-require-effective-target powerpc_p8vector_ok } */ -/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power8" } } */ -/* { dg-options "-mcpu=power8 -O2 -mno-upper-regs-df" } */ - -/* PR target/80099 was an issue with -mno-upper-regs-sf. Test for all variable - extract types with various -mno-upper-regs-* options. */ - -double -d_extract_arg_n (vector double v, unsigned long n) -{ - return __builtin_vec_extract (v, n); -} - -float -f_extract_arg_n (vector float v, unsigned long n) -{ - return __builtin_vec_extract (v, n); -} - -long -sl_extract_arg_n (vector long v, unsigned long n) -{ - return (long) __builtin_vec_extract (v, n); -} - -unsigned long -ul_extract_arg_n (vector unsigned long v, unsigned long n) -{ - return (unsigned long) __builtin_vec_extract (v, n); -} - -long -si_extract_arg_n (vector int v, unsigned long n) -{ - return (int) __builtin_vec_extract (v, n); -} - -unsigned long -ui_extract_arg_n (vector unsigned int v, unsigned long n) -{ - return (unsigned int) __builtin_vec_extract (v, n); -} - -long -ss_extract_arg_n (vector short v, unsigned long n) -{ - return (short) __builtin_vec_extract (v, n); -} - -unsigned long -us_extract_arg_n (vector unsigned short v, unsigned long n) -{ - return (unsigned short) __builtin_vec_extract (v, n); -} - -long -sc_extract_arg_n (vector signed char v, unsigned long n) -{ - return (signed char) __builtin_vec_extract (v, n); -} - -unsigned long -uc_extract_arg_n (vector unsigned char v, unsigned long n) -{ - return (unsigned char) __builtin_vec_extract (v, n); -} - - -double -d_extract_mem_n (vector double *p, unsigned long n) -{ - return __builtin_vec_extract (*p, n); -} - -float -f_extract_mem_n (vector float *p, unsigned long n) -{ - return __builtin_vec_extract (*p, n); -} - -long -sl_extract_mem_n (vector long *p, unsigned long n) -{ - return (long) __builtin_vec_extract (*p, n); -} - -unsigned long -ul_extract_mem_n (vector unsigned long *p, unsigned long n) -{ - return (unsigned long) __builtin_vec_extract (*p, n); -} - -long -si_extract_mem_n (vector int *p, unsigned long n) -{ - return (int) __builtin_vec_extract (*p, n); -} - -unsigned long -ui_extract_mem_n (vector unsigned int *p, unsigned long n) -{ - return (unsigned int) __builtin_vec_extract (*p, n); -} - -long -ss_extract_mem_n (vector short *p, unsigned long n) -{ - return (short) __builtin_vec_extract (*p, n); -} - -unsigned long -us_extract_mem_n (vector unsigned short *p, unsigned long n) -{ - return (unsigned short) __builtin_vec_extract (*p, n); -} - -long -sc_extract_mem_n (vector signed char *p, unsigned long n) -{ - return (signed char) __builtin_vec_extract (*p, n); -} - -unsigned long -uc_extract_mem_n (vector unsigned char *p, unsigned long n) -{ - return (unsigned char) __builtin_vec_extract (*p, n); -} diff --git a/gcc/testsuite/gcc.target/powerpc/pr80099-4.c b/gcc/testsuite/gcc.target/powerpc/pr80099-4.c deleted file mode 100644 index 145dd1724af..00000000000 --- a/gcc/testsuite/gcc.target/powerpc/pr80099-4.c +++ /dev/null @@ -1,128 +0,0 @@ -/* { dg-do compile { target { powerpc*-*-* && lp64 } } } */ -/* { dg-require-effective-target powerpc_p8vector_ok } */ -/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power8" } } */ -/* { dg-options "-mcpu=power8 -O2 -mno-upper-regs-di" } */ - -/* PR target/80099 was an issue with -mno-upper-regs-sf. Test for all variable - extract types with various -mno-upper-regs-* options. */ - -double -d_extract_arg_n (vector double v, unsigned long n) -{ - return __builtin_vec_extract (v, n); -} - -float -f_extract_arg_n (vector float v, unsigned long n) -{ - return __builtin_vec_extract (v, n); -} - -long -sl_extract_arg_n (vector long v, unsigned long n) -{ - return (long) __builtin_vec_extract (v, n); -} - -unsigned long -ul_extract_arg_n (vector unsigned long v, unsigned long n) -{ - return (unsigned long) __builtin_vec_extract (v, n); -} - -long -si_extract_arg_n (vector int v, unsigned long n) -{ - return (int) __builtin_vec_extract (v, n); -} - -unsigned long -ui_extract_arg_n (vector unsigned int v, unsigned long n) -{ - return (unsigned int) __builtin_vec_extract (v, n); -} - -long -ss_extract_arg_n (vector short v, unsigned long n) -{ - return (short) __builtin_vec_extract (v, n); -} - -unsigned long -us_extract_arg_n (vector unsigned short v, unsigned long n) -{ - return (unsigned short) __builtin_vec_extract (v, n); -} - -long -sc_extract_arg_n (vector signed char v, unsigned long n) -{ - return (signed char) __builtin_vec_extract (v, n); -} - -unsigned long -uc_extract_arg_n (vector unsigned char v, unsigned long n) -{ - return (unsigned char) __builtin_vec_extract (v, n); -} - - -double -d_extract_mem_n (vector double *p, unsigned long n) -{ - return __builtin_vec_extract (*p, n); -} - -float -f_extract_mem_n (vector float *p, unsigned long n) -{ - return __builtin_vec_extract (*p, n); -} - -long -sl_extract_mem_n (vector long *p, unsigned long n) -{ - return (long) __builtin_vec_extract (*p, n); -} - -unsigned long -ul_extract_mem_n (vector unsigned long *p, unsigned long n) -{ - return (unsigned long) __builtin_vec_extract (*p, n); -} - -long -si_extract_mem_n (vector int *p, unsigned long n) -{ - return (int) __builtin_vec_extract (*p, n); -} - -unsigned long -ui_extract_mem_n (vector unsigned int *p, unsigned long n) -{ - return (unsigned int) __builtin_vec_extract (*p, n); -} - -long -ss_extract_mem_n (vector short *p, unsigned long n) -{ - return (short) __builtin_vec_extract (*p, n); -} - -unsigned long -us_extract_mem_n (vector unsigned short *p, unsigned long n) -{ - return (unsigned short) __builtin_vec_extract (*p, n); -} - -long -sc_extract_mem_n (vector signed char *p, unsigned long n) -{ - return (signed char) __builtin_vec_extract (*p, n); -} - -unsigned long -uc_extract_mem_n (vector unsigned char *p, unsigned long n) -{ - return (unsigned char) __builtin_vec_extract (*p, n); -} diff --git a/gcc/testsuite/gcc.target/powerpc/pr80099-5.c b/gcc/testsuite/gcc.target/powerpc/pr80099-5.c deleted file mode 100644 index 9ebc0fe466d..00000000000 --- a/gcc/testsuite/gcc.target/powerpc/pr80099-5.c +++ /dev/null @@ -1,128 +0,0 @@ -/* { dg-do compile { target { powerpc*-*-* && lp64 } } } */ -/* { dg-require-effective-target powerpc_p8vector_ok } */ -/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power8" } } */ -/* { dg-options "-mcpu=power8 -O2 -mno-upper-regs" } */ - -/* PR target/80099 was an issue with -mno-upper-regs-sf. Test for all variable - extract types with various -mno-upper-regs-* options. */ - -double -d_extract_arg_n (vector double v, unsigned long n) -{ - return __builtin_vec_extract (v, n); -} - -float -f_extract_arg_n (vector float v, unsigned long n) -{ - return __builtin_vec_extract (v, n); -} - -long -sl_extract_arg_n (vector long v, unsigned long n) -{ - return (long) __builtin_vec_extract (v, n); -} - -unsigned long -ul_extract_arg_n (vector unsigned long v, unsigned long n) -{ - return (unsigned long) __builtin_vec_extract (v, n); -} - -long -si_extract_arg_n (vector int v, unsigned long n) -{ - return (int) __builtin_vec_extract (v, n); -} - -unsigned long -ui_extract_arg_n (vector unsigned int v, unsigned long n) -{ - return (unsigned int) __builtin_vec_extract (v, n); -} - -long -ss_extract_arg_n (vector short v, unsigned long n) -{ - return (short) __builtin_vec_extract (v, n); -} - -unsigned long -us_extract_arg_n (vector unsigned short v, unsigned long n) -{ - return (unsigned short) __builtin_vec_extract (v, n); -} - -long -sc_extract_arg_n (vector signed char v, unsigned long n) -{ - return (signed char) __builtin_vec_extract (v, n); -} - -unsigned long -uc_extract_arg_n (vector unsigned char v, unsigned long n) -{ - return (unsigned char) __builtin_vec_extract (v, n); -} - - -double -d_extract_mem_n (vector double *p, unsigned long n) -{ - return __builtin_vec_extract (*p, n); -} - -float -f_extract_mem_n (vector float *p, unsigned long n) -{ - return __builtin_vec_extract (*p, n); -} - -long -sl_extract_mem_n (vector long *p, unsigned long n) -{ - return (long) __builtin_vec_extract (*p, n); -} - -unsigned long -ul_extract_mem_n (vector unsigned long *p, unsigned long n) -{ - return (unsigned long) __builtin_vec_extract (*p, n); -} - -long -si_extract_mem_n (vector int *p, unsigned long n) -{ - return (int) __builtin_vec_extract (*p, n); -} - -unsigned long -ui_extract_mem_n (vector unsigned int *p, unsigned long n) -{ - return (unsigned int) __builtin_vec_extract (*p, n); -} - -long -ss_extract_mem_n (vector short *p, unsigned long n) -{ - return (short) __builtin_vec_extract (*p, n); -} - -unsigned long -us_extract_mem_n (vector unsigned short *p, unsigned long n) -{ - return (unsigned short) __builtin_vec_extract (*p, n); -} - -long -sc_extract_mem_n (vector signed char *p, unsigned long n) -{ - return (signed char) __builtin_vec_extract (*p, n); -} - -unsigned long -uc_extract_mem_n (vector unsigned char *p, unsigned long n) -{ - return (unsigned char) __builtin_vec_extract (*p, n); -} diff --git a/gcc/testsuite/gcc.target/powerpc/pr80103-1.c b/gcc/testsuite/gcc.target/powerpc/pr80103-1.c index 35d48c4d8ce..bbec707df20 100644 --- a/gcc/testsuite/gcc.target/powerpc/pr80103-1.c +++ b/gcc/testsuite/gcc.target/powerpc/pr80103-1.c @@ -12,5 +12,5 @@ int a; void b (__attribute__ ((__vector_size__ (16))) char c) { - a = ((__attributes__ ((__vector_size__ (2 * sizeof (long)))) long) c)[0]; + a = ((__attribute__ ((__vector_size__ (2 * sizeof (long)))) long) c)[0]; } diff --git a/gcc/testsuite/gcc.target/powerpc/pr81348.c b/gcc/testsuite/gcc.target/powerpc/pr81348.c new file mode 100644 index 00000000000..e8e10bb598b --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/pr81348.c @@ -0,0 +1,24 @@ +/* { dg-do compile { target { powerpc64*-*-* && lp64 } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ +/* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-options "-mcpu=power9 -Og" } */ + +/* PR target/81348: Compiler died in doing short->float conversion due to using + the wrong register in a define_split. */ + +int a; +short b; +float ***c; + +void d(void) +{ + int e = 3; + + if (a) + e = b; + + ***c = e; +} + +/* { dg-final { scan-assembler {\mlxsihzx\M} } } */ +/* { dg-final { scan-assembler {\mvextsh2d\M} } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/upper-regs-df.c b/gcc/testsuite/gcc.target/powerpc/upper-regs-df.c index 17f01bfbfca..0df579797ad 100644 --- a/gcc/testsuite/gcc.target/powerpc/upper-regs-df.c +++ b/gcc/testsuite/gcc.target/powerpc/upper-regs-df.c @@ -2,10 +2,10 @@ /* { dg-require-effective-target powerpc_vsx_ok } */ /* { dg-skip-if "" { powerpc*-*-darwin* } } */ /* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power8" } } */ -/* { dg-options "-mcpu=power7 -O2 -mupper-regs-df" } */ +/* { dg-options "-mcpu=power7 -O2" } */ -/* Test for the -mupper-regs-df option to make sure double values are allocated - to the Altivec registers as well as the traditional FPR registers. */ +/* Test to make sure double values are allocated to the Altivec registers as + well as the traditional FPR registers. */ #ifndef TYPE #define TYPE double diff --git a/gcc/testsuite/gcc.target/powerpc/upper-regs-sf.c b/gcc/testsuite/gcc.target/powerpc/upper-regs-sf.c index 8c246796805..fd29fb5fd6e 100644 --- a/gcc/testsuite/gcc.target/powerpc/upper-regs-sf.c +++ b/gcc/testsuite/gcc.target/powerpc/upper-regs-sf.c @@ -2,10 +2,10 @@ /* { dg-require-effective-target powerpc_p8vector_ok } */ /* { dg-skip-if "" { powerpc*-*-darwin* } } */ /* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power8" } } */ -/* { dg-options "-mcpu=power8 -O2 -mupper-regs-df -mupper-regs-sf" } */ +/* { dg-options "-mcpu=power8 -O2" } */ -/* Test for the -mupper-regs-df option to make sure double values are allocated - to the Altivec registers as well as the traditional FPR registers. */ +/* Test make sure single precision values are allocated to the Altivec + registers as well as the traditional FPR registers. */ #ifndef TYPE #define TYPE float diff --git a/gcc/testsuite/gcc.target/powerpc/vec-extract-1.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-1.c index 2f9624d4c86..9c8e6f3a684 100644 --- a/gcc/testsuite/gcc.target/powerpc/vec-extract-1.c +++ b/gcc/testsuite/gcc.target/powerpc/vec-extract-1.c @@ -2,7 +2,7 @@ /* { dg-skip-if "" { powerpc*-*-darwin* } } */ /* { dg-require-effective-target powerpc_p8vector_ok } */ /* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power8" } } */ -/* { dg-options "-mcpu=power8 -O2 -mupper-regs-df -mupper-regs-di" } */ +/* { dg-options "-mcpu=power8 -O2" } */ #include <altivec.h> diff --git a/gcc/testsuite/gcc.target/powerpc/vec-init-3.c b/gcc/testsuite/gcc.target/powerpc/vec-init-3.c index d6d546942da..f4a536a2ea9 100644 --- a/gcc/testsuite/gcc.target/powerpc/vec-init-3.c +++ b/gcc/testsuite/gcc.target/powerpc/vec-init-3.c @@ -1,7 +1,7 @@ /* { dg-do compile { target { powerpc64*-*-* && lp64 } } } */ /* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ /* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-mcpu=power9 -O2 -mupper-regs-di" } */ +/* { dg-options "-mcpu=power9 -O2" } */ vector long merge (long a, long b) diff --git a/gcc/testsuite/gcc.target/powerpc/vec-init-6.c b/gcc/testsuite/gcc.target/powerpc/vec-init-6.c index 14e605ca435..8d610e158cc 100644 --- a/gcc/testsuite/gcc.target/powerpc/vec-init-6.c +++ b/gcc/testsuite/gcc.target/powerpc/vec-init-6.c @@ -1,7 +1,7 @@ /* { dg-do compile { target { powerpc64*-*-* && lp64 } } } */ /* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power8" } } */ /* { dg-require-effective-target powerpc_p8vector_ok } */ -/* { dg-options "-mcpu=power8 -O2 -mupper-regs-di" } */ +/* { dg-options "-mcpu=power8 -O2" } */ vector int merge (int a, int b, int c, int d) diff --git a/gcc/testsuite/gcc.target/powerpc/vec-init-7.c b/gcc/testsuite/gcc.target/powerpc/vec-init-7.c index b5e531ea7f1..c44fa9b2a3d 100644 --- a/gcc/testsuite/gcc.target/powerpc/vec-init-7.c +++ b/gcc/testsuite/gcc.target/powerpc/vec-init-7.c @@ -1,7 +1,7 @@ /* { dg-do compile { target { powerpc64*-*-* && lp64 } } } */ /* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power8" } } */ /* { dg-require-effective-target powerpc_p8vector_ok } */ -/* { dg-options "-mcpu=power8 -O2 -mupper-regs-di" } */ +/* { dg-options "-mcpu=power8 -O2" } */ vector int splat (int a) diff --git a/gcc/testsuite/gcc.target/powerpc/vec-set-char.c b/gcc/testsuite/gcc.target/powerpc/vec-set-char.c index 2da79ef9e9d..5df260ded29 100644 --- a/gcc/testsuite/gcc.target/powerpc/vec-set-char.c +++ b/gcc/testsuite/gcc.target/powerpc/vec-set-char.c @@ -3,7 +3,7 @@ /* { dg-do compile { target { powerpc64*-*-* && lp64 } } } */ /* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ /* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-mcpu=power9 -O2 -mupper-regs-di -mvsx-small-integer" } */ +/* { dg-options "-mcpu=power9 -O2" } */ vector char insert_0_0 (vector char v) diff --git a/gcc/testsuite/gcc.target/powerpc/vec-set-int.c b/gcc/testsuite/gcc.target/powerpc/vec-set-int.c index dc97ac9d4d3..deaa6acfa6e 100644 --- a/gcc/testsuite/gcc.target/powerpc/vec-set-int.c +++ b/gcc/testsuite/gcc.target/powerpc/vec-set-int.c @@ -3,7 +3,7 @@ /* { dg-do compile { target { powerpc64*-*-* && lp64 } } } */ /* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ /* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-mcpu=power9 -O2 -mupper-regs-di -mvsx-small-integer" } */ +/* { dg-options "-mcpu=power9 -O2" } */ vector int insert_0_0 (vector int v) diff --git a/gcc/testsuite/gcc.target/powerpc/vec-set-short.c b/gcc/testsuite/gcc.target/powerpc/vec-set-short.c index d82760955fd..eabcf3488de 100644 --- a/gcc/testsuite/gcc.target/powerpc/vec-set-short.c +++ b/gcc/testsuite/gcc.target/powerpc/vec-set-short.c @@ -3,7 +3,7 @@ /* { dg-do compile { target { powerpc64*-*-* && lp64 } } } */ /* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ /* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-mcpu=power9 -O2 -mupper-regs-di -mvsx-small-integer" } */ +/* { dg-options "-mcpu=power9 -O2" } */ vector short insert_0_0 (vector short v) diff --git a/gcc/testsuite/gcc.target/powerpc/vsx-himode.c b/gcc/testsuite/gcc.target/powerpc/vsx-himode.c index 8f710e5c5bd..2a4e610de72 100644 --- a/gcc/testsuite/gcc.target/powerpc/vsx-himode.c +++ b/gcc/testsuite/gcc.target/powerpc/vsx-himode.c @@ -2,7 +2,7 @@ /* { dg-skip-if "" { powerpc*-*-darwin* } } */ /* { dg-require-effective-target powerpc_p9vector_ok } */ /* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ -/* { dg-options "-mcpu=power9 -O2 -mvsx-small-integer" } */ +/* { dg-options "-mcpu=power9 -O2" } */ double load_asm_d_constraint (short *p) { diff --git a/gcc/testsuite/gcc.target/powerpc/vsx-himode2.c b/gcc/testsuite/gcc.target/powerpc/vsx-himode2.c index e6f26a8e014..6ee08cf109a 100644 --- a/gcc/testsuite/gcc.target/powerpc/vsx-himode2.c +++ b/gcc/testsuite/gcc.target/powerpc/vsx-himode2.c @@ -2,7 +2,7 @@ /* { dg-skip-if "" { powerpc*-*-darwin* } } */ /* { dg-require-effective-target powerpc_p9vector_ok } */ /* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ -/* { dg-options "-mcpu=power9 -O2 -mvsx-small-integer" } */ +/* { dg-options "-mcpu=power9 -O2" } */ unsigned int foo (unsigned short u) { diff --git a/gcc/testsuite/gcc.target/powerpc/vsx-himode3.c b/gcc/testsuite/gcc.target/powerpc/vsx-himode3.c index 3c0e66d14ca..972be677dd6 100644 --- a/gcc/testsuite/gcc.target/powerpc/vsx-himode3.c +++ b/gcc/testsuite/gcc.target/powerpc/vsx-himode3.c @@ -2,7 +2,7 @@ /* { dg-skip-if "" { powerpc*-*-darwin* } } */ /* { dg-require-effective-target powerpc_p9vector_ok } */ /* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ -/* { dg-options "-mcpu=power9 -O2 -mvsx-small-integer" } */ +/* { dg-options "-mcpu=power9 -O2" } */ double load_asm_v_constraint (short *p) { diff --git a/gcc/testsuite/gcc.target/powerpc/vsx-qimode.c b/gcc/testsuite/gcc.target/powerpc/vsx-qimode.c index a252457f314..1c224cb1b61 100644 --- a/gcc/testsuite/gcc.target/powerpc/vsx-qimode.c +++ b/gcc/testsuite/gcc.target/powerpc/vsx-qimode.c @@ -2,7 +2,7 @@ /* { dg-skip-if "" { powerpc*-*-darwin* } } */ /* { dg-require-effective-target powerpc_p9vector_ok } */ /* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ -/* { dg-options "-mcpu=power9 -O2 -mvsx-small-integer" } */ +/* { dg-options "-mcpu=power9 -O2" } */ double load_asm_d_constraint (signed char *p) { diff --git a/gcc/testsuite/gcc.target/powerpc/vsx-qimode2.c b/gcc/testsuite/gcc.target/powerpc/vsx-qimode2.c index d321970d0ac..478c9da3051 100644 --- a/gcc/testsuite/gcc.target/powerpc/vsx-qimode2.c +++ b/gcc/testsuite/gcc.target/powerpc/vsx-qimode2.c @@ -2,7 +2,7 @@ /* { dg-skip-if "" { powerpc*-*-darwin* } } */ /* { dg-require-effective-target powerpc_p9vector_ok } */ /* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ -/* { dg-options "-mcpu=power9 -O2 -mvsx-small-integer" } */ +/* { dg-options "-mcpu=power9 -O2" } */ unsigned int foo (unsigned char u) { diff --git a/gcc/testsuite/gcc.target/powerpc/vsx-qimode3.c b/gcc/testsuite/gcc.target/powerpc/vsx-qimode3.c index 50142e8d86d..6537d8b80a0 100644 --- a/gcc/testsuite/gcc.target/powerpc/vsx-qimode3.c +++ b/gcc/testsuite/gcc.target/powerpc/vsx-qimode3.c @@ -2,7 +2,7 @@ /* { dg-skip-if "" { powerpc*-*-darwin* } } */ /* { dg-require-effective-target powerpc_p9vector_ok } */ /* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ -/* { dg-options "-mcpu=power9 -O2 -mvsx-small-integer" } */ +/* { dg-options "-mcpu=power9 -O2" } */ double load_asm_v_constraint (signed char *p) { diff --git a/gcc/testsuite/gcc.target/powerpc/vsx-simode.c b/gcc/testsuite/gcc.target/powerpc/vsx-simode.c index 91d55bb8791..77049008845 100644 --- a/gcc/testsuite/gcc.target/powerpc/vsx-simode.c +++ b/gcc/testsuite/gcc.target/powerpc/vsx-simode.c @@ -2,7 +2,7 @@ /* { dg-skip-if "" { powerpc*-*-darwin* } } */ /* { dg-require-effective-target powerpc_p8vector_ok } */ /* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power8" } } */ -/* { dg-options "-mcpu=power8 -O2 -mvsx-small-integer" } */ +/* { dg-options "-mcpu=power8 -O2" } */ double load_asm_d_constraint (int *p) { diff --git a/gcc/testsuite/gcc.target/powerpc/vsx-simode2.c b/gcc/testsuite/gcc.target/powerpc/vsx-simode2.c index 56793a16222..92053d9ac35 100644 --- a/gcc/testsuite/gcc.target/powerpc/vsx-simode2.c +++ b/gcc/testsuite/gcc.target/powerpc/vsx-simode2.c @@ -2,7 +2,7 @@ /* { dg-skip-if "" { powerpc*-*-darwin* } } */ /* { dg-require-effective-target powerpc_p8vector_ok } */ /* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power8" } } */ -/* { dg-options "-mcpu=power8 -O2 -mvsx-small-integer" } */ +/* { dg-options "-mcpu=power8 -O2" } */ unsigned int foo (unsigned int u) { diff --git a/gcc/testsuite/gcc.target/powerpc/vsx-simode3.c b/gcc/testsuite/gcc.target/powerpc/vsx-simode3.c index a35e6db0b79..62f5ab46c04 100644 --- a/gcc/testsuite/gcc.target/powerpc/vsx-simode3.c +++ b/gcc/testsuite/gcc.target/powerpc/vsx-simode3.c @@ -2,7 +2,7 @@ /* { dg-skip-if "" { powerpc*-*-darwin* } } */ /* { dg-require-effective-target powerpc_p8vector_ok } */ /* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power8" } } */ -/* { dg-options "-mcpu=power8 -O2 -mvsx-small-integer" } */ +/* { dg-options "-mcpu=power8 -O2" } */ double load_asm_v_constraint (int *p) { |