10 files changed, 98 insertions, 5 deletions
diff --git a/gcc/testsuite/gcc.target/powerpc/bswap-brw.c b/gcc/testsuite/gcc.target/powerpc/bswap-brw.c
index b3f923eea84..0ed2a7bd1d2 100644
--- a/gcc/testsuite/gcc.target/powerpc/bswap-brw.c
+++ b/gcc/testsuite/gcc.target/powerpc/bswap-brw.c
@@ -17,6 +17,6 @@ bswap_int_dbl (unsigned int a)
   /* Force the value to be loaded into a vector register.  */
   __asm__ (" # %x0" : "+wa" (b));
 
-  /* { dg-final { scan-assembler {\mxxbrw\M} } } */
+  /* { dg-final { scan-assembler {\mxxbrw\M} {xfail {has_arch_pwr10 && {! has_arch_ppc64}}} } } */
   return (double) __builtin_bswap32 (b);
 }
diff --git a/gcc/testsuite/gcc.target/powerpc/p9-vec-length-epil-7.c b/gcc/testsuite/gcc.target/powerpc/p9-vec-length-epil-7.c
index a27ee347ca1..011b731f7c5 100644
--- a/gcc/testsuite/gcc.target/powerpc/p9-vec-length-epil-7.c
+++ b/gcc/testsuite/gcc.target/powerpc/p9-vec-length-epil-7.c
@@ -1,5 +1,7 @@
 /* { dg-do compile { target { lp64 && powerpc_p9vector_ok } } } */
-/* { dg-options "-mdejagnu-cpu=power9 -O2 -ftree-vectorize -fno-vect-cost-model -fno-unroll-loops -ffast-math" } */
+/* Pass cunroll isn't disabled by -fno-unroll-loops, so use explicit
+   disabling option for it.  */
+/* { dg-options "-mdejagnu-cpu=power9 -O2 -ftree-vectorize -fno-vect-cost-model -fno-unroll-loops -ffast-math -fdisable-tree-cunroll" } */
 
 /* { dg-additional-options "--param=vect-partial-vector-usage=1" } */
 
diff --git a/gcc/testsuite/gcc.target/powerpc/p9-vec-length-full-7.c b/gcc/testsuite/gcc.target/powerpc/p9-vec-length-full-7.c
index 89ff38443e7..e0e51d9a972 100644
--- a/gcc/testsuite/gcc.target/powerpc/p9-vec-length-full-7.c
+++ b/gcc/testsuite/gcc.target/powerpc/p9-vec-length-full-7.c
@@ -1,5 +1,7 @@
 /* { dg-do compile { target { lp64 && powerpc_p9vector_ok } } } */
-/* { dg-options "-mdejagnu-cpu=power9 -O2 -ftree-vectorize -fno-vect-cost-model -fno-unroll-loops -ffast-math" } */
+/* Pass cunroll isn't disabled by -fno-unroll-loops, so use explicit
+   disabling option for it.  */
+/* { dg-options "-mdejagnu-cpu=power9 -O2 -ftree-vectorize -fno-vect-cost-model -fno-unroll-loops -ffast-math -fdisable-tree-cunroll" } */
 
 /* { dg-additional-options "--param=vect-partial-vector-usage=2" } */
 
diff --git a/gcc/testsuite/gcc.target/powerpc/pr104253.c b/gcc/testsuite/gcc.target/powerpc/pr104253.c
index 02049cc978f..e5f9499b7c8 100644
--- a/gcc/testsuite/gcc.target/powerpc/pr104253.c
+++ b/gcc/testsuite/gcc.target/powerpc/pr104253.c
@@ -6,8 +6,9 @@
  */
 
 /* { dg-do run } */
-/* { require-effective-target ppc_float128_sw } */
+/* { dg-require-effective-target ppc_float128_sw } */
 /* { dg-options "-O2 -mvsx -mfloat128" } */
+/* { dg-prune-output ".-mfloat128. option may not be fully supported" } */
 
 /*
  * PR target/104253
diff --git a/gcc/testsuite/gcc.target/powerpc/pr104894-2.c b/gcc/testsuite/gcc.target/powerpc/pr104894-2.c
new file mode 100644
index 00000000000..d1a011ef4d9
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/pr104894-2.c
@@ -0,0 +1,22 @@
+/* PR target/104894 */
+/* { dg-require-effective-target powerpc_elfv2 } */
+/* { dg-require-effective-target power10_ok } */
+/* { dg-options "-O2 -mdejagnu-cpu=power10 -fno-plt" } */
+
+/* Verify we do not ICE on the following test case and that we emit one
+   indirect call and one indirect sibcall, with r12 and CTR containing
+   the function addresses.  */
+
+void foo (void);
+
+void
+bar (void)
+{
+  foo ();
+  foo ();
+}
+
+/* { dg-final { scan-assembler-times {\mmtctr 12\M} 2 } } */
+/* { dg-final { scan-assembler-times {\mbctrl\M} 1 } } */
+/* { dg-final { scan-assembler-times {\mbctr\M} 1 } } */
+/* { dg-final { scan-assembler-not {\mbl\M} } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/pr104894.c b/gcc/testsuite/gcc.target/powerpc/pr104894.c
new file mode 100644
index 00000000000..f46fe88168f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/pr104894.c
@@ -0,0 +1,20 @@
+/* PR target/104894 */
+/* { dg-require-effective-target powerpc_elfv2 } */
+/* { dg-require-effective-target power10_ok } */
+/* { dg-options "-O2 -mdejagnu-cpu=power10 -fno-plt" } */
+
+/* Verify we do not ICE on the following test case and that we emit an
+   indirect sibcall, with r12 and CTR containing the function address.  */
+
+void foo (void);
+
+void
+bar (void)
+{
+  foo ();
+}
+
+/* { dg-final { scan-assembler-times {\mmtctr 12\M} 1 } } */
+/* { dg-final { scan-assembler-times {\mbctr\M} 1 } } */
+/* { dg-final { scan-assembler-not {\mbl\M} } } */
+/* { dg-final { scan-assembler-not {\mbctrl\M} } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/pr105271.c b/gcc/testsuite/gcc.target/powerpc/pr105271.c
new file mode 100644
index 00000000000..1c5f88cadcf
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/pr105271.c
@@ -0,0 +1,14 @@
+/* { dg-require-effective-target powerpc_vsx_ok } */
+/* { dg-options "-mdejagnu-cpu=power7" } */
+
+/* It's to verify no ICE here, ignore error messages about
+   the required options for vec_neg here.  */
+/* { dg-excess-errors "pr105271" } */
+
+#include <altivec.h>
+
+vector signed long long
+test (vector signed long long x)
+{
+  return vec_neg (x);
+}
diff --git a/gcc/testsuite/gcc.target/powerpc/pr105334.c b/gcc/testsuite/gcc.target/powerpc/pr105334.c
new file mode 100644
index 00000000000..7664e033dd0
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/pr105334.c
@@ -0,0 +1,31 @@
+/* Skip this on aix, since it takes soft-float and long-double-128
+   incompatible and warns it.  */
+/* { dg-skip-if "aix long-double-128 soft-float" { powerpc*-*-aix* } } */
+/* { dg-options "-mlong-double-128 -msoft-float" } */
+
+/* Verify there is no ICE.  */
+
+#include <stddef.h>
+#include <stdlib.h>
+#include <math.h>
+
+#define PACK __builtin_pack_ibm128
+#define UNPACK __builtin_unpack_ibm128
+#define LDOUBLE __ibm128
+
+extern LDOUBLE bar (LDOUBLE);
+
+int
+main (void)
+{
+  double high = pow (2.0, 60);
+  double low = 2.0;
+  LDOUBLE a = ((LDOUBLE) high) + ((LDOUBLE) low);
+  double x0 = UNPACK (a, 0);
+  double x1 = UNPACK (a, 1);
+  LDOUBLE b = PACK (x0, x1);
+  LDOUBLE c = bar (b);
+
+  return c > a;
+}
+
diff --git a/gcc/testsuite/gcc.target/powerpc/pr56605.c b/gcc/testsuite/gcc.target/powerpc/pr56605.c
index fdedbfc573d..7695f87db6f 100644
--- a/gcc/testsuite/gcc.target/powerpc/pr56605.c
+++ b/gcc/testsuite/gcc.target/powerpc/pr56605.c
@@ -11,5 +11,5 @@ void foo (short* __restrict sb, int* __restrict ia)
     ia[i] = (int) sb[i];
 }
 
-/* { dg-final { scan-rtl-dump-times {\(compare:CC \((?:and|zero_extend):(?:DI) \((?:sub)?reg:[SD]I} 1 "combine" } } */
+/* { dg-final { scan-rtl-dump-times {\(compare:CC \((?:and|zero_extend):(?:[SD]I) \((?:sub)?reg:[SD]I} 1 "combine" } } */
 
diff --git a/gcc/testsuite/gcc.target/powerpc/pr60203.c b/gcc/testsuite/gcc.target/powerpc/pr60203.c
index 7ada64a32db..a5a574a8837 100644
--- a/gcc/testsuite/gcc.target/powerpc/pr60203.c
+++ b/gcc/testsuite/gcc.target/powerpc/pr60203.c
@@ -1,5 +1,6 @@
 /* { dg-do compile { target { powerpc*-*-* && lp64 } } } */
 /* { dg-skip-if "" { powerpc*-*-darwin* } } */
+/* { dg-require-effective-target longdouble128 } */
 /* { dg-require-effective-target powerpc_p8vector_ok } */
 /* { dg-options "-mdejagnu-cpu=power8 -O3" } */