diff options
Diffstat (limited to 'gcc/testsuite/gcc.target/mips')
24 files changed, 429 insertions, 1 deletions
diff --git a/gcc/testsuite/gcc.target/mips/mips.exp b/gcc/testsuite/gcc.target/mips/mips.exp index ad32fb67713..15b1386bd9e 100644 --- a/gcc/testsuite/gcc.target/mips/mips.exp +++ b/gcc/testsuite/gcc.target/mips/mips.exp @@ -238,6 +238,7 @@ set mips_option_groups { fp "-mfp(32|64)" gp "-mgp(32|64)" long "-mlong(32|64)" + micromips "-mmicromips|-mno-micromips" mips16 "-mips16|-mno-mips16|-mflip-mips16" mips3d "-mips3d|-mno-mips3d" pic "-f(no-|)(pic|PIC)" @@ -816,6 +817,8 @@ proc mips-dg-finish {} { # | | # -mips16/-mflip-mips16 -mno-mips16 # | | +# -micromips -mno-micromips +# | | # -mips3d -mno-mips3d # | | # -mpaired-single -mno-paired-single @@ -904,6 +907,8 @@ proc mips-dg-options { args } { # Handle dependencies between options on the left of the # dependency diagram. + mips_option_dependency options "-mips16" "-mno-micromips" + mips_option_dependency options "-mmicromips" "-mno-mips16" mips_option_dependency options "-mips3d" "-mpaired-single" mips_option_dependency options "-mpaired-single" "-mfp64" mips_option_dependency options "-mfp64" "-mhard-float" @@ -1246,6 +1251,10 @@ proc mips-dg-options { args } { append extra_tool_flags " -DMIPS16=__attribute__((mips16))" } + if { [mips_have_test_option_p options "-mmicromips"] } { + append extra_tool_flags " -DMICROMIPS=__attribute__((micromips))" + } + # Use our version of gcc-dg-test for this test. if { ![string equal [info procs "mips-gcc-dg-test"] ""] } { rename gcc-dg-test mips-old-gcc-dg-test @@ -1275,6 +1284,6 @@ proc mips-gcc-dg-test { prog do_what extra_tool_flags } { dg-init mips-dg-init gcc-dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/*.c]] \ - "-DNOMIPS16=__attribute__((nomips16))" + "-DNOMIPS16=__attribute__((nomips16)) -DNOMICROMIPS=__attribute__((nomicromips)) -DNOCOMPRESSION=__attribute__((nocompression))" mips-dg-finish dg-finish diff --git a/gcc/testsuite/gcc.target/mips/umips-constraints-1.c b/gcc/testsuite/gcc.target/mips/umips-constraints-1.c index e69de29bb2d..ddec815b0f3 100644 --- a/gcc/testsuite/gcc.target/mips/umips-constraints-1.c +++ b/gcc/testsuite/gcc.target/mips/umips-constraints-1.c @@ -0,0 +1,14 @@ +/* { dg-options "(-mmicromips)" } */ +/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */ + +MICROMIPS void +foo (int *x) +{ + asm volatile ("insn1\t%a0" :: "ZD" (&x[0])); + asm volatile ("insn2\t%a0" :: "ZD" (&x[511])); + asm volatile ("insn3\t%a0" :: "ZD" (&x[512])); +} + +/* { dg-final { scan-assembler "\tinsn1\t0\\(" } } */ +/* { dg-final { scan-assembler "\tinsn2\t2044\\(" } } */ +/* { dg-final { scan-assembler-not "\tinsn3\t2048\\(" } } */ diff --git a/gcc/testsuite/gcc.target/mips/umips-constraints-2.c b/gcc/testsuite/gcc.target/mips/umips-constraints-2.c index e69de29bb2d..0240d467026 100644 --- a/gcc/testsuite/gcc.target/mips/umips-constraints-2.c +++ b/gcc/testsuite/gcc.target/mips/umips-constraints-2.c @@ -0,0 +1,14 @@ +/* { dg-options "(-mmicromips)" } */ +/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */ + +MICROMIPS void +foo (int *x) +{ + asm volatile ("insn1\t%0" :: "ZC" (x[0])); + asm volatile ("insn2\t%0" :: "ZC" (x[511])); + asm volatile ("insn3\t%0" :: "ZC" (x[512])); +} + +/* { dg-final { scan-assembler "\tinsn1\t0\\(" } } */ +/* { dg-final { scan-assembler "\tinsn2\t2044\\(" } } */ +/* { dg-final { scan-assembler-not "\tinsn3\t2048\\(" } } */ diff --git a/gcc/testsuite/gcc.target/mips/umips-lwp-1.c b/gcc/testsuite/gcc.target/mips/umips-lwp-1.c index e69de29bb2d..0cdb1b7f2bc 100644 --- a/gcc/testsuite/gcc.target/mips/umips-lwp-1.c +++ b/gcc/testsuite/gcc.target/mips/umips-lwp-1.c @@ -0,0 +1,17 @@ +/* { dg-options "-mgp32 -fpeephole2 -mtune=m14k (-mmicromips)" } */ +/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */ + +void MICROMIPS +foo (int *r4) +{ + int r5 = r4[0]; + int r6 = r4[1]; + r4[2] = r5 * r5; + { + register int r5asm asm ("$5") = r5; + register int r6asm asm ("$6") = r6; + asm ("#foo" : "=m" (r4[3]) : "d" (r5asm), "d" (r6asm)); + } +} + +/* { dg-final { scan-assembler "\tlwp\t\\\$5,0\\(\\\$4\\)" } }*/ diff --git a/gcc/testsuite/gcc.target/mips/umips-lwp-2.c b/gcc/testsuite/gcc.target/mips/umips-lwp-2.c index e69de29bb2d..ea3f3960742 100644 --- a/gcc/testsuite/gcc.target/mips/umips-lwp-2.c +++ b/gcc/testsuite/gcc.target/mips/umips-lwp-2.c @@ -0,0 +1,17 @@ +/* { dg-options "-mgp32 -fpeephole2 -mtune=m14k (-mmicromips)" } */ +/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */ + +void MICROMIPS +foo (int *r4) +{ + int r5 = r4[0]; + int r6 = r4[1]; + r4[2] = r6 * r6; + { + register int r5asm asm ("$5") = r5; + register int r6asm asm ("$6") = r6; + asm ("#foo" : "=m" (r4[3]) : "d" (r5asm), "d" (r6asm)); + } +} + +/* { dg-final { scan-assembler "\tlwp\t\\\$5,0\\(\\\$4\\)" } }*/ diff --git a/gcc/testsuite/gcc.target/mips/umips-lwp-3.c b/gcc/testsuite/gcc.target/mips/umips-lwp-3.c index e69de29bb2d..2cb37510feb 100644 --- a/gcc/testsuite/gcc.target/mips/umips-lwp-3.c +++ b/gcc/testsuite/gcc.target/mips/umips-lwp-3.c @@ -0,0 +1,17 @@ +/* { dg-options "-mgp32 -fpeephole2 -mtune=m14k (-mmicromips)" } */ +/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */ + +void MICROMIPS +foo (int *r4) +{ + int r5 = r4[511]; + int r6 = r4[512]; + r4[2] = r5 * r5; + { + register int r5asm asm ("$5") = r5; + register int r6asm asm ("$6") = r6; + asm ("#foo" : "=m" (r4[3]) : "d" (r5asm), "d" (r6asm)); + } +} + +/* { dg-final { scan-assembler "\tlwp\t\\\$5,2044\\(\\\$4\\)" } }*/ diff --git a/gcc/testsuite/gcc.target/mips/umips-lwp-4.c b/gcc/testsuite/gcc.target/mips/umips-lwp-4.c index e69de29bb2d..b8a86b4ed90 100644 --- a/gcc/testsuite/gcc.target/mips/umips-lwp-4.c +++ b/gcc/testsuite/gcc.target/mips/umips-lwp-4.c @@ -0,0 +1,17 @@ +/* { dg-options "-mgp32 -fpeephole2 -mtune=m14k (-mmicromips)" } */ +/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */ + +void MICROMIPS +foo (int *r4) +{ + int r5 = r4[511]; + int r6 = r4[512]; + r4[2] = r6 * r6; + { + register int r5asm asm ("$5") = r5; + register int r6asm asm ("$6") = r6; + asm ("#foo" : "=m" (r4[3]) : "d" (r5asm), "d" (r6asm)); + } +} + +/* { dg-final { scan-assembler "\tlwp\t\\\$5,2044\\(\\\$4\\)" } }*/ diff --git a/gcc/testsuite/gcc.target/mips/umips-lwp-5.c b/gcc/testsuite/gcc.target/mips/umips-lwp-5.c index e69de29bb2d..2315f21e91e 100644 --- a/gcc/testsuite/gcc.target/mips/umips-lwp-5.c +++ b/gcc/testsuite/gcc.target/mips/umips-lwp-5.c @@ -0,0 +1,17 @@ +/* { dg-options "-mgp32 -fpeephole2 -mtune=m14k (-mmicromips)" } */ +/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */ + +void MICROMIPS +foo (int *r4) +{ + int r5 = r4[512]; + int r6 = r4[513]; + r4[2] = r5 * r5; + { + register int r5asm asm ("$5") = r5; + register int r6asm asm ("$6") = r6; + asm ("#foo" : "=m" (r4[3]) : "d" (r5asm), "d" (r6asm)); + } +} + +/* { dg-final { scan-assembler-not "\tlwp" } }*/ diff --git a/gcc/testsuite/gcc.target/mips/umips-lwp-6.c b/gcc/testsuite/gcc.target/mips/umips-lwp-6.c index e69de29bb2d..9534974de8f 100644 --- a/gcc/testsuite/gcc.target/mips/umips-lwp-6.c +++ b/gcc/testsuite/gcc.target/mips/umips-lwp-6.c @@ -0,0 +1,17 @@ +/* { dg-options "-mgp32 -fpeephole2 -mtune=m14k (-mmicromips)" } */ +/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */ + +void MICROMIPS +foo (int *r4) +{ + int r5 = r4[512]; + int r6 = r4[513]; + r4[2] = r6 * r6; + { + register int r5asm asm ("$5") = r5; + register int r6asm asm ("$6") = r6; + asm ("#foo" : "=m" (r4[3]) : "d" (r5asm), "d" (r6asm)); + } +} + +/* { dg-final { scan-assembler-not "\tlwp" } }*/ diff --git a/gcc/testsuite/gcc.target/mips/umips-lwp-7.c b/gcc/testsuite/gcc.target/mips/umips-lwp-7.c index e69de29bb2d..87ff6dc1154 100644 --- a/gcc/testsuite/gcc.target/mips/umips-lwp-7.c +++ b/gcc/testsuite/gcc.target/mips/umips-lwp-7.c @@ -0,0 +1,41 @@ +/* { dg-options "-mgp32 -fpeephole2 -mtune=m14k (-mmicromips)" } */ +/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */ + +void MICROMIPS +f1 (int *r4, int dummy, int *other) +{ + int r5 = r4[1]; + int newr4 = r4[0]; + other[0] = r5 * r5; + { + register int r5asm asm ("$5") = r5; + register int r4asm asm ("$4") = newr4; + asm ("#foo" : "=m" (other[1]) : "d" (r4asm), "d" (r5asm)); + } +} + +void MICROMIPS +f2 (int *r4, int dummy, int *other) +{ + int newr4 = r4[0]; + int r5 = *(int *)(newr4 + 4); + { + register int r5asm asm ("$5") = r5; + register int r4asm asm ("$4") = newr4; + asm ("#foo" : "=m" (other[0]) : "d" (r4asm), "d" (r5asm)); + } +} + +void MICROMIPS +f3 (int dummy, int *r5, int *other) +{ + int newr5 = r5[1]; + int r4 = *(int *)newr5; + { + register int r5asm asm ("$4") = r4; + register int r4asm asm ("$5") = newr5; + asm ("#foo" : "=m" (other[0]) : "d" (r4asm), "d" (r5asm)); + } +} + +/* { dg-final { scan-assembler-not "\tlwp" } }*/ diff --git a/gcc/testsuite/gcc.target/mips/umips-lwp-8.c b/gcc/testsuite/gcc.target/mips/umips-lwp-8.c index e69de29bb2d..43b98423dfd 100644 --- a/gcc/testsuite/gcc.target/mips/umips-lwp-8.c +++ b/gcc/testsuite/gcc.target/mips/umips-lwp-8.c @@ -0,0 +1,17 @@ +/* { dg-options "-mgp32 -fpeephole2 -mtune=m14k (-mmicromips)" } */ +/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */ + +void MICROMIPS +f1 (int dummy, int *r5, int *other) +{ + int r4 = r5[0]; + int newr5 = r5[1]; + other[0] = r4 * r4; + { + register int r5asm asm ("$4") = r4; + register int r4asm asm ("$5") = newr5; + asm ("#foo" : "=m" (other[1]) : "d" (r4asm), "d" (r5asm)); + } +} + +/* { dg-final { scan-assembler "\tlwp\t\\\$4,0\\(\\\$5\\)" } }*/ diff --git a/gcc/testsuite/gcc.target/mips/umips-lwp-swp-volatile.c b/gcc/testsuite/gcc.target/mips/umips-lwp-swp-volatile.c index e69de29bb2d..da2cbaff38b 100644 --- a/gcc/testsuite/gcc.target/mips/umips-lwp-swp-volatile.c +++ b/gcc/testsuite/gcc.target/mips/umips-lwp-swp-volatile.c @@ -0,0 +1,42 @@ +/* { dg-do compile } */ +/* { dg-options "-mmicromips" } */ + +/* This test ensures that we do not generate microMIPS SWP or LWP + instructions when any component of the accessed memory is volatile; + they are unsafe for such since they might cause replay of partial + accesses if interrupted by an exception. */ + +static void set_csr (volatile void *p, int v) +{ + *(volatile int *) (p) = v; +} + +static int get_csr (volatile void *p) +{ + return *(volatile int *) (p); +} + +int main () +{ + int i, q = 0, p = 0, r = 0; + + for (i = 0; i < 20; i++) + { + set_csr ((volatile void *) 0xbf0100a8, 0xffff0002); + set_csr ((volatile void *) 0xbf0100a4, 0x80000008); + } + + for (i = 0; i < 20; i++) + { + register int k, j; + k = get_csr ((volatile void *) 0xbf0100b8); + p += k; + j = get_csr ((volatile void *) 0xbf0100b4); + r += j; + q = j + k; + } + return q + r + p; +} + +/* { dg-final { scan-assembler-not "\tswp" } } */ +/* { dg-final { scan-assembler-not "\tlwp" } } */ diff --git a/gcc/testsuite/gcc.target/mips/umips-movep-1.c b/gcc/testsuite/gcc.target/mips/umips-movep-1.c index e69de29bb2d..0865b78bd8c 100644 --- a/gcc/testsuite/gcc.target/mips/umips-movep-1.c +++ b/gcc/testsuite/gcc.target/mips/umips-movep-1.c @@ -0,0 +1,16 @@ +/* Check that we can generate the MOVEP instruction. */ +/* { dg-options "-mgp32 -fpeephole2 (-mmicromips)" } */ +/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */ + +long long bar (long long, long long); + +MICROMIPS long long +foo (long long n, long long a) +{ + long long i, j; + + i = bar (n, a); + j = bar (n, a); + return i + j; +} +/* { dg-final { scan-assembler "\tmovep\t" } } */ diff --git a/gcc/testsuite/gcc.target/mips/umips-movep-2.c b/gcc/testsuite/gcc.target/mips/umips-movep-2.c index e69de29bb2d..5a3a8419eee 100644 --- a/gcc/testsuite/gcc.target/mips/umips-movep-2.c +++ b/gcc/testsuite/gcc.target/mips/umips-movep-2.c @@ -0,0 +1,13 @@ +/* Check that we can generate the MOVEP instruction. */ +/* { dg-options "-fpeephole2 -mgp32 (-mmicromips)" } */ +/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */ + +int bar (int, int); + +int MICROMIPS +foo (int n, int a) +{ + return bar (0, 0); +} + +/* { dg-final { scan-assembler "\tmovep\t\\\$4,\\\$5,\\\$0,\\\$0" } } */ diff --git a/gcc/testsuite/gcc.target/mips/umips-save-restore-1.c b/gcc/testsuite/gcc.target/mips/umips-save-restore-1.c index e69de29bb2d..ff1ea4b339a 100644 --- a/gcc/testsuite/gcc.target/mips/umips-save-restore-1.c +++ b/gcc/testsuite/gcc.target/mips/umips-save-restore-1.c @@ -0,0 +1,18 @@ +/* Check that we can use the swm/lwm instructions. */ +/* { dg-options "-mabi=32 (-mmicromips)" } */ +/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */ + +int bar (int, int, int, int, int); + +MICROMIPS int +foo (int n, int a, int b, int c, int d) +{ + int i, j; + + i = bar (n, a, b, c, d); + j = bar (n, a, b, c, d); + return i + j; +} + +/* { dg-final { scan-assembler "\tswm\t\\\$16-\\\$2(0|1),\\\$31" } } */ +/* { dg-final { scan-assembler "\tlwm\t\\\$16-\\\$2(0|1),\\\$31" } } */ diff --git a/gcc/testsuite/gcc.target/mips/umips-save-restore-2.c b/gcc/testsuite/gcc.target/mips/umips-save-restore-2.c index e69de29bb2d..cb421d5d4be 100644 --- a/gcc/testsuite/gcc.target/mips/umips-save-restore-2.c +++ b/gcc/testsuite/gcc.target/mips/umips-save-restore-2.c @@ -0,0 +1,16 @@ +/* Check that we can use the save instruction to save spilled arguments. */ +/* { dg-options "-mabi=32 (-mmicromips)" } */ +/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */ + +MICROMIPS void +foo (int *a, int b, int c) +{ + asm volatile ("" ::: "$2", "$3", "$4", "$5", "$6", "$7", "$8", + "$9", "$10", "$11", "$12", "$13", "$14", "$15", "$16", + "$17", "$18", "$19", "$20", "$21", "$22", "$23", "$24", + "$25", "$30", "memory"); + a[b] = 1; + a[c] = 1; +} +/* { dg-final { scan-assembler "\tswm\t\\\$16-\\\$23,\\\$fp" } } */ +/* { dg-final { scan-assembler "\tlwm\t\\\$16-\\\$23,\\\$fp" } } */ diff --git a/gcc/testsuite/gcc.target/mips/umips-save-restore-3.c b/gcc/testsuite/gcc.target/mips/umips-save-restore-3.c index e69de29bb2d..22c6f45f717 100644 --- a/gcc/testsuite/gcc.target/mips/umips-save-restore-3.c +++ b/gcc/testsuite/gcc.target/mips/umips-save-restore-3.c @@ -0,0 +1,14 @@ +/* Check that we can use the swm instruction to save $16, $17 and $31. */ +/* { dg-options "-mgp32 (-mmicromips)" } */ +/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */ + +void bar (void); + +MICROMIPS void +foo (void) +{ + bar (); + asm volatile ("" ::: "$16", "$17"); +} +/* { dg-final { scan-assembler "\tswm\t\\\$16-\\\$17,\\\$31" } } */ +/* { dg-final { scan-assembler "\tlwm\t\\\$16-\\\$17,\\\$31" } } */ diff --git a/gcc/testsuite/gcc.target/mips/umips-swp-1.c b/gcc/testsuite/gcc.target/mips/umips-swp-1.c index e69de29bb2d..5e337b27b6c 100644 --- a/gcc/testsuite/gcc.target/mips/umips-swp-1.c +++ b/gcc/testsuite/gcc.target/mips/umips-swp-1.c @@ -0,0 +1,10 @@ +/* { dg-options "-fpeephole2 -mgp32 (-mmicromips)" } */ +/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */ + +void MICROMIPS +foo (long long l1, long long *l2) +{ + *l2 = l1; +} + +/* { dg-final { scan-assembler "\tswp\t\\\$4,0\\(\\\$6\\)" } }*/ diff --git a/gcc/testsuite/gcc.target/mips/umips-swp-2.c b/gcc/testsuite/gcc.target/mips/umips-swp-2.c index e69de29bb2d..042322c2175 100644 --- a/gcc/testsuite/gcc.target/mips/umips-swp-2.c +++ b/gcc/testsuite/gcc.target/mips/umips-swp-2.c @@ -0,0 +1,17 @@ +/* { dg-options "-fpeephole2 -mtune=m14k (-mmicromips)" } */ +/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */ + +void MICROMIPS +foo (int *r4, int r5, int r6) +{ + r6 *= r6; + r4[0] = r5; + r4[1] = r6; + { + register int r5asm asm ("$5") = r5; + register int r6asm asm ("$6") = r6; + asm ("#foo" : "=m" (r4[2]) : "d" (r5asm), "d" (r6asm)); + } +} + +/* { dg-final { scan-assembler "\tswp\t\\\$5,0\\(\\\$4\\)" } }*/ diff --git a/gcc/testsuite/gcc.target/mips/umips-swp-3.c b/gcc/testsuite/gcc.target/mips/umips-swp-3.c index e69de29bb2d..f0e54647d9c 100644 --- a/gcc/testsuite/gcc.target/mips/umips-swp-3.c +++ b/gcc/testsuite/gcc.target/mips/umips-swp-3.c @@ -0,0 +1,17 @@ +/* { dg-options "-fpeephole2 -mtune=m14k (-mmicromips)" } */ +/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */ + +void MICROMIPS +foo (int *r4, int r5, int r6) +{ + r5 *= r5; + r4[0] = r5; + r4[1] = r6; + { + register int r5asm asm ("$5") = r5; + register int r6asm asm ("$6") = r6; + asm ("#foo" : "=m" (r4[2]) : "d" (r5asm), "d" (r6asm)); + } +} + +/* { dg-final { scan-assembler "\tswp\t\\\$5,0\\(\\\$4\\)" } }*/ diff --git a/gcc/testsuite/gcc.target/mips/umips-swp-4.c b/gcc/testsuite/gcc.target/mips/umips-swp-4.c index e69de29bb2d..5e8f5ea2a76 100644 --- a/gcc/testsuite/gcc.target/mips/umips-swp-4.c +++ b/gcc/testsuite/gcc.target/mips/umips-swp-4.c @@ -0,0 +1,17 @@ +/* { dg-options "-fpeephole2 -mtune=m14k (-mmicromips)" } */ +/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */ + +void MICROMIPS +foo (int *r4, int r5, int r6) +{ + r6 *= r6; + r4[511] = r5; + r4[512] = r6; + { + register int r5asm asm ("$5") = r5; + register int r6asm asm ("$6") = r6; + asm ("#foo" : "=m" (r4[2]) : "d" (r5asm), "d" (r6asm)); + } +} + +/* { dg-final { scan-assembler "\tswp\t\\\$5,2044\\(\\\$4\\)" } }*/ diff --git a/gcc/testsuite/gcc.target/mips/umips-swp-5.c b/gcc/testsuite/gcc.target/mips/umips-swp-5.c index e69de29bb2d..dc1938e47b5 100644 --- a/gcc/testsuite/gcc.target/mips/umips-swp-5.c +++ b/gcc/testsuite/gcc.target/mips/umips-swp-5.c @@ -0,0 +1,17 @@ +/* { dg-options "-fpeephole2 -mtune=m14k (-mmicromips)" } */ +/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */ + +void MICROMIPS +foo (int *r4, int r5, int r6) +{ + r5 *= r5; + r4[511] = r5; + r4[512] = r6; + { + register int r5asm asm ("$5") = r5; + register int r6asm asm ("$6") = r6; + asm ("#foo" : "=m" (r4[2]) : "d" (r5asm), "d" (r6asm)); + } +} + +/* { dg-final { scan-assembler "\tswp\t\\\$5,2044\\(\\\$4\\)" } }*/ diff --git a/gcc/testsuite/gcc.target/mips/umips-swp-6.c b/gcc/testsuite/gcc.target/mips/umips-swp-6.c index e69de29bb2d..b489006ce99 100644 --- a/gcc/testsuite/gcc.target/mips/umips-swp-6.c +++ b/gcc/testsuite/gcc.target/mips/umips-swp-6.c @@ -0,0 +1,17 @@ +/* { dg-options "-fpeephole2 -mtune=m14k (-mmicromips)" } */ +/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */ + +void MICROMIPS +foo (int *r4, int r5, int r6) +{ + r6 *= r6; + r4[512] = r5; + r4[513] = r6; + { + register int r5asm asm ("$5") = r5; + register int r6asm asm ("$6") = r6; + asm ("#foo" : "=m" (r4[2]) : "d" (r5asm), "d" (r6asm)); + } +} + +/* { dg-final { scan-assembler-not "\tswp" } }*/ diff --git a/gcc/testsuite/gcc.target/mips/umips-swp-7.c b/gcc/testsuite/gcc.target/mips/umips-swp-7.c index e69de29bb2d..6dde49b8a35 100644 --- a/gcc/testsuite/gcc.target/mips/umips-swp-7.c +++ b/gcc/testsuite/gcc.target/mips/umips-swp-7.c @@ -0,0 +1,17 @@ +/* { dg-options "-fpeephole2 -mtune=m14k (-mmicromips)" } */ +/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */ + +void MICROMIPS +foo (int *r4, int r5, int r6) +{ + r5 *= r5; + r4[512] = r5; + r4[513] = r6; + { + register int r5asm asm ("$5") = r5; + register int r6asm asm ("$6") = r6; + asm ("#foo" : "=m" (r4[2]) : "d" (r5asm), "d" (r6asm)); + } +} + +/* { dg-final { scan-assembler-not "\tswp" } }*/ |