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Diffstat (limited to 'gcc/testsuite/gcc.target/arm/neon/vld3u64.c')
-rw-r--r--gcc/testsuite/gcc.target/arm/neon/vld3u64.c18
1 files changed, 18 insertions, 0 deletions
diff --git a/gcc/testsuite/gcc.target/arm/neon/vld3u64.c b/gcc/testsuite/gcc.target/arm/neon/vld3u64.c
new file mode 100644
index 00000000000..f31c4804d36
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld3u64.c
@@ -0,0 +1,18 @@
+/* Test the `vld3u64' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld3u64 (void)
+{
+ uint64x1x3_t out_uint64x1x3_t;
+
+ out_uint64x1x3_t = vld3_u64 (0);
+}
+
+/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */