diff options
Diffstat (limited to 'gcc/testsuite/gcc.target/arm/neon/vRshlQs64.c')
| -rw-r--r-- | gcc/testsuite/gcc.target/arm/neon/vRshlQs64.c | 20 |
1 files changed, 20 insertions, 0 deletions
diff --git a/gcc/testsuite/gcc.target/arm/neon/vRshlQs64.c b/gcc/testsuite/gcc.target/arm/neon/vRshlQs64.c new file mode 100644 index 00000000000..f20de10fdf8 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vRshlQs64.c @@ -0,0 +1,20 @@ +/* Test the `vRshlQs64' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */ + +#include "arm_neon.h" + +void test_vRshlQs64 (void) +{ + int64x2_t out_int64x2_t; + int64x2_t arg0_int64x2_t; + int64x2_t arg1_int64x2_t; + + out_int64x2_t = vrshlq_s64 (arg0_int64x2_t, arg1_int64x2_t); +} + +/* { dg-final { scan-assembler "vrshl\.s64\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ |