diff options
Diffstat (limited to 'gcc/rtlanal.c')
| -rw-r--r-- | gcc/rtlanal.c | 45 |
1 files changed, 24 insertions, 21 deletions
diff --git a/gcc/rtlanal.c b/gcc/rtlanal.c index 4e600c0de6d..4d7aad0dff0 100644 --- a/gcc/rtlanal.c +++ b/gcc/rtlanal.c @@ -2304,10 +2304,24 @@ add_shallow_copy_of_reg_note (rtx_insn *insn, rtx note) add_reg_note (insn, REG_NOTE_KIND (note), XEXP (note, 0)); } +/* Duplicate NOTE and return the copy. */ +rtx +duplicate_reg_note (rtx note) +{ + reg_note kind = REG_NOTE_KIND (note); + + if (GET_CODE (note) == INT_LIST) + return gen_rtx_INT_LIST ((machine_mode) kind, XINT (note, 0), NULL_RTX); + else if (GET_CODE (note) == EXPR_LIST) + return alloc_reg_note (kind, copy_insn_1 (XEXP (note, 0)), NULL_RTX); + else + return alloc_reg_note (kind, XEXP (note, 0), NULL_RTX); +} + /* Remove register note NOTE from the REG_NOTES of INSN. */ void -remove_note (rtx insn, const_rtx note) +remove_note (rtx_insn *insn, const_rtx note) { rtx link; @@ -2328,7 +2342,7 @@ remove_note (rtx insn, const_rtx note) { case REG_EQUAL: case REG_EQUIV: - df_notes_rescan (as_a <rtx_insn *> (insn)); + df_notes_rescan (insn); break; default: break; @@ -4361,13 +4375,11 @@ nonzero_bits1 (const_rtx x, machine_mode mode, const_rtx known_x, return UINTVAL (x); case MEM: -#ifdef LOAD_EXTEND_OP /* In many, if not most, RISC machines, reading a byte from memory zeros the rest of the register. Noticing that fact saves a lot of extra zero-extends. */ if (LOAD_EXTEND_OP (GET_MODE (x)) == ZERO_EXTEND) nonzero &= GET_MODE_MASK (GET_MODE (x)); -#endif break; case EQ: case NE: @@ -4567,19 +4579,17 @@ nonzero_bits1 (const_rtx x, machine_mode mode, const_rtx known_x, nonzero &= cached_nonzero_bits (SUBREG_REG (x), mode, known_x, known_mode, known_ret); -#ifdef LOAD_EXTEND_OP - /* If this is a typical RISC machine, we only have to worry - about the way loads are extended. */ - if (WORD_REGISTER_OPERATIONS - && ((LOAD_EXTEND_OP (inner_mode) == SIGN_EXTEND + /* On many CISC machines, accessing an object in a wider mode + causes the high-order bits to become undefined. So they are + not known to be zero. */ + if (!WORD_REGISTER_OPERATIONS + /* If this is a typical RISC machine, we only have to worry + about the way loads are extended. */ + || ((LOAD_EXTEND_OP (inner_mode) == SIGN_EXTEND ? val_signbit_known_set_p (inner_mode, nonzero) : LOAD_EXTEND_OP (inner_mode) != ZERO_EXTEND) || !MEM_P (SUBREG_REG (x)))) -#endif { - /* On many CISC machines, accessing an object in a wider mode - causes the high-order bits to become undefined. So they are - not known to be zero. */ if (GET_MODE_PRECISION (GET_MODE (x)) > GET_MODE_PRECISION (inner_mode)) nonzero |= (GET_MODE_MASK (GET_MODE (x)) @@ -4824,10 +4834,7 @@ num_sign_bit_copies1 (const_rtx x, machine_mode mode, const_rtx known_x, than a word and loads of that size don't sign extend, we can say nothing about the high order bits. */ if (GET_MODE_PRECISION (GET_MODE (x)) < BITS_PER_WORD -#ifdef LOAD_EXTEND_OP - && LOAD_EXTEND_OP (GET_MODE (x)) != SIGN_EXTEND -#endif - ) + && LOAD_EXTEND_OP (GET_MODE (x)) != SIGN_EXTEND) return 1; } @@ -4868,12 +4875,10 @@ num_sign_bit_copies1 (const_rtx x, machine_mode mode, const_rtx known_x, break; case MEM: -#ifdef LOAD_EXTEND_OP /* Some RISC machines sign-extend all loads of smaller than a word. */ if (LOAD_EXTEND_OP (GET_MODE (x)) == SIGN_EXTEND) return MAX (1, ((int) bitwidth - (int) GET_MODE_PRECISION (GET_MODE (x)) + 1)); -#endif break; case CONST_INT: @@ -4910,7 +4915,6 @@ num_sign_bit_copies1 (const_rtx x, machine_mode mode, const_rtx known_x, - bitwidth))); } -#ifdef LOAD_EXTEND_OP /* For paradoxical SUBREGs on machines where all register operations affect the entire register, just look inside. Note that we are passing MODE to the recursive call, so the number of sign bit copies @@ -4927,7 +4931,6 @@ num_sign_bit_copies1 (const_rtx x, machine_mode mode, const_rtx known_x, && MEM_P (SUBREG_REG (x))) return cached_num_sign_bit_copies (SUBREG_REG (x), mode, known_x, known_mode, known_ret); -#endif break; case SIGN_EXTRACT: |