diff options
Diffstat (limited to 'gcc/doc')
| -rw-r--r-- | gcc/doc/contrib.texi | 5 | ||||
| -rw-r--r-- | gcc/doc/cppdiropts.texi | 5 | ||||
| -rw-r--r-- | gcc/doc/cppopts.texi | 2 | ||||
| -rw-r--r-- | gcc/doc/extend.texi | 26 | ||||
| -rw-r--r-- | gcc/doc/fragments.texi | 10 | ||||
| -rw-r--r-- | gcc/doc/install.texi | 5 | ||||
| -rw-r--r-- | gcc/doc/invoke.texi | 408 | ||||
| -rw-r--r-- | gcc/doc/sourcebuild.texi | 15 |
8 files changed, 419 insertions, 57 deletions
diff --git a/gcc/doc/contrib.texi b/gcc/doc/contrib.texi index 4f5ffc1710f..60b71026779 100644 --- a/gcc/doc/contrib.texi +++ b/gcc/doc/contrib.texi @@ -761,6 +761,11 @@ clean-ups and porting work, and maintaining the IRIX, Solaris 2, and Tru64 UNIX ports. @item +Steven Pemberton for his contribution of @file{enquire} which allowed GCC to +determine various properties of the floating point unit and generate +@file{float.h} in older versions of GCC. + +@item Hartmut Penner for work on the s390 port. @item diff --git a/gcc/doc/cppdiropts.texi b/gcc/doc/cppdiropts.texi index 1f72649937c..eee2b5cede8 100644 --- a/gcc/doc/cppdiropts.texi +++ b/gcc/doc/cppdiropts.texi @@ -22,8 +22,9 @@ for header files during preprocessing. @ifset cppmanual @xref{Search Path}. @end ifset -If @var{dir} begins with @samp{=}, then the @samp{=} is replaced -by the sysroot prefix; see @option{--sysroot} and @option{-isysroot}. +If @var{dir} begins with @samp{=} or @code{$SYSROOT}, then the @samp{=} +or @code{$SYSROOT} is replaced by the sysroot prefix; see +@option{--sysroot} and @option{-isysroot}. Directories specified with @option{-iquote} apply only to the quote form of the directive, @code{@w{#include "@var{file}"}}. diff --git a/gcc/doc/cppopts.texi b/gcc/doc/cppopts.texi index 0497712bee9..16bf22a6f38 100644 --- a/gcc/doc/cppopts.texi +++ b/gcc/doc/cppopts.texi @@ -125,6 +125,8 @@ preprocessed output. When used with the driver options @option{-MD} or @option{-MMD}, @option{-MF} overrides the default dependency output file. +If @var{file} is @file{-}, then the dependencies are written to @file{stdout}. + @item -MG @opindex MG In conjunction with an option such as @option{-M} requesting diff --git a/gcc/doc/extend.texi b/gcc/doc/extend.texi index ef1ae73954c..43f9ecf2466 100644 --- a/gcc/doc/extend.texi +++ b/gcc/doc/extend.texi @@ -2911,6 +2911,18 @@ This has a similar effect as the @option{-fno-toplevel-reorder} option, but only applies to the marked symbols. +@item no_sanitize ("@var{sanitize_option}") +@cindex @code{no_sanitize} function attribute +The @code{no_sanitize} attribute on functions is used +to inform the compiler that it should not do sanitization of all options +mentioned in @var{sanitize_option}. A list of values acceptable by +@option{-fsanitize} option can be provided. + +@smallexample +void __attribute__ ((no_sanitize ("alignment", "object-size"))) +f () @{ /* @r{Do something.} */; @} +@end smallexample + @item no_sanitize_address @itemx no_address_safety_analysis @cindex @code{no_sanitize_address} function attribute @@ -15990,6 +16002,20 @@ vector float vec_expte (vector float); vector float vec_floor (vector float); +vector float vec_float (vector signed int); +vector float vec_float (vector unsigned int); + +vector float vec_float2 (vector signed long long, vector signed long long); +vector float vec_float2 (vector unsigned long long, vector signed long long); + +vector float vec_floate (vector double); +vector float vec_floate (vector signed long long); +vector float vec_floate (vector unsigned long long); + +vector float vec_floato (vector double); +vector float vec_floato (vector signed long long); +vector float vec_floato (vector unsigned long long); + vector float vec_ld (int, const vector float *); vector float vec_ld (int, const float *); vector bool int vec_ld (int, const vector bool int *); diff --git a/gcc/doc/fragments.texi b/gcc/doc/fragments.texi index d68be7ad0ed..6aef5537f43 100644 --- a/gcc/doc/fragments.texi +++ b/gcc/doc/fragments.texi @@ -160,10 +160,12 @@ A reuse rule is comprised of two parts connected by equality sign. The left part is the option set used to build multilib and the right part is the option set that will reuse this multilib. Both parts should only use options specified in @code{MULTILIB_OPTIONS} and the equality signs found in options -name should be replaced with periods. The order of options in the left part -matters and should be same with those specified in @code{MULTILIB_REQUIRED} or -aligned with the order in @code{MULTILIB_OPTIONS}. There is no such limitation -for options in the right part as we don't build multilib from them. +name should be replaced with periods. An explicit period in the rule can be +escaped by preceding it with a backslash. The order of options in the left +part matters and should be same with those specified in +@code{MULTILIB_REQUIRED} or aligned with the order in @code{MULTILIB_OPTIONS}. +There is no such limitation for options in the right part as we don't build +multilib from them. @code{MULTILIB_REUSE} is different from @code{MULTILIB_MATCHES} in that it sets up relations between two option sets rather than two options. Here is an diff --git a/gcc/doc/install.texi b/gcc/doc/install.texi index 8e17bcc1d42..7c9e2f25d44 100644 --- a/gcc/doc/install.texi +++ b/gcc/doc/install.texi @@ -2619,8 +2619,9 @@ bootstrap the compiler with profile feedback, use @code{make profiledbootstrap}. When @samp{make profiledbootstrap} is run, it will first build a @code{stage1} compiler. This compiler is used to build a @code{stageprofile} compiler instrumented to collect execution counts of instruction and branch -probabilities. Then runtime libraries are compiled with profile collected. -Finally a @code{stagefeedback} compiler is built using the information collected. +probabilities. Training run is done by building @code{stagetrain} +compiler. Finally a @code{stagefeedback} compiler is built +using the information collected. Unlike standard bootstrap, several additional restrictions apply. The compiler used to build @code{stage1} needs to support a 64-bit integral type. diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi index 653bc076759..e4ca1b4b4fc 100644 --- a/gcc/doc/invoke.texi +++ b/gcc/doc/invoke.texi @@ -215,7 +215,8 @@ in the following sections. -Wabi=@var{n} -Wabi-tag -Wconversion-null -Wctor-dtor-privacy @gol -Wdelete-non-virtual-dtor -Wliteral-suffix -Wmultiple-inheritance @gol -Wnamespaces -Wnarrowing @gol --Wnoexcept -Wnoexcept-type -Wnon-virtual-dtor -Wreorder -Wregister @gol +-Wnoexcept -Wnoexcept-type -Wclass-memaccess @gol +-Wnon-virtual-dtor -Wreorder -Wregister @gol -Weffc++ -Wstrict-null-sentinel -Wtemplates @gol -Wno-non-template-friend -Wold-style-cast @gol -Woverloaded-virtual -Wno-pmf-conversions @gol @@ -2907,7 +2908,7 @@ to a function that does not have a non-throwing exception specification (i.e. @code{throw()} or @code{noexcept}) but is known by the compiler to never throw an exception. -@item -Wnoexcept @r{(C++ and Objective-C++ only)} +@item -Wnoexcept-type @r{(C++ and Objective-C++ only)} @opindex Wnoexcept-type @opindex Wno-noexcept-type Warn if the C++1z feature making @code{noexcept} part of a function @@ -2920,6 +2921,23 @@ void g() noexcept; void h() @{ f(g); @} // in C++14 calls f<void(*)()>, in C++1z calls f<void(*)()noexcept> @end smallexample +@item -Wclass-memaccess @r{(C++ and Objective-C++ only)} +@opindex Wclass-memaccess +Warn when the destination of a call to a raw memory function such as +@code{memset} or @code{memcpy} is an object of class type writing into which +might bypass the class non-trivial or deleted constructor or copy assignment, +violate const-correctness or encapsulation, or corrupt the virtual table. +Modifying the representation of such objects may violate invariants maintained +by member functions of the class. For example, the call to @code{memset} +below is undefined becase it modifies a non-trivial class object and is, +therefore, diagnosed. The safe way to either initialize or clear the storage +of objects of such types is by using the appropriate constructor or assignment +operator, if one is available. +@smallexample +std::string str = "abc"; +memset (&str, 0, 3); +@end smallexample +The @option{-Wclass-memaccess} option is enabled by @option{-Wall}. @item -Wnon-virtual-dtor @r{(C++ and Objective-C++ only)} @opindex Wnon-virtual-dtor @@ -14059,17 +14077,20 @@ processors implementing the target architecture. @opindex mtune Specify the name of the target processor for which GCC should tune the performance of the code. Permissible values for this option are: -@samp{generic}, @samp{cortex-a35}, @samp{cortex-a53}, @samp{cortex-a57}, -@samp{cortex-a72}, @samp{cortex-a73}, @samp{exynos-m1}, +@samp{generic}, @samp{cortex-a35}, @samp{cortex-a53}, @samp{cortex-a55}, +@samp{cortex-a57}, @samp{cortex-a72}, @samp{cortex-a73}, @samp{cortex-a75}, +@samp{exynos-m1}, @samp{falkor}, @samp{qdf24xx}, @samp{xgene1}, @samp{vulcan}, @samp{thunderx}, @samp{thunderxt88}, @samp{thunderxt88p1}, @samp{thunderxt81}, @samp{thunderxt83}, @samp{thunderx2t99}, @samp{cortex-a57.cortex-a53}, @samp{cortex-a72.cortex-a53}, @samp{cortex-a73.cortex-a35}, -@samp{cortex-a73.cortex-a53}, @samp{native}. +@samp{cortex-a73.cortex-a53}, @samp{cortex-a75.cortex-a55}, +@samp{native}. The values @samp{cortex-a57.cortex-a53}, @samp{cortex-a72.cortex-a53}, -@samp{cortex-a73.cortex-a35}, @samp{cortex-a73.cortex-a53} -specify that GCC should tune for a big.LITTLE system. +@samp{cortex-a73.cortex-a35}, @samp{cortex-a73.cortex-a53}, +@samp{cortex-a75.cortex-a55} specify that GCC should tune for a +big.LITTLE system. Additionally on native AArch64 GNU/Linux systems the value @samp{native} tunes performance to the host system. This option has no effect @@ -15140,48 +15161,291 @@ the default for all standard configurations. Generate code for a processor running in big-endian mode; the default is to compile code for a little-endian processor. -@item -march=@var{name} +@item -march=@var{name@r{[}+extension@dots{}@r{]}} @opindex march This specifies the name of the target ARM architecture. GCC uses this name to determine what kind of instructions it can emit when generating assembly code. This option can be used in conjunction with or instead -of the @option{-mcpu=} option. Permissible names are: @samp{armv2}, -@samp{armv2a}, @samp{armv3}, @samp{armv3m}, @samp{armv4}, @samp{armv4t}, -@samp{armv5}, @samp{armv5e}, @samp{armv5t}, @samp{armv5te}, -@samp{armv6}, @samp{armv6-m}, @samp{armv6j}, @samp{armv6k}, -@samp{armv6kz}, @samp{armv6s-m}, -@samp{armv6t2}, @samp{armv6z}, @samp{armv6zk}, -@samp{armv7}, @samp{armv7-a}, @samp{armv7-m}, @samp{armv7-r}, @samp{armv7e-m}, -@samp{armv7ve}, @samp{armv8-a}, @samp{armv8-a+crc}, @samp{armv8.1-a}, -@samp{armv8.1-a+crc}, @samp{armv8-m.base}, @samp{armv8-m.main}, -@samp{armv8-m.main+dsp}, @samp{iwmmxt}, @samp{iwmmxt2}. +of the @option{-mcpu=} option. + +Permissible names are: +@samp{armv4t}, +@samp{armv5t}, @samp{armv5te}, +@samp{armv6}, @samp{armv6j}, @samp{armv6k}, @samp{armv6kz}, @samp{armv6t2}, +@samp{armv6z}, @samp{armv6zk}, +@samp{armv7}, @samp{armv7-a}, @samp{armv7ve}, +@samp{armv8-a}, @samp{armv8.1-a}, @samp{armv8.2-a}, +@samp{armv7-r}, +@samp{armv6-m}, @samp{armv6s-m}, +@samp{armv7-m}, @samp{armv7e-m}, +@samp{armv8-m.base}, @samp{armv8-m.main}, +@samp{iwmmxt} and @samp{iwmmxt2}. + +Additionally, the following architectures, which lack support for the +Thumb exection state, are recognized but support is deprecated: +@samp{armv2}, @samp{armv2a}, @samp{armv3}, @samp{armv3m}, +@samp{armv4}, @samp{armv5} and @samp{armv5e}. + +Many of the architectures support extensions. These can be added by +appending @samp{+@var{extension}} to the architecture name. Extension +options are processed in order and capabilities accumulate. An extension +will also enable any necessary base extensions +upon which it depends. For example, the @samp{+crypto} extension +will always enable the @samp{+simd} extension. The exception to the +additive construction is for extensions that are prefixed with +@samp{+no@dots{}}: these extensions disable the specified option and +any other extensions that may depend on the presence of that +extension. -Architecture revisions older than @samp{armv4t} are deprecated. +For example, @samp{-march=armv7-a+simd+nofp+vfpv4} is equivalent to +writing @samp{-march=armv7-a+vfpv4} since the @samp{+simd} option is +entirely disabled by the @samp{+nofp} option that follows it. -@option{-march=armv6s-m} is the @samp{armv6-m} architecture with support for -the (now mandatory) SVC instruction. +Most extension names are generically named, but have an effect that is +dependent upon the architecture to which it is applied. For example, +the @samp{+simd} option can be applied to both @samp{armv7-a} and +@samp{armv8-a} architectures, but will enable the original ARMv7 +Advanced SIMD (Neon) extensions for @samp{armv7-a} and the ARMv8-a +variant for @samp{armv8-a}. -@option{-march=armv6zk} is an alias for @samp{armv6kz}, existing for backwards -compatibility. +The table below lists the supported extensions for each architecture. +Architectures not mentioned do not support any extensions. -@option{-march=armv7ve} is the @samp{armv7-a} architecture with virtualization -extensions. +@table @samp +@item armv5e +@itemx armv5te +@itemx armv6 +@itemx armv6j +@itemx armv6k +@itemx armv6kz +@itemx armv6t2 +@itemx armv6z +@itemx armv6zk +@table @samp +@item +fp +The VFPv2 floating-point instructions. The extension @samp{+vfpv2} can be +used as an alias for this extension. -@option{-march=armv8-a+crc} enables code generation for the ARMv8-A -architecture together with the optional CRC32 extensions. +@item +nofp +Disable the floating-point instructions. +@end table -@option{-march=armv8.1-a} enables compiler support for the ARMv8.1-A -architecture. This also enables the features provided by -@option{-march=armv8-a+crc}. +@item armv7 +The common subset of the ARMv7-A, ARMv7-R and ARMv7-M architectures. +@table @samp +@item +fp +The VFPv3 floating-point instructions, with 16 double-precision +registers. The extension @samp{+vfpv3-d16} can be used as an alias +for this extension. Note that floating-point is not supported by the +base ARMv7-M architecture, but is compatible with both the ARMv7-A and +ARMv7-R architectures. + +@item +nofp +Disable the floating-point instructions. +@end table -@option{-march=armv8.2-a} enables compiler support for the ARMv8.2-A -architecture. This also enables the features provided by -@option{-march=armv8.1-a}. +@item armv7-a +@table @samp +@item +fp +The VFPv3 floating-point instructions, with 16 double-precision +registers. The extension @samp{+vfpv3-d16} can be used as an alias +for this extension. + +@item +simd +The Advanced SIMD (Neon) v1 and the VFPv3 floating-point instructions. +The extensions @samp{+neon} and @samp{+neon-vfpv3} can be used as aliases +for this extension. + +@item +vfpv3 +The VFPv3 floating-point instructions, with 32 double-precision +registers. + +@item +vfpv3-d16-fp16 +The VFPv3 floating-point instructions, with 16 double-precision +registers and the half-precision floating-point conversion operations. + +@item +vfpv3-fp16 +The VFPv3 floating-point instructions, with 32 double-precision +registers and the half-precision floating-point conversion operations. + +@item +vfpv4-d16 +The VFPv4 floating-point instructions, with 16 double-precision +registers. + +@item +vfpv4 +The VFPv4 floating-point instructions, with 32 double-precision +registers. + +@item +neon-fp16 +The Advanced SIMD (Neon) v1 and the VFPv3 floating-point instructions, with +the half-precision floating-point conversion operations. + +@item +neon-vfpv4 +The Advanced SIMD (Neon) v2 and the VFPv4 floating-point instructions. + +@item +nosimd +Disable the Advanced SIMD instructions (does not disable floating point). -@option{-march=armv8.2-a+fp16} enables compiler support for the -ARMv8.2-A architecture with the optional FP16 instructions extension. -This also enables the features provided by @option{-march=armv8.1-a} -and implies @option{-mfp16-format=ieee}. +@item +nofp +Disable the floating-point and Advanced SIMD instructions. +@end table + +@item armv7ve +The extended version of the ARMv7-A architecture with support for +virtualization. +@table @samp +@item +fp +The VFPv4 floating-point instructions, with 16 double-precision registers. +The extension @samp{+vfpv4-d16} can be used as an alias for this extension. + +@item +simd +The Advanced SIMD (Neon) v2 and the VFPv4 floating-point instructions. The +extension @samp{+neon-vfpv4} can be used as an alias for this extension. + +@item +vfpv3-d16 +The VFPv3 floating-point instructions, with 16 double-precision +registers. + +@item +vfpv3 +The VFPv3 floating-point instructions, with 32 double-precision +registers. + +@item +vfpv3-d16-fp16 +The VFPv3 floating-point instructions, with 16 double-precision +registers and the half-precision floating-point conversion operations. + +@item +vfpv3-fp16 +The VFPv3 floating-point instructions, with 32 double-precision +registers and the half-precision floating-point conversion operations. + +@item +vfpv4-d16 +The VFPv4 floating-point instructions, with 16 double-precision +registers. + +@item +vfpv4 +The VFPv4 floating-point instructions, with 32 double-precision +registers. + +@item +neon +The Advanced SIMD (Neon) v1 and the VFPv3 floating-point instructions. +The extension @samp{+neon-vfpv3} can be used as an alias for this extension. + +@item +neon-fp16 +The Advanced SIMD (Neon) v1 and the VFPv3 floating-point instructions, with +the half-precision floating-point conversion operations. + +@item +nosimd +Disable the Advanced SIMD instructions (does not disable floating point). + +@item +nofp +Disable the floating-point and Advanced SIMD instructions. +@end table + +@item armv8-a +@table @samp +@item +crc +The Cyclic Redundancy Check (CRC) instructions. +@item +simd +The ARMv8 Advanced SIMD and floating-point instructions. +@item +crypto +The cryptographic instructions. +@item +nocrypto +Disable the cryptographic isntructions. +@item +nofp +Disable the floating-point, Advanced SIMD and cryptographic instructions. +@end table + +@item armv8.1-a +@table @samp +@item +simd +The ARMv8.1 Advanced SIMD and floating-point instructions. + +@item +crypto +The cryptographic instructions. This also enables the Advanced SIMD and +floating-point instructions. + +@item +nocrypto +Disable the cryptographic isntructions. + +@item +nofp +Disable the floating-point, Advanced SIMD and cryptographic instructions. +@end table + +@item armv8.2-a +@table @samp +@item +fp16 +The half-precision floating-point data processing instructions. +This also enables the Advanced SIMD and floating-point instructions. + +@item +simd +The ARMv8.1 Advanced SIMD and floating-point instructions. + +@item +crypto +The cryptographic instructions. This also enables the Advanced SIMD and +floating-point instructions. + +@item +nocrypto +Disable the cryptographic extension. + +@item +nofp +Disable the floating-point, Advanced SIMD and cryptographic instructions. +@end table + +@item armv7-r +@table @samp +@item +fp.sp +The single-precision VFPv3 floating-point instructions. The extension +@samp{+vfpv3xd} can be used as an alias for this extension. + +@item +fp +The VFPv3 floating-point instructions with 16 double-precision registers. +The extension +vfpv3-d16 can be used as an alias for this extension. + +@item +nofp +Disable the floating-point extension. + +@item +idiv +The ARM-state integer division instructions. + +@item +noidiv +Disable the ARM-state integer division extension. +@end table + +@item armv7e-m +@table @samp +@item +fp +The single-precision VFPv4 floating-point instructions. + +@item +fpv5 +The single-precision FPv5 floating-point instructions. + +@item +fp.dp +The single- and double-precision FPv5 floating-point instructions. + +@item +nofp +Disable the floating-point extensions. +@end table + +@item armv8-m.main +@table @samp +@item +dsp +The DSP instructions. + +@item +nodsp +Disable the DSP extension. + +@item +fp +The single-precision floating-point instructions. + +@item +fp.dp +The single- and double-precision floating-point instructions. + +@item +nofp +Disable the floating-point extension. + +@end table + +@end table @option{-march=native} causes the compiler to auto-detect the architecture of the build computer. At present, this feature is only supported on @@ -15228,8 +15492,6 @@ Permissible names are: @samp{arm2}, @samp{arm250}, @samp{cortex-m0.small-multiply}, @samp{cortex-m0plus.small-multiply}, @samp{exynos-m1}, -@samp{falkor}, -@samp{qdf24xx}, @samp{marvell-pj4}, @samp{xscale}, @samp{iwmmxt}, @samp{iwmmxt2}, @samp{ep9312}, @samp{fa526}, @samp{fa626}, @@ -15249,12 +15511,15 @@ processors, balancing between optimizations that benefit some CPUs in the range, and avoiding performance pitfalls of other CPUs. The effects of this option may change in future GCC versions as CPU models come and go. +@option{-mtune} permits the same extension options as @option{-mcpu}, but +the extension options do not affect the tuning of the generated code. + @option{-mtune=native} causes the compiler to auto-detect the CPU of the build computer. At present, this feature is only supported on GNU/Linux, and not all architectures are recognized. If the auto-detect is unsuccessful the option has no effect. -@item -mcpu=@var{name} +@item -mcpu=@var{name@r{[}+extension@dots{}@r{]}} @opindex mcpu This specifies the name of the target ARM processor. GCC uses this name to derive the name of the target ARM architecture (as if specified @@ -15263,9 +15528,62 @@ performance (as if specified by @option{-mtune}). Where this option is used in conjunction with @option{-march} or @option{-mtune}, those options take precedence over the appropriate part of this option. +Many of the supported CPUs implement optional architectural +extensions. Where this is so the architectural extensions are +normally enabled by default. If implementations that lack the +extension exist, then the extension syntax can be used to disable +those extensions that have been omitted. For floating-point and +Advanced SIMD (Neon) instructions, the settings of the options +@option{-mfloat-abi} and @option{-mfpu} must also be considered: +floating-point and Advanced SIMD instructions will only be used if +@option{-mfloat-abi} is not set to @samp{soft}; and any setting of +@option{-mfpu} other than @samp{auto} will override the available +floating-point and SIMD extension instructions. + +For example, @samp{cortex-a9} can be found in three major +configurations: integer only, with just a floating-point unit or with +floating-point and Advanced SIMD. The default is to enable all the +instructions, but the extensions @samp{+nosimd} and @samp{+nofp} can +be used to disable just the SIMD or both the SIMD and floating-point +instructions respectively. + Permissible names for this option are the same as those for @option{-mtune}. +The following extension options are common to the listed CPUs: + +@table @samp +@item +nofp +Disables the floating-point instructions on @samp{arm9e}, +@samp{arm946e-s}, @samp{arm966e-s}, @samp{arm968e-s}, @samp{arm10e}, +@samp{arm1020e}, @samp{arm1022e}, @samp{arm926ej-s}, +@samp{arm1026ej-s}, @samp{cortex-r5}, @samp{cortex-r7}, @samp{cortex-r8}, +@samp{cortex-m4}, @samp{cortex-m7} and @samp{cortex-m33}. +Disables the floating-point and SIMD instructions on +@samp{generic-armv7-a}, @samp{cortex-a5}, @samp{cortex-a7}, +@samp{cortex-a8}, @samp{cortex-a9}, @samp{cortex-a12}, +@samp{cortex-a15}, @samp{cortex-a17}, @samp{cortex-a15.cortex-a7}, +@samp{cortex-a17.cortex-a7}, @samp{cortex-a32}, @samp{cortex-a35} +and @samp{cortex-a53}. + +@item +nofp.dp +Disables the double-precision component of the floating-point instructions +on @samp{cortex-r5} and @samp{cortex-m7}. + +@item +nosimd +Disables the SIMD (but not floating-point) instructions on +@samp{generic-armv7-a}, @samp{cortex-a5}, @samp{cortex-a7} +and @samp{cortex-a9}. +@end table + +Additionally the @samp{generic-armv7-a} pseudo target defaults to +VFPv3 with 16 double-precision registers. It supports the following +extension options: @samp{vfpv3-d16}, @samp{vfpv3}, +@samp{vfpv3-d16-fp16}, @samp{vfpv3-fp16}, @samp{vfpv4-d16}, +@samp{vfpv4}, @samp{neon}, @samp{neon-vfpv3}, @samp{neon-fp16}, +@samp{neon-vfpv4}. The meanings are the same as for the extensions to +@option{-march=armv7-a}. + @option{-mcpu=generic-@var{arch}} is also permissible, and is equivalent to @option{-march=@var{arch} -mtune=generic-@var{arch}}. See @option{-mtune} for more information. @@ -15278,7 +15596,8 @@ is unsuccessful the option has no effect. @item -mfpu=@var{name} @opindex mfpu This specifies what floating-point hardware (or hardware emulation) is -available on the target. Permissible names are: @samp{vfpv2}, @samp{vfpv3}, +available on the target. Permissible names are: @samp{auto}, @samp{vfpv2}, +@samp{vfpv3}, @samp{vfpv3-fp16}, @samp{vfpv3-d16}, @samp{vfpv3-d16-fp16}, @samp{vfpv3xd}, @samp{vfpv3xd-fp16}, @samp{neon-vfpv3}, @samp{neon-fp16}, @samp{vfpv4}, @samp{vfpv4-d16}, @samp{fpv4-sp-d16}, @samp{neon-vfpv4}, @@ -15287,11 +15606,12 @@ available on the target. Permissible names are: @samp{vfpv2}, @samp{vfpv3}, Note that @samp{neon} is an alias for @samp{neon-vfpv3} and @samp{vfp} is an alias for @samp{vfpv2}. -If @option{-msoft-float} is specified this specifies the format of -floating-point values. +The setting @samp{auto} is the default and is special. It causes the +compiler to select the floating-point and Advanced SIMD instructions +based on the settings of @option{-mcpu} and @option{-march}. If the selected floating-point hardware includes the NEON extension -(e.g. @option{-mfpu}=@samp{neon}), note that floating-point +(e.g. @option{-mfpu=neon}), note that floating-point operations are not generated by GCC's auto-vectorization pass unless @option{-funsafe-math-optimizations} is also specified. This is because NEON hardware does not fully implement the IEEE 754 standard for diff --git a/gcc/doc/sourcebuild.texi b/gcc/doc/sourcebuild.texi index e5f0da6a49b..7f5c2cf58c4 100644 --- a/gcc/doc/sourcebuild.texi +++ b/gcc/doc/sourcebuild.texi @@ -2097,11 +2097,10 @@ Target supports section anchors. Target defaults to short enums. @item stack_size -Target has limited stack size. The stack size limit can be obtained using -@code{[dg-effective-target-value stack_size]}. For example: -@smallexample -/* @{ dg-additional-options "-DSTACK_SIZE=[dg-effective-target-value stack_size]" @{ target @{ stack_size @} @} @} */ -@end smallexample +@anchor{stack_size_et} +Target has limited stack size. The stack size limit can be obtained using the +STACK_SIZE macro defined by @ref{stack_size_ao,,@code{dg-add-options} feature +@code{stack_size}}. @item static Target supports @option{-static}. @@ -2282,6 +2281,12 @@ compliance mode. @code{mips16} function attributes. Only MIPS targets support this feature, and only then in certain modes. +@item stack_size +@anchor{stack_size_ao} +Add the flags needed to define macro STACK_SIZE and set it to the stack size +limit associated with the @ref{stack_size_et,,@code{stack_size} effective +target}. + @item tls Add the target-specific flags needed to use thread-local storage. @end table |