diff options
Diffstat (limited to 'gcc/doc/invoke.texi')
| -rw-r--r-- | gcc/doc/invoke.texi | 98 |
1 files changed, 91 insertions, 7 deletions
diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi index f02c226e5a9..1496d3042af 100644 --- a/gcc/doc/invoke.texi +++ b/gcc/doc/invoke.texi @@ -512,7 +512,8 @@ Objective-C and Objective-C++ Dialects}. -mword-relocations @gol -mfix-cortex-m3-ldrd @gol -munaligned-access @gol --mneon-for-64bits} +-mneon-for-64bits @gol +-mrestrict-it} @emph{AVR Options} @gccoptlist{-mmcu=@var{mcu} -maccumulate-args -mbranch-cost=@var{cost} @gol @@ -752,6 +753,7 @@ Objective-C and Objective-C++ Dialects}. -mno-float -msingle-float -mdouble-float @gol -mdsp -mno-dsp -mdspr2 -mno-dspr2 @gol -mmcu -mmno-mcu @gol +-meva -mno-eva @gol -mmicromips -mno-micromips @gol -mfpu=@var{fpu-type} @gol -msmartmips -mno-smartmips @gol @@ -860,7 +862,10 @@ See RS/6000 and PowerPC Options. -mno-recip-precision @gol -mveclibabi=@var{type} -mfriz -mno-friz @gol -mpointers-to-nested-functions -mno-pointers-to-nested-functions @gol --msave-toc-indirect -mno-save-toc-indirect} +-msave-toc-indirect -mno-save-toc-indirect @gol +-mpower8-fusion -mno-mpower8-fusion -mpower8-vector -mno-power8-vector @gol +-mcrypto -mno-crypto -mdirect-move -mno-direct-move @gol +-mquad-memory -mno-quad-memory} @emph{RX Options} @gccoptlist{-m64bit-doubles -m32bit-doubles -fpu -nofpu@gol @@ -933,7 +938,7 @@ See RS/6000 and PowerPC Options. -mvis2 -mno-vis2 -mvis3 -mno-vis3 @gol -mcbcond -mno-cbcond @gol -mfmaf -mno-fmaf -mpopc -mno-popc @gol --mfix-at697f} +-mfix-at697f -mfix-ut699} @emph{SPU Options} @gccoptlist{-mwarn-reloc -merror-reloc @gol @@ -1796,6 +1801,17 @@ Program Interface v3.0 @w{@uref{http://www.openmp.org/}}. This option implies @option{-pthread}, and thus is only supported on targets that have support for @option{-pthread}. +@item -fcilkplus +@opindex fcilkplus +@cindex Enable Cilk Plus +Enable the usage of Cilk Language extension features for C/C++. When the flag +@option{-fcilkplus} is specified, all the Cilk Plus components are converted +to the appropriate C/C++ code. The present implementation follows ABI version +0.9. There are four major parts to Cilk Plus language +extension: Array Notations, Cilk Keywords, SIMD annotations and elemental +functions. Detailed information about Cilk Plus can be found at +@w{@uref{http://www.cilkplus.org}}. + @item -fgnu-tm @opindex fgnu-tm When the option @option{-fgnu-tm} is specified, the compiler @@ -6158,7 +6174,7 @@ Controls optimization dumps from various optimization passes. If the @samp{-@var{options}} form is used, @var{options} is a list of @samp{-} separated options to select the dump details and optimizations. If @var{options} is not specified, it defaults to -@option{all} for details and @option{optall} for optimization +@option{optimized} for details and @option{optall} for optimization groups. If the @var{filename} is not specified, it defaults to @file{stderr}. Note that the output @var{filename} will be overwritten in case of multiple translation units. If a combined output from @@ -11618,6 +11634,12 @@ defined. Enables using Neon to handle scalar 64-bits operations. This is disabled by default since the cost of moving data from core registers to Neon is high. + +@item -mrestrict-it +@opindex mrestrict-it +Restricts generation of IT blocks to conform to the rules of ARMv8. +IT blocks can only contain a single 16-bit instruction from a select +set of instructions. This option is on by default for ARMv8 Thumb mode. @end table @node AVR Options @@ -13811,10 +13833,19 @@ Intel Core CPU with 64-bit extensions, MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AES, PCLMUL, FSGSBASE, RDRND and F16C instruction set support. +@item core-avx2 +Intel Core CPU with 64-bit extensions, MOVBE, MMX, SSE, SSE2, SSE3, SSSE3, +SSE4.1, SSE4.2, AVX, AVX2, AES, PCLMUL, FSGSBASE, RDRND, FMA, BMI, BMI2 +and F16C instruction set support. + @item atom -Intel Atom CPU with 64-bit extensions, MMX, SSE, SSE2, SSE3 and SSSE3 +Intel Atom CPU with 64-bit extensions, MOVBE, MMX, SSE, SSE2, SSE3 and SSSE3 instruction set support. +@item slm +Intel Silvermont CPU with 64-bit extensions, MOVBE, MMX, SSE, SSE2, SSE3, SSSE3, +SSE4.1 and SSE4.2 instruction set support. + @item k6 AMD K6 CPU with MMX instruction set support. @@ -15993,7 +16024,7 @@ The processor names are: @samp{1004kc}, @samp{1004kf2_1}, @samp{1004kf1_1}, @samp{loongson2e}, @samp{loongson2f}, @samp{loongson3a}, @samp{m4k}, -@samp{m14k}, @samp{m14ke}, @samp{m14kec}, +@samp{m14k}, @samp{m14kc}, @samp{m14ke}, @samp{m14kec}, @samp{octeon}, @samp{octeon+}, @samp{octeon2}, @samp{orion}, @samp{r2000}, @samp{r3000}, @samp{r3900}, @samp{r4000}, @samp{r4400}, @@ -16362,6 +16393,12 @@ Use (do not use) MT Multithreading instructions. @opindex mno-mcu Use (do not use) the MIPS MCU ASE instructions. +@item -meva +@itemx -mno-eva +@opindex meva +@opindex mno-eva +Use (do not use) the MIPS Enhanced Virtual Addressing instructions. + @item -mlong64 @opindex mlong64 Force @code{long} types to be 64 bits wide. See @option{-mlong32} for @@ -17341,7 +17378,8 @@ following options: @gccoptlist{-maltivec -mfprnd -mhard-float -mmfcrf -mmultiple @gol -mpopcntb -mpopcntd -mpowerpc64 @gol -mpowerpc-gpopt -mpowerpc-gfxopt -msingle-float -mdouble-float @gol --msimple-fpu -mstring -mmulhw -mdlmzb -mmfpgpr -mvsx} +-msimple-fpu -mstring -mmulhw -mdlmzb -mmfpgpr -mvsx @gol +-mcrypto -mdirect-move -mpower8-fusion -mpower8-vector -mquad-memory} The particular options set for any particular CPU varies between compiler versions, depending on what setting seems to produce optimal @@ -17459,6 +17497,47 @@ Generate code that uses (does not use) vector/scalar (VSX) instructions, and also enable the use of built-in functions that allow more direct access to the VSX instruction set. +@item -mcrypto +@itemx -mno-crypto +@opindex mcrypto +@opindex mno-crypto +Enable the use (disable) of the built-in functions that allow direct +access to the cryptographic instructions that were added in version +2.07 of the PowerPC ISA. + +@item -mdirect-move +@itemx -mno-direct-move +@opindex mdirect-move +@opindex mno-direct-move +Generate code that uses (does not use) the instructions to move data +between the general purpose registers and the vector/scalar (VSX) +registers that were added in version 2.07 of the PowerPC ISA. + +@item -mpower8-fusion +@itemx -mno-power8-fusion +@opindex mpower8-fusion +@opindex mno-power8-fusion +Generate code that keeps (does not keeps) some integer operations +adjacent so that the instructions can be fused together on power8 and +later processors. + +@item -mpower8-vector +@itemx -mno-power8-vector +@opindex mpower8-vector +@opindex mno-power8-vector +Generate code that uses (does not use) the vector and scalar +instructions that were added in version 2.07 of the PowerPC ISA. Also +enable the use of built-in functions that allow more direct access to +the vector instructions. + +@item -mquad-memory +@itemx -mno-quad-memory +@opindex mquad-memory +@opindex mno-quad-memory +Generate code that uses (does not use) the quad word memory +instructions. The @option{-mquad-memory} option requires use of +64-bit mode. + @item -mfloat-gprs=@var{yes/single/double/no} @itemx -mfloat-gprs @opindex mfloat-gprs @@ -19404,6 +19483,11 @@ later. @opindex mfix-at697f Enable the documented workaround for the single erratum of the Atmel AT697F processor (which corresponds to erratum #13 of the AT697E processor). + +@item -mfix-ut699 +@opindex mfix-ut699 +Enable the documented workarounds for the floating-point errata of the UT699 +processor. @end table These @samp{-m} options are supported in addition to the above |