summaryrefslogtreecommitdiff
path: root/gcc/config
diff options
context:
space:
mode:
Diffstat (limited to 'gcc/config')
-rw-r--r--gcc/config/alpha/alpha.c28
-rw-r--r--gcc/config/alpha/linux-unwind.h4
-rw-r--r--gcc/config/arm/arm.c5
-rw-r--r--gcc/config/arm/arm.h3
-rw-r--r--gcc/config/avr/avr-stdint.h66
-rw-r--r--gcc/config/bfin/linux-unwind.h6
-rw-r--r--gcc/config/i386/driver-i386.c15
-rw-r--r--gcc/config/i386/i386.c22
-rw-r--r--gcc/config/i386/i386.h9
-rw-r--r--gcc/config/i386/i386.md13
-rw-r--r--gcc/config/i386/linux-unwind.h7
-rw-r--r--gcc/config/i386/sse.md53
-rw-r--r--gcc/config/ia64/linux-unwind.h6
-rw-r--r--gcc/config/mips/linux-unwind.h5
-rw-r--r--gcc/config/pa/linux-unwind.h4
-rw-r--r--gcc/config/pa/pa.c29
-rw-r--r--gcc/config/pa/pa.h9
-rw-r--r--gcc/config/rs6000/altivec.md16
-rw-r--r--gcc/config/rs6000/rs6000.c28
-rw-r--r--gcc/config/rs6000/rs6000.h9
-rw-r--r--gcc/config/rs6000/rs6000.md52
-rw-r--r--gcc/config/sh/linux-unwind.h9
-rw-r--r--gcc/config/sh/sh.c11
-rw-r--r--gcc/config/sh/sh.opt2
-rw-r--r--gcc/config/xtensa/linux-unwind.h4
25 files changed, 265 insertions, 150 deletions
diff --git a/gcc/config/alpha/alpha.c b/gcc/config/alpha/alpha.c
index 34ec9674727..2f4873eb6c2 100644
--- a/gcc/config/alpha/alpha.c
+++ b/gcc/config/alpha/alpha.c
@@ -2469,7 +2469,7 @@ alpha_emit_conditional_branch (rtx operands[], enum machine_mode cmp_mode)
{
case EQ: case LE: case LT: case LEU: case LTU:
case UNORDERED:
- /* We have these compares: */
+ /* We have these compares. */
cmp_code = code, branch_code = NE;
break;
@@ -2706,13 +2706,15 @@ alpha_emit_conditional_move (rtx cmp, enum machine_mode mode)
switch (code)
{
case EQ: case LE: case LT: case LEU: case LTU:
+ case UNORDERED:
/* We have these compares. */
cmp_code = code, code = NE;
break;
case NE:
- /* This must be reversed. */
- cmp_code = EQ, code = EQ;
+ case ORDERED:
+ /* These must be reversed. */
+ cmp_code = reverse_condition (code), code = EQ;
break;
case GE: case GT: case GEU: case GTU:
@@ -2732,6 +2734,14 @@ alpha_emit_conditional_move (rtx cmp, enum machine_mode mode)
gcc_unreachable ();
}
+ if (cmp_mode == DImode)
+ {
+ if (!reg_or_0_operand (op0, DImode))
+ op0 = force_reg (DImode, op0);
+ if (!reg_or_8bit_operand (op1, DImode))
+ op1 = force_reg (DImode, op1);
+ }
+
tem = gen_reg_rtx (cmp_mode);
emit_insn (gen_rtx_SET (VOIDmode, tem,
gen_rtx_fmt_ee (cmp_code, cmp_mode,
@@ -2743,6 +2753,14 @@ alpha_emit_conditional_move (rtx cmp, enum machine_mode mode)
local_fast_math = 1;
}
+ if (cmp_mode == DImode)
+ {
+ if (!reg_or_0_operand (op0, DImode))
+ op0 = force_reg (DImode, op0);
+ if (!reg_or_8bit_operand (op1, DImode))
+ op1 = force_reg (DImode, op1);
+ }
+
/* We may be able to use a conditional move directly.
This avoids emitting spurious compares. */
if (signed_comparison_operator (cmp, VOIDmode)
@@ -2761,11 +2779,13 @@ alpha_emit_conditional_move (rtx cmp, enum machine_mode mode)
switch (code)
{
case EQ: case LE: case LT: case LEU: case LTU:
+ case UNORDERED:
/* We have these compares: */
break;
case NE:
- /* This must be reversed. */
+ case ORDERED:
+ /* These must be reversed. */
code = reverse_condition (code);
cmov_code = EQ;
break;
diff --git a/gcc/config/alpha/linux-unwind.h b/gcc/config/alpha/linux-unwind.h
index 4c811dca4bf..8c04b3b415f 100644
--- a/gcc/config/alpha/linux-unwind.h
+++ b/gcc/config/alpha/linux-unwind.h
@@ -1,5 +1,5 @@
/* DWARF2 EH unwinding support for Alpha Linux.
- Copyright (C) 2004, 2005, 2009, 2011 Free Software Foundation, Inc.
+ Copyright (C) 2004, 2005, 2009, 2011, 2012 Free Software Foundation, Inc.
This file is part of GCC.
@@ -49,7 +49,7 @@ alpha_fallback_frame_state (struct _Unwind_Context *context,
else if (pc[1] == 0x201f015f) /* lda $0,NR_rt_sigreturn */
{
struct rt_sigframe {
- struct siginfo info;
+ siginfo_t info;
struct ucontext uc;
} *rt_ = context->cfa;
sc = &rt_->uc.uc_mcontext;
diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c
index a5edf04b9ed..db2d723ba97 100644
--- a/gcc/config/arm/arm.c
+++ b/gcc/config/arm/arm.c
@@ -23423,8 +23423,11 @@ arm_output_sync_loop (emit_f emit,
}
}
- arm_process_output_memory_barrier (emit, NULL);
+ /* Note: label is before barrier so that in cmp failure case we still get
+ a barrier to stop subsequent loads floating upwards past the ldrex
+ PR target/48126. */
arm_output_asm_insn (emit, 1, operands, "%sLSYB%%=:", LOCAL_LABEL_PREFIX);
+ arm_process_output_memory_barrier (emit, NULL);
}
static rtx
diff --git a/gcc/config/arm/arm.h b/gcc/config/arm/arm.h
index 151d3141381..292b48f96de 100644
--- a/gcc/config/arm/arm.h
+++ b/gcc/config/arm/arm.h
@@ -294,7 +294,8 @@ extern void (*arm_lang_output_object_attributes_hook)(void);
#define TARGET_HAVE_DMB (arm_arch7)
/* Nonzero if this chip implements a memory barrier via CP15. */
-#define TARGET_HAVE_DMB_MCR (arm_arch6k && ! TARGET_HAVE_DMB)
+#define TARGET_HAVE_DMB_MCR (arm_arch6 && ! TARGET_HAVE_DMB \
+ && ! TARGET_THUMB1)
/* Nonzero if this chip implements a memory barrier instruction. */
#define TARGET_HAVE_MEMORY_BARRIER (TARGET_HAVE_DMB || TARGET_HAVE_DMB_MCR)
diff --git a/gcc/config/avr/avr-stdint.h b/gcc/config/avr/avr-stdint.h
new file mode 100644
index 00000000000..c3ec3ce9fd5
--- /dev/null
+++ b/gcc/config/avr/avr-stdint.h
@@ -0,0 +1,66 @@
+/* Definitions for <stdint.h> types on systems using newlib.
+ Copyright (C) 2012 Free Software Foundation, Inc.
+
+This file is part of GCC.
+
+GCC is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 3, or (at your option)
+any later version.
+
+GCC is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with GCC; see the file COPYING3. If not see
+<http://www.gnu.org/licenses/>. */
+
+/*
+ The intention of this file is to supply definitions that work with
+ avr-gcc's -mint8 that sets int to an 8-bit type.
+
+ This file is intended to yield the same results as newlib-stdint.h,
+ but there are some differences to newlib-stdint.h:
+
+ - AVR is an 8-bit architecture that cannot access 16-bit values
+ atomically, this SIG_ATOMIC_TYPE is "char".
+
+ - For the same reason, [u]int_fast8_t is defined as 8-bit type.
+
+*/
+
+#define SIG_ATOMIC_TYPE "char"
+
+#define INT8_TYPE "signed char"
+#define INT16_TYPE (INT_TYPE_SIZE == 16 ? "short int" : "long int")
+#define INT32_TYPE (INT_TYPE_SIZE == 16 ? "long int" : "long long int")
+#define INT64_TYPE (INT_TYPE_SIZE == 16 ? "long long int" : 0)
+#define UINT8_TYPE "unsigned char"
+#define UINT16_TYPE (INT_TYPE_SIZE == 16 ? "short unsigned int" : "long unsigned int")
+#define UINT32_TYPE (INT_TYPE_SIZE == 16 ? "long unsigned int" : "long long unsigned int")
+#define UINT64_TYPE (INT_TYPE_SIZE == 16 ? "long long unsigned int" : 0)
+
+#define INT_LEAST8_TYPE INT8_TYPE
+#define INT_LEAST16_TYPE INT16_TYPE
+#define INT_LEAST32_TYPE INT32_TYPE
+#define INT_LEAST64_TYPE INT64_TYPE
+#define UINT_LEAST8_TYPE UINT8_TYPE
+#define UINT_LEAST16_TYPE UINT16_TYPE
+#define UINT_LEAST32_TYPE UINT32_TYPE
+#define UINT_LEAST64_TYPE UINT64_TYPE
+
+#define INT_FAST8_TYPE INT8_TYPE
+#define INT_FAST16_TYPE (INT_TYPE_SIZE == 16 ? "int" : INT16_TYPE)
+#define INT_FAST32_TYPE INT32_TYPE
+#define INT_FAST64_TYPE INT64_TYPE
+#define UINT_FAST8_TYPE UINT8_TYPE
+#define UINT_FAST16_TYPE (INT_TYPE_SIZE == 16 ? "unsigned int" : UINT16_TYPE)
+#define UINT_FAST32_TYPE UINT32_TYPE
+#define UINT_FAST64_TYPE UINT64_TYPE
+
+#define INTPTR_TYPE PTRDIFF_TYPE
+#ifndef UINTPTR_TYPE
+#define UINTPTR_TYPE SIZE_TYPE
+#endif
diff --git a/gcc/config/bfin/linux-unwind.h b/gcc/config/bfin/linux-unwind.h
index 88c8285632d..15bb2f12b69 100644
--- a/gcc/config/bfin/linux-unwind.h
+++ b/gcc/config/bfin/linux-unwind.h
@@ -1,5 +1,5 @@
/* DWARF2 EH unwinding support for Blackfin.
- Copyright (C) 2007, 2009 Free Software Foundation, Inc.
+ Copyright (C) 2007, 2009, 2012 Free Software Foundation, Inc.
This file is part of GCC.
@@ -48,10 +48,10 @@ bfin_fallback_frame_state (struct _Unwind_Context *context,
{
struct rt_sigframe {
int sig;
- struct siginfo *pinfo;
+ siginfo_t *pinfo;
void *puc;
char retcode[8];
- struct siginfo info;
+ siginfo_t info;
struct ucontext uc;
} *rt_ = context->cfa;
diff --git a/gcc/config/i386/driver-i386.c b/gcc/config/i386/driver-i386.c
index 0b5fd99d4d0..1871ae48504 100644
--- a/gcc/config/i386/driver-i386.c
+++ b/gcc/config/i386/driver-i386.c
@@ -397,6 +397,7 @@ const char *host_detect_local_cpu (int argc, const char **argv)
unsigned int has_pclmul = 0, has_abm = 0, has_lwp = 0;
unsigned int has_fma = 0, has_fma4 = 0, has_xop = 0;
unsigned int has_bmi = 0, has_tbm = 0;
+ unsigned int has_rdrnd = 0, has_f16c = 0, has_fsgsbase = 0;
bool arch;
@@ -444,6 +445,8 @@ const char *host_detect_local_cpu (int argc, const char **argv)
has_aes = ecx & bit_AES;
has_pclmul = ecx & bit_PCLMUL;
has_fma = ecx & bit_FMA;
+ has_f16c = ecx & bit_F16C;
+ has_rdrnd = ecx & bit_RDRND;
has_cmpxchg8b = edx & bit_CMPXCHG8B;
has_cmov = edx & bit_CMOV;
@@ -451,6 +454,13 @@ const char *host_detect_local_cpu (int argc, const char **argv)
has_sse = edx & bit_SSE;
has_sse2 = edx & bit_SSE2;
+ if (max_level >= 7)
+ {
+ __cpuid_count (7, 0, eax, ebx, ecx, edx);
+
+ has_fsgsbase = ebx & bit_FSGSBASE;
+ }
+
/* Check cpuid level of extended features. */
__cpuid (0x80000000, ext_level, ebx, ecx, edx);
@@ -711,10 +721,13 @@ const char *host_detect_local_cpu (int argc, const char **argv)
const char *avx = has_avx ? " -mavx" : " -mno-avx";
const char *sse4_2 = has_sse4_2 ? " -msse4.2" : " -mno-sse4.2";
const char *sse4_1 = has_sse4_1 ? " -msse4.1" : " -mno-sse4.1";
+ const char *rdrnd = has_rdrnd ? " -mrdrnd" : " -mno-rdrnd";
+ const char *f16c = has_f16c ? " -mf16c" : " -mno-f16c";
+ const char *fsgsbase = has_fsgsbase ? " -mfsgsbase" : " -mno-fsgsbase";
options = concat (options, cx16, sahf, movbe, ase, pclmul,
popcnt, abm, lwp, fma, fma4, xop, bmi, tbm,
- avx, sse4_2, sse4_1, NULL);
+ avx, sse4_2, sse4_1, rdrnd, f16c, fsgsbase, NULL);
}
done:
diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c
index e98c4dd2dcc..aa51739c884 100644
--- a/gcc/config/i386/i386.c
+++ b/gcc/config/i386/i386.c
@@ -2095,7 +2095,7 @@ unsigned char ix86_arch_features[X86_ARCH_LAST];
/* Feature tests against the various architecture variations, used to create
ix86_arch_features based on the processor mask. */
static unsigned int initial_ix86_arch_features[X86_ARCH_LAST] = {
- /* X86_ARCH_CMOVE: Conditional move was added for pentiumpro. */
+ /* X86_ARCH_CMOV: Conditional move was added for pentiumpro. */
~(m_386 | m_486 | m_PENT | m_K6),
/* X86_ARCH_CMPXCHG: Compare and exchange was added for 80486. */
@@ -3884,7 +3884,7 @@ ix86_option_override_internal (bool main_args_p)
-mtune (rather than -march) points us to a processor that has them.
However, the VIA C3 gives a SIGILL, so we only do that for i686 and
higher processors. */
- if (TARGET_CMOVE
+ if (TARGET_CMOV
&& (processor_alias_table[i].flags & (PTA_PREFETCH_SSE | PTA_SSE)))
x86_prefetch_sse = true;
break;
@@ -4254,12 +4254,6 @@ ix86_option_override_internal (bool main_args_p)
target_flags |= MASK_ACCUMULATE_OUTGOING_ARGS;
}
- /* For sane SSE instruction set generation we need fcomi instruction.
- It is safe to enable all CMOVE instructions. Also, RDRAND intrinsic
- expands to a sequence that includes conditional move. */
- if (TARGET_SSE || TARGET_RDRND)
- TARGET_CMOVE = 1;
-
/* Figure out what ASM_GENERATE_INTERNAL_LABEL builds as a prefix. */
{
char *p;
@@ -27446,8 +27440,8 @@ ix86_expand_special_args_builtin (const struct builtin_description *d,
arg_adjust = 0;
if (optimize
|| target == 0
- || GET_MODE (target) != tmode
- || !insn_p->operand[0].predicate (target, tmode))
+ || !register_operand (target, tmode)
+ || GET_MODE (target) != tmode)
target = gen_reg_rtx (tmode);
}
@@ -31646,9 +31640,9 @@ ix86_expand_vector_set (bool mmx_ok, rtx target, rtx val, int elt)
tmp = gen_reg_rtx (GET_MODE_INNER (mode));
ix86_expand_vector_extract (true, tmp, target, 1 - elt);
if (elt == 0)
- tmp = gen_rtx_VEC_CONCAT (mode, tmp, val);
- else
tmp = gen_rtx_VEC_CONCAT (mode, val, tmp);
+ else
+ tmp = gen_rtx_VEC_CONCAT (mode, tmp, val);
emit_insn (gen_rtx_SET (VOIDmode, target, tmp));
return;
}
@@ -31662,9 +31656,9 @@ ix86_expand_vector_set (bool mmx_ok, rtx target, rtx val, int elt)
tmp = gen_reg_rtx (GET_MODE_INNER (mode));
ix86_expand_vector_extract (false, tmp, target, 1 - elt);
if (elt == 0)
- tmp = gen_rtx_VEC_CONCAT (mode, tmp, val);
- else
tmp = gen_rtx_VEC_CONCAT (mode, val, tmp);
+ else
+ tmp = gen_rtx_VEC_CONCAT (mode, tmp, val);
emit_insn (gen_rtx_SET (VOIDmode, target, tmp));
return;
diff --git a/gcc/config/i386/i386.h b/gcc/config/i386/i386.h
index 030b72d0b58..67cae2cc85b 100644
--- a/gcc/config/i386/i386.h
+++ b/gcc/config/i386/i386.h
@@ -426,7 +426,7 @@ extern unsigned char ix86_tune_features[X86_TUNE_LAST];
/* Feature tests against the various architecture variations. */
enum ix86_arch_indices {
- X86_ARCH_CMOVE, /* || TARGET_SSE */
+ X86_ARCH_CMOV,
X86_ARCH_CMPXCHG,
X86_ARCH_CMPXCHG8B,
X86_ARCH_XADD,
@@ -437,12 +437,17 @@ enum ix86_arch_indices {
extern unsigned char ix86_arch_features[X86_ARCH_LAST];
-#define TARGET_CMOVE ix86_arch_features[X86_ARCH_CMOVE]
+#define TARGET_CMOV ix86_arch_features[X86_ARCH_CMOV]
#define TARGET_CMPXCHG ix86_arch_features[X86_ARCH_CMPXCHG]
#define TARGET_CMPXCHG8B ix86_arch_features[X86_ARCH_CMPXCHG8B]
#define TARGET_XADD ix86_arch_features[X86_ARCH_XADD]
#define TARGET_BSWAP ix86_arch_features[X86_ARCH_BSWAP]
+/* For sane SSE instruction set generation we need fcomi instruction.
+ It is safe to enable all CMOVE instructions. Also, RDRAND intrinsic
+ expands to a sequence that includes conditional move. */
+#define TARGET_CMOVE (TARGET_CMOV || TARGET_SSE || TARGET_RDRND)
+
#define TARGET_FISTTP (TARGET_SSE3 && TARGET_80387)
extern int x86_prefetch_sse;
diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md
index 3010977075c..1251458658f 100644
--- a/gcc/config/i386/i386.md
+++ b/gcc/config/i386/i386.md
@@ -233,9 +233,6 @@
;; For BMI support
UNSPEC_BEXTR
-
- ;; For RDRAND support
- UNSPEC_RDRAND
])
(define_c_enum "unspecv" [
@@ -270,6 +267,9 @@
UNSPECV_WRFSBASE
UNSPECV_WRGSBASE
UNSPECV_SPLIT_STACK_RETURN
+
+ ;; For RDRAND support
+ UNSPECV_RDRAND
])
;; Constants to represent pcomtrue/pcomfalse variants
@@ -16407,7 +16407,8 @@
(define_insn "*x86_mov<mode>cc_0_m1_neg"
[(set (match_operand:SWI48 0 "register_operand" "=r")
(neg:SWI48 (match_operator 1 "ix86_carry_flag_operator"
- [(reg FLAGS_REG) (const_int 0)])))]
+ [(reg FLAGS_REG) (const_int 0)])))
+ (clobber (reg:CC FLAGS_REG))]
""
"sbb{<imodesuffix>}\t%0, %0"
[(set_attr "type" "alu")
@@ -18415,9 +18416,9 @@
(define_insn "rdrand<mode>_1"
[(set (match_operand:SWI248 0 "register_operand" "=r")
- (unspec:SWI248 [(const_int 0)] UNSPEC_RDRAND))
+ (unspec_volatile:SWI248 [(const_int 0)] UNSPECV_RDRAND))
(set (reg:CCC FLAGS_REG)
- (unspec:CCC [(const_int 0)] UNSPEC_RDRAND))]
+ (unspec_volatile:CCC [(const_int 0)] UNSPECV_RDRAND))]
"TARGET_RDRND"
"rdrand\t%0"
[(set_attr "type" "other")
diff --git a/gcc/config/i386/linux-unwind.h b/gcc/config/i386/linux-unwind.h
index c5f7ea0e873..9e4be80109b 100644
--- a/gcc/config/i386/linux-unwind.h
+++ b/gcc/config/i386/linux-unwind.h
@@ -1,5 +1,6 @@
/* DWARF2 EH unwinding support for AMD x86-64 and x86.
- Copyright (C) 2004, 2005, 2006, 2009, 2010 Free Software Foundation, Inc.
+ Copyright (C) 2004, 2005, 2006, 2009, 2010, 2012 Free Software Foundation,
+ Inc.
This file is part of GCC.
@@ -133,9 +134,9 @@ x86_fallback_frame_state (struct _Unwind_Context *context,
{
struct rt_sigframe {
int sig;
- struct siginfo *pinfo;
+ siginfo_t *pinfo;
void *puc;
- struct siginfo info;
+ siginfo_t info;
struct ucontext uc;
} *rt_ = context->cfa;
/* The void * cast is necessary to avoid an aliasing warning.
diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md
index 1c61dbb3ade..938c073df90 100644
--- a/gcc/config/i386/sse.md
+++ b/gcc/config/i386/sse.md
@@ -392,18 +392,7 @@
DONE;
})
-(define_expand "avx_movu<ssemodesuffix><avxmodesuffix>"
- [(set (match_operand:AVXMODEF2P 0 "nonimmediate_operand" "")
- (unspec:AVXMODEF2P
- [(match_operand:AVXMODEF2P 1 "nonimmediate_operand" "")]
- UNSPEC_MOVU))]
- "AVX_VEC_FLOAT_MODE_P (<MODE>mode)"
-{
- if (MEM_P (operands[0]) && MEM_P (operands[1]))
- operands[1] = force_reg (<MODE>mode, operands[1]);
-})
-
-(define_insn "*avx_movu<ssemodesuffix><avxmodesuffix>"
+(define_insn "avx_movu<ssemodesuffix><avxmodesuffix>"
[(set (match_operand:AVXMODEF2P 0 "nonimmediate_operand" "=x,m")
(unspec:AVXMODEF2P
[(match_operand:AVXMODEF2P 1 "nonimmediate_operand" "xm,x")]
@@ -429,18 +418,7 @@
(set_attr "prefix" "maybe_vex")
(set_attr "mode" "TI")])
-(define_expand "<sse>_movu<ssemodesuffix>"
- [(set (match_operand:SSEMODEF2P 0 "nonimmediate_operand" "")
- (unspec:SSEMODEF2P
- [(match_operand:SSEMODEF2P 1 "nonimmediate_operand" "")]
- UNSPEC_MOVU))]
- "SSE_VEC_FLOAT_MODE_P (<MODE>mode)"
-{
- if (MEM_P (operands[0]) && MEM_P (operands[1]))
- operands[1] = force_reg (<MODE>mode, operands[1]);
-})
-
-(define_insn "*<sse>_movu<ssemodesuffix>"
+(define_insn "<sse>_movu<ssemodesuffix>"
[(set (match_operand:SSEMODEF2P 0 "nonimmediate_operand" "=x,m")
(unspec:SSEMODEF2P
[(match_operand:SSEMODEF2P 1 "nonimmediate_operand" "xm,x")]
@@ -452,18 +430,7 @@
(set_attr "movu" "1")
(set_attr "mode" "<MODE>")])
-(define_expand "avx_movdqu<avxmodesuffix>"
- [(set (match_operand:AVXMODEQI 0 "nonimmediate_operand" "")
- (unspec:AVXMODEQI
- [(match_operand:AVXMODEQI 1 "nonimmediate_operand" "")]
- UNSPEC_MOVU))]
- "TARGET_AVX"
-{
- if (MEM_P (operands[0]) && MEM_P (operands[1]))
- operands[1] = force_reg (<MODE>mode, operands[1]);
-})
-
-(define_insn "*avx_movdqu<avxmodesuffix>"
+(define_insn "avx_movdqu<avxmodesuffix>"
[(set (match_operand:AVXMODEQI 0 "nonimmediate_operand" "=x,m")
(unspec:AVXMODEQI
[(match_operand:AVXMODEQI 1 "nonimmediate_operand" "xm,x")]
@@ -475,17 +442,7 @@
(set_attr "prefix" "vex")
(set_attr "mode" "<avxvecmode>")])
-(define_expand "sse2_movdqu"
- [(set (match_operand:V16QI 0 "nonimmediate_operand" "")
- (unspec:V16QI [(match_operand:V16QI 1 "nonimmediate_operand" "")]
- UNSPEC_MOVU))]
- "TARGET_SSE2"
-{
- if (MEM_P (operands[0]) && MEM_P (operands[1]))
- operands[1] = force_reg (V16QImode, operands[1]);
-})
-
-(define_insn "*sse2_movdqu"
+(define_insn "sse2_movdqu"
[(set (match_operand:V16QI 0 "nonimmediate_operand" "=x,m")
(unspec:V16QI [(match_operand:V16QI 1 "nonimmediate_operand" "xm,x")]
UNSPEC_MOVU))]
@@ -12095,7 +12052,7 @@
(unspec:V8SF [(match_operand:V8HI 1 "register_operand" "x")]
UNSPEC_VCVTPH2PS)
(parallel [(const_int 0) (const_int 1)
- (const_int 1) (const_int 2)])))]
+ (const_int 2) (const_int 3)])))]
"TARGET_F16C"
"vcvtph2ps\t{%1, %0|%0, %1}"
[(set_attr "type" "ssecvt")
diff --git a/gcc/config/ia64/linux-unwind.h b/gcc/config/ia64/linux-unwind.h
index 93f762de573..da31259782b 100644
--- a/gcc/config/ia64/linux-unwind.h
+++ b/gcc/config/ia64/linux-unwind.h
@@ -1,5 +1,5 @@
/* DWARF2 EH unwinding support for IA64 Linux.
- Copyright (C) 2004, 2005, 2009 Free Software Foundation, Inc.
+ Copyright (C) 2004, 2005, 2009, 2012 Free Software Foundation, Inc.
This file is part of GCC.
@@ -47,7 +47,7 @@ ia64_fallback_frame_state (struct _Unwind_Context *context,
struct sigframe {
char scratch[16];
unsigned long sig_number;
- struct siginfo *info;
+ siginfo_t *info;
struct sigcontext *sc;
} *frame_ = (struct sigframe *)context->psp;
struct sigcontext *sc = frame_->sc;
@@ -137,7 +137,7 @@ ia64_handle_unwabi (struct _Unwind_Context *context, _Unwind_FrameState *fs)
struct sigframe {
char scratch[16];
unsigned long sig_number;
- struct siginfo *info;
+ siginfo_t *info;
struct sigcontext *sc;
} *frame = (struct sigframe *)context->psp;
struct sigcontext *sc = frame->sc;
diff --git a/gcc/config/mips/linux-unwind.h b/gcc/config/mips/linux-unwind.h
index 02f7cd54c5a..094ff58cb03 100644
--- a/gcc/config/mips/linux-unwind.h
+++ b/gcc/config/mips/linux-unwind.h
@@ -1,5 +1,6 @@
/* DWARF2 EH unwinding support for MIPS Linux.
- Copyright (C) 2004, 2005, 2006, 2007, 2008, 2009 Free Software Foundation, Inc.
+ Copyright (C) 2004, 2005, 2006, 2007, 2008, 2009, 2012 Free Software
+ Foundation, Inc.
This file is part of GCC.
@@ -75,7 +76,7 @@ mips_fallback_frame_state (struct _Unwind_Context *context,
struct rt_sigframe {
u_int32_t ass[4]; /* Argument save space for o32. */
u_int32_t trampoline[2];
- struct siginfo info;
+ siginfo_t info;
_sig_ucontext_t uc;
} *rt_ = context->cfa;
sc = &rt_->uc.uc_mcontext;
diff --git a/gcc/config/pa/linux-unwind.h b/gcc/config/pa/linux-unwind.h
index a0560e97445..38b4eda7aee 100644
--- a/gcc/config/pa/linux-unwind.h
+++ b/gcc/config/pa/linux-unwind.h
@@ -1,5 +1,5 @@
/* DWARF2 EH unwinding support for PA Linux.
- Copyright (C) 2004, 2005, 2009 Free Software Foundation, Inc.
+ Copyright (C) 2004, 2005, 2009, 2012 Free Software Foundation, Inc.
This file is part of GCC.
@@ -63,7 +63,7 @@ pa32_fallback_frame_state (struct _Unwind_Context *context,
int i;
struct sigcontext *sc;
struct rt_sigframe {
- struct siginfo info;
+ siginfo_t info;
struct ucontext uc;
} *frame;
diff --git a/gcc/config/pa/pa.c b/gcc/config/pa/pa.c
index 5e5a0f05b79..83e6e859e78 100644
--- a/gcc/config/pa/pa.c
+++ b/gcc/config/pa/pa.c
@@ -185,6 +185,7 @@ static bool pa_can_eliminate (const int, const int);
static void pa_conditional_register_usage (void);
static enum machine_mode pa_c_mode_for_suffix (char);
static section *pa_function_section (tree, enum node_frequency, bool, bool);
+static unsigned int pa_section_type_flags (tree, const char *, int);
/* The following extra sections are only used for SOM. */
static GTY(()) section *som_readonly_data_section;
@@ -400,6 +401,9 @@ static const struct default_options pa_option_optimization_table[] =
#undef TARGET_ASM_FUNCTION_SECTION
#define TARGET_ASM_FUNCTION_SECTION pa_function_section
+#undef TARGET_SECTION_TYPE_FLAGS
+#define TARGET_SECTION_TYPE_FLAGS pa_section_type_flags
+
struct gcc_target targetm = TARGET_INITIALIZER;
/* Parse the -mfixed-range= option string. */
@@ -7540,7 +7544,7 @@ attr_length_millicode_call (rtx insn)
return 24;
else
{
- if (!TARGET_LONG_CALLS && distance < 240000)
+ if (!TARGET_LONG_CALLS && distance < MAX_PCREL17F_OFFSET)
return 8;
if (TARGET_LONG_ABS_CALL && !flag_pic)
@@ -7753,7 +7757,7 @@ attr_length_call (rtx insn, int sibcall)
/* pc-relative branch. */
if (!TARGET_LONG_CALLS
&& ((TARGET_PA_20 && !sibcall && distance < 7600000)
- || distance < 240000))
+ || distance < MAX_PCREL17F_OFFSET))
length += 8;
/* 64-bit plabel sequence. */
@@ -8112,7 +8116,7 @@ attr_length_indirect_call (rtx insn)
if (TARGET_FAST_INDIRECT_CALLS
|| (!TARGET_PORTABLE_RUNTIME
&& ((TARGET_PA_20 && !TARGET_SOM && distance < 7600000)
- || distance < 240000)))
+ || distance < MAX_PCREL17F_OFFSET)))
return 8;
if (flag_pic)
@@ -10431,4 +10435,23 @@ pa_function_section (tree decl, enum node_frequency freq,
return default_function_section (decl, freq, startup, exit);
}
+/* Implement TARGET_SECTION_TYPE_FLAGS. */
+
+static unsigned int
+pa_section_type_flags (tree decl, const char *name, int reloc)
+{
+ unsigned int flags;
+
+ flags = default_section_type_flags (decl, name, reloc);
+
+ /* Function labels are placed in the constant pool. This can
+ cause a section conflict if decls are put in ".data.rel.ro"
+ or ".data.rel.ro.local" using the __attribute__ construct. */
+ if (strcmp (name, ".data.rel.ro") == 0
+ || strcmp (name, ".data.rel.ro.local") == 0)
+ flags |= SECTION_WRITE | SECTION_RELRO;
+
+ return flags;
+}
+
#include "gt-pa.h"
diff --git a/gcc/config/pa/pa.h b/gcc/config/pa/pa.h
index 012186854de..e59cd5d4578 100644
--- a/gcc/config/pa/pa.h
+++ b/gcc/config/pa/pa.h
@@ -1563,3 +1563,12 @@ do { \
#undef TARGET_HAVE_TLS
#define TARGET_HAVE_TLS true
#endif
+
+/* The maximum offset in bytes for a PA 1.X pc-relative call to the
+ head of the preceding stub table. The selected offsets have been
+ chosen so that approximately one call stub is allocated for every
+ 86.7 instructions. A long branch stub is two instructions when
+ not generating PIC code. For HP-UX and ELF targets, PIC stubs are
+ seven and four instructions, respectively. */
+#define MAX_PCREL17F_OFFSET \
+ (flag_pic ? (TARGET_HPUX ? 198164 : 221312) : 240000)
diff --git a/gcc/config/rs6000/altivec.md b/gcc/config/rs6000/altivec.md
index 80e82cc9c29..9fbced17365 100644
--- a/gcc/config/rs6000/altivec.md
+++ b/gcc/config/rs6000/altivec.md
@@ -2394,8 +2394,8 @@
(define_insn "altivec_stvlx"
[(parallel
- [(set (match_operand:V4SI 0 "memory_operand" "=Z")
- (match_operand:V4SI 1 "register_operand" "v"))
+ [(set (match_operand:V16QI 0 "memory_operand" "=Z")
+ (match_operand:V16QI 1 "register_operand" "v"))
(unspec [(const_int 0)] UNSPEC_STVLX)])]
"TARGET_ALTIVEC && rs6000_cpu == PROCESSOR_CELL"
"stvlx %1,%y0"
@@ -2403,8 +2403,8 @@
(define_insn "altivec_stvlxl"
[(parallel
- [(set (match_operand:V4SI 0 "memory_operand" "=Z")
- (match_operand:V4SI 1 "register_operand" "v"))
+ [(set (match_operand:V16QI 0 "memory_operand" "=Z")
+ (match_operand:V16QI 1 "register_operand" "v"))
(unspec [(const_int 0)] UNSPEC_STVLXL)])]
"TARGET_ALTIVEC && rs6000_cpu == PROCESSOR_CELL"
"stvlxl %1,%y0"
@@ -2412,8 +2412,8 @@
(define_insn "altivec_stvrx"
[(parallel
- [(set (match_operand:V4SI 0 "memory_operand" "=Z")
- (match_operand:V4SI 1 "register_operand" "v"))
+ [(set (match_operand:V16QI 0 "memory_operand" "=Z")
+ (match_operand:V16QI 1 "register_operand" "v"))
(unspec [(const_int 0)] UNSPEC_STVRX)])]
"TARGET_ALTIVEC && rs6000_cpu == PROCESSOR_CELL"
"stvrx %1,%y0"
@@ -2421,8 +2421,8 @@
(define_insn "altivec_stvrxl"
[(parallel
- [(set (match_operand:V4SI 0 "memory_operand" "=Z")
- (match_operand:V4SI 1 "register_operand" "v"))
+ [(set (match_operand:V16QI 0 "memory_operand" "=Z")
+ (match_operand:V16QI 1 "register_operand" "v"))
(unspec [(const_int 0)] UNSPEC_STVRXL)])]
"TARGET_ALTIVEC && rs6000_cpu == PROCESSOR_CELL"
"stvrxl %1,%y0"
diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c
index 5c101a51aff..36aba430eb9 100644
--- a/gcc/config/rs6000/rs6000.c
+++ b/gcc/config/rs6000/rs6000.c
@@ -15822,7 +15822,6 @@ void
print_operand (FILE *file, rtx x, int code)
{
int i;
- HOST_WIDE_INT val;
unsigned HOST_WIDE_INT uval;
switch (code)
@@ -16263,34 +16262,17 @@ print_operand (FILE *file, rtx x, int code)
case 'W':
/* MB value for a PowerPC64 rldic operand. */
- val = (GET_CODE (x) == CONST_INT
- ? INTVAL (x) : CONST_DOUBLE_HIGH (x));
-
- if (val < 0)
- i = -1;
- else
- for (i = 0; i < HOST_BITS_PER_WIDE_INT; i++)
- if ((val <<= 1) < 0)
- break;
+ i = clz_hwi (GET_CODE (x) == CONST_INT
+ ? INTVAL (x) : CONST_DOUBLE_HIGH (x));
#if HOST_BITS_PER_WIDE_INT == 32
- if (GET_CODE (x) == CONST_INT && i >= 0)
+ if (GET_CODE (x) == CONST_INT && i > 0)
i += 32; /* zero-extend high-part was all 0's */
else if (GET_CODE (x) == CONST_DOUBLE && i == 32)
- {
- val = CONST_DOUBLE_LOW (x);
-
- gcc_assert (val);
- if (val < 0)
- --i;
- else
- for ( ; i < 64; i++)
- if ((val <<= 1) < 0)
- break;
- }
+ i = clz_hwi (CONST_DOUBLE_LOW (x)) + 32;
#endif
- fprintf (file, "%d", i + 1);
+ fprintf (file, "%d", i);
return;
case 'x':
diff --git a/gcc/config/rs6000/rs6000.h b/gcc/config/rs6000/rs6000.h
index a8d42398ec5..0eae3265a0f 100644
--- a/gcc/config/rs6000/rs6000.h
+++ b/gcc/config/rs6000/rs6000.h
@@ -469,10 +469,11 @@ extern int rs6000_vector_align[];
/* ISA 2.01 allowed FCFID to be done in 32-bit, previously it was 64-bit only.
Enable 32-bit fcfid's on any of the switches for newer ISA machines or
XILINX. */
-#define TARGET_FCFID (TARGET_POWERPC64 \
- || TARGET_POPCNTB /* ISA 2.02 */ \
- || TARGET_CMPB /* ISA 2.05 */ \
- || TARGET_POPCNTD /* ISA 2.06 */ \
+#define TARGET_FCFID (TARGET_POWERPC64 \
+ || TARGET_PPC_GPOPT /* 970/power4 */ \
+ || TARGET_POPCNTB /* ISA 2.02 */ \
+ || TARGET_CMPB /* ISA 2.05 */ \
+ || TARGET_POPCNTD /* ISA 2.06 */ \
|| TARGET_XILINX_FPU)
#define TARGET_FCTIDZ TARGET_FCFID
diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index 16be86c27a4..7befb56a378 100644
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -2524,7 +2524,18 @@
if (GET_CODE (addr1) == PLUS)
{
emit_insn (gen_add3_insn (op2, XEXP (addr1, 0), GEN_INT (4)));
- addr2 = gen_rtx_PLUS (Pmode, op2, XEXP (addr1, 1));
+ if (TARGET_AVOID_XFORM)
+ {
+ emit_insn (gen_add3_insn (op2, XEXP (addr1, 1), op2));
+ addr2 = op2;
+ }
+ else
+ addr2 = gen_rtx_PLUS (Pmode, op2, XEXP (addr1, 1));
+ }
+ else if (TARGET_AVOID_XFORM)
+ {
+ emit_insn (gen_add3_insn (op2, addr1, GEN_INT (4)));
+ addr2 = op2;
}
else
{
@@ -2574,7 +2585,18 @@
if (GET_CODE (addr1) == PLUS)
{
emit_insn (gen_add3_insn (op2, XEXP (addr1, 0), GEN_INT (4)));
- addr2 = gen_rtx_PLUS (Pmode, op2, XEXP (addr1, 1));
+ if (TARGET_AVOID_XFORM)
+ {
+ emit_insn (gen_add3_insn (op2, XEXP (addr1, 1), op2));
+ addr2 = op2;
+ }
+ else
+ addr2 = gen_rtx_PLUS (Pmode, op2, XEXP (addr1, 1));
+ }
+ else if (TARGET_AVOID_XFORM)
+ {
+ emit_insn (gen_add3_insn (op2, addr1, GEN_INT (4)));
+ addr2 = op2;
}
else
{
@@ -2655,7 +2677,18 @@
if (GET_CODE (addr1) == PLUS)
{
emit_insn (gen_add3_insn (op2, XEXP (addr1, 0), GEN_INT (4)));
- addr2 = gen_rtx_PLUS (SImode, op2, XEXP (addr1, 1));
+ if (TARGET_AVOID_XFORM)
+ {
+ emit_insn (gen_add3_insn (op2, XEXP (addr1, 1), op2));
+ addr2 = op2;
+ }
+ else
+ addr2 = gen_rtx_PLUS (SImode, op2, XEXP (addr1, 1));
+ }
+ else if (TARGET_AVOID_XFORM)
+ {
+ emit_insn (gen_add3_insn (op2, addr1, GEN_INT (4)));
+ addr2 = op2;
}
else
{
@@ -2700,7 +2733,18 @@
if (GET_CODE (addr1) == PLUS)
{
emit_insn (gen_add3_insn (op2, XEXP (addr1, 0), GEN_INT (4)));
- addr2 = gen_rtx_PLUS (SImode, op2, XEXP (addr1, 1));
+ if (TARGET_AVOID_XFORM)
+ {
+ emit_insn (gen_add3_insn (op2, XEXP (addr1, 1), op2));
+ addr2 = op2;
+ }
+ else
+ addr2 = gen_rtx_PLUS (SImode, op2, XEXP (addr1, 1));
+ }
+ else if (TARGET_AVOID_XFORM)
+ {
+ emit_insn (gen_add3_insn (op2, addr1, GEN_INT (4)));
+ addr2 = op2;
}
else
{
diff --git a/gcc/config/sh/linux-unwind.h b/gcc/config/sh/linux-unwind.h
index 94ed95d55e1..5a78e3172aa 100644
--- a/gcc/config/sh/linux-unwind.h
+++ b/gcc/config/sh/linux-unwind.h
@@ -1,5 +1,6 @@
/* DWARF2 EH unwinding support for SH Linux.
- Copyright (C) 2004, 2005, 2006, 2007, 2009 Free Software Foundation, Inc.
+ Copyright (C) 2004, 2005, 2006, 2007, 2009, 2012 Free Software Foundation,
+ Inc.
This file is part of GCC.
@@ -80,9 +81,9 @@ shmedia_fallback_frame_state (struct _Unwind_Context *context,
&& (*(unsigned long *) (pc+11) == 0x6ff0fff0))
{
struct rt_sigframe {
- struct siginfo *pinfo;
+ siginfo_t *pinfo;
void *puc;
- struct siginfo info;
+ siginfo_t info;
struct ucontext uc;
} *rt_ = context->cfa;
/* The void * cast is necessary to avoid an aliasing warning.
@@ -179,7 +180,7 @@ sh_fallback_frame_state (struct _Unwind_Context *context,
&& (*(unsigned short *) (pc+14) == 0x00ad))))
{
struct rt_sigframe {
- struct siginfo info;
+ siginfo_t info;
struct ucontext uc;
} *rt_ = context->cfa;
/* The void * cast is necessary to avoid an aliasing warning.
diff --git a/gcc/config/sh/sh.c b/gcc/config/sh/sh.c
index 6ac593e839e..39ef00d265c 100644
--- a/gcc/config/sh/sh.c
+++ b/gcc/config/sh/sh.c
@@ -911,8 +911,6 @@ sh_option_override (void)
if (! VALID_REGISTER_P (ADDREGNAMES_REGNO (regno)))
sh_additional_register_names[regno][0] = '\0';
- flag_omit_frame_pointer = (PREFERRED_DEBUGGING_TYPE == DWARF2_DEBUG);
-
if ((flag_pic && ! TARGET_PREFERGOT)
|| (TARGET_SHMEDIA && !TARGET_PT_FIXED))
flag_no_function_cse = 1;
@@ -944,22 +942,17 @@ sh_option_override (void)
flag_schedule_insns = 0;
}
- if ((target_flags_explicit & MASK_ACCUMULATE_OUTGOING_ARGS) == 0)
- target_flags |= MASK_ACCUMULATE_OUTGOING_ARGS;
-
/* Unwind info is not correct around the CFG unless either a frame
pointer is present or M_A_O_A is set. Fixing this requires rewriting
unwind info generation to be aware of the CFG and propagating states
around edges. */
if ((flag_unwind_tables || flag_asynchronous_unwind_tables
|| flag_exceptions || flag_non_call_exceptions)
- && flag_omit_frame_pointer
- && !(target_flags & MASK_ACCUMULATE_OUTGOING_ARGS))
+ && flag_omit_frame_pointer && !TARGET_ACCUMULATE_OUTGOING_ARGS)
{
- if (target_flags_explicit & MASK_ACCUMULATE_OUTGOING_ARGS)
warning (0, "unwind tables currently require either a frame pointer "
"or -maccumulate-outgoing-args for correctness");
- target_flags |= MASK_ACCUMULATE_OUTGOING_ARGS;
+ TARGET_ACCUMULATE_OUTGOING_ARGS = 1;
}
/* Unwinding with -freorder-blocks-and-partition does not work on this
diff --git a/gcc/config/sh/sh.opt b/gcc/config/sh/sh.opt
index e94f53a5cbd..99a6373e20e 100644
--- a/gcc/config/sh/sh.opt
+++ b/gcc/config/sh/sh.opt
@@ -202,7 +202,7 @@ Target RejectNegative Condition(SUPPORT_SH5_32MEDIA_NOFPU)
Generate FPU-less SHcompact code
maccumulate-outgoing-args
-Target Report Mask(ACCUMULATE_OUTGOING_ARGS)
+Target Report Var(TARGET_ACCUMULATE_OUTGOING_ARGS) Init(1)
Reserve space for outgoing arguments in the function prologue
madjust-unroll
diff --git a/gcc/config/xtensa/linux-unwind.h b/gcc/config/xtensa/linux-unwind.h
index 32e93497287..24564972820 100644
--- a/gcc/config/xtensa/linux-unwind.h
+++ b/gcc/config/xtensa/linux-unwind.h
@@ -1,5 +1,5 @@
/* DWARF2 EH unwinding support for Xtensa.
- Copyright (C) 2008, 2009 Free Software Foundation, Inc.
+ Copyright (C) 2008, 2009, 2012 Free Software Foundation, Inc.
This file is part of GCC.
@@ -62,7 +62,7 @@ xtensa_fallback_frame_state (struct _Unwind_Context *context,
struct sigcontext *sc;
struct rt_sigframe {
- struct siginfo info;
+ siginfo_t info;
struct ucontext uc;
} *rt_;
View Lorry Controller Status