diff options
Diffstat (limited to 'gcc/config')
45 files changed, 1488 insertions, 658 deletions
diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c index 9af66dd8ace..5522fc12172 100644 --- a/gcc/config/arm/arm.c +++ b/gcc/config/arm/arm.c @@ -82,6 +82,7 @@ static int arm_legitimate_index_p (enum machine_mode, rtx, RTX_CODE, int); static int thumb2_legitimate_index_p (enum machine_mode, rtx, int); static int thumb1_base_register_rtx_p (rtx, enum machine_mode, int); static rtx arm_legitimize_address (rtx, rtx, enum machine_mode); +static reg_class_t arm_preferred_reload_class (rtx, reg_class_t); static rtx thumb_legitimize_address (rtx, rtx, enum machine_mode); inline static int thumb1_index_register_rtx_p (rtx, int); static bool arm_legitimate_address_p (enum machine_mode, rtx, bool); @@ -576,6 +577,9 @@ static const struct attribute_spec arm_attribute_table[] = #undef TARGET_LEGITIMATE_ADDRESS_P #define TARGET_LEGITIMATE_ADDRESS_P arm_legitimate_address_p +#undef TARGET_PREFERRED_RELOAD_CLASS +#define TARGET_PREFERRED_RELOAD_CLASS arm_preferred_reload_class + #undef TARGET_INVALID_PARAMETER_TYPE #define TARGET_INVALID_PARAMETER_TYPE arm_invalid_parameter_type @@ -6226,6 +6230,30 @@ arm_legitimate_address_p (enum machine_mode mode, rtx x, bool strict_p) return thumb1_legitimate_address_p (mode, x, strict_p); } +/* Worker function for TARGET_PREFERRED_RELOAD_CLASS. + + Given an rtx X being reloaded into a reg required to be + in class CLASS, return the class of reg to actually use. + In general this is just CLASS, but for the Thumb core registers and + immediate constants we prefer a LO_REGS class or a subset. */ + +static reg_class_t +arm_preferred_reload_class (rtx x ATTRIBUTE_UNUSED, reg_class_t rclass) +{ + if (TARGET_32BIT) + return rclass; + else + { + if (rclass == GENERAL_REGS + || rclass == HI_REGS + || rclass == NO_REGS + || rclass == STACK_REG) + return LO_REGS; + else + return rclass; + } +} + /* Build the SYMBOL_REF for __tls_get_addr. */ static GTY(()) rtx tls_get_addr_libfunc; diff --git a/gcc/config/arm/arm.h b/gcc/config/arm/arm.h index 443d2ed168d..c6b4cc09a46 100644 --- a/gcc/config/arm/arm.h +++ b/gcc/config/arm/arm.h @@ -1151,16 +1151,6 @@ enum reg_class #define TARGET_SMALL_REGISTER_CLASSES_FOR_MODE_P \ arm_small_register_classes_for_mode_p -/* Given an rtx X being reloaded into a reg required to be - in class CLASS, return the class of reg to actually use. - In general this is just CLASS, but for the Thumb core registers and - immediate constants we prefer a LO_REGS class or a subset. */ -#define PREFERRED_RELOAD_CLASS(X, CLASS) \ - (TARGET_32BIT ? (CLASS) : \ - ((CLASS) == GENERAL_REGS || (CLASS) == HI_REGS \ - || (CLASS) == NO_REGS || (CLASS) == STACK_REG \ - ? LO_REGS : (CLASS))) - /* Must leave BASE_REGS reloads alone */ #define THUMB_SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X) \ ((CLASS) != LO_REGS && (CLASS) != BASE_REGS \ diff --git a/gcc/config/arm/arm.opt b/gcc/config/arm/arm.opt index 934aa35775e..e03a1633767 100644 --- a/gcc/config/arm/arm.opt +++ b/gcc/config/arm/arm.opt @@ -59,7 +59,7 @@ Target Report Mask(ABORT_NORETURN) Generate a call to abort if a noreturn function returns mapcs -Target RejectNegative Mask(APCS_FRAME) MaskExists Undocumented +Target RejectNegative Mask(APCS_FRAME) Undocumented mapcs-float Target Report Mask(APCS_FLOAT) diff --git a/gcc/config/avr/avr-c.c b/gcc/config/avr/avr-c.c index 1babb5372c2..d689fa02380 100644 --- a/gcc/config/avr/avr-c.c +++ b/gcc/config/avr/avr-c.c @@ -128,6 +128,12 @@ avr_cpu_cpp_builtins (struct cpp_reader *pfile) else cpp_define (pfile, "__AVR_HAVE_16BIT_SP__"); + if (avr_sp8) + cpp_define (pfile, "__AVR_SP8__"); + + if (AVR_HAVE_SPH) + cpp_define (pfile, "__AVR_HAVE_SPH__"); + if (TARGET_NO_INTERRUPTS) cpp_define (pfile, "__NO_INTERRUPTS__"); diff --git a/gcc/config/avr/avr.c b/gcc/config/avr/avr.c index 341fe9b2f85..c25f8983a79 100644 --- a/gcc/config/avr/avr.c +++ b/gcc/config/avr/avr.c @@ -963,7 +963,7 @@ avr_prologue_setup_frame (HOST_WIDE_INT size, HARD_REG_SET set) { /* Don't error so that insane code from newlib still compiles and does not break building newlib. As PR51345 is implemented - now, there are multilib variants with -mtiny-stack. + now, there are multilib variants with -msp8. If user wants sanity checks he can use -Wstack-usage= or similar options. @@ -2774,7 +2774,7 @@ output_movhi (rtx insn, rtx xop[], int *plen) } else if (test_hard_reg_class (STACK_REG, src)) { - return AVR_HAVE_8BIT_SP + return !AVR_HAVE_SPH ? avr_asm_len ("in %A0,__SP_L__" CR_TAB "clr %B0", xop, plen, -2) @@ -7341,7 +7341,7 @@ avr_file_start (void) /* Print I/O addresses of some SFRs used with IN and OUT. */ - if (!AVR_HAVE_8BIT_SP) + if (AVR_HAVE_SPH) fprintf (asm_out_file, "__SP_H__ = 0x%02x\n", avr_addr.sp_h - sfr_offset); fprintf (asm_out_file, "__SP_L__ = 0x%02x\n", avr_addr.sp_l - sfr_offset); @@ -10285,6 +10285,42 @@ enum avr_builtin_id AVR_BUILTIN_COUNT }; +struct GTY(()) avr_builtin_description +{ + enum insn_code icode; + const char *name; + int n_args; + tree fndecl; +}; + + +/* Notice that avr_bdesc[] and avr_builtin_id are initialized in such a way + that a built-in's ID can be used to access the built-in by means of + avr_bdesc[ID] */ + +static GTY(()) struct avr_builtin_description +avr_bdesc[AVR_BUILTIN_COUNT] = + { + +#define DEF_BUILTIN(NAME, N_ARGS, ID, TYPE, ICODE) \ + { ICODE, NAME, N_ARGS, NULL_TREE }, +#include "builtins.def" +#undef DEF_BUILTIN + }; + + +/* Implement `TARGET_BUILTIN_DECL'. */ + +static tree +avr_builtin_decl (unsigned id, bool initialize_p ATTRIBUTE_UNUSED) +{ + if (id < AVR_BUILTIN_COUNT) + return avr_bdesc[id].fndecl; + + return error_mark_node; +} + + static void avr_init_builtin_int24 (void) { @@ -10295,6 +10331,7 @@ avr_init_builtin_int24 (void) (*lang_hooks.types.register_builtin_type) (uint24_type, "__uint24"); } + /* Implement `TARGET_INIT_BUILTINS' */ /* Set up all builtin functions for this target. */ @@ -10348,7 +10385,9 @@ avr_init_builtins (void) NULL); #define DEF_BUILTIN(NAME, N_ARGS, ID, TYPE, CODE) \ - add_builtin_function (NAME, TYPE, ID, BUILT_IN_MD, NULL, NULL_TREE); + gcc_assert (ID < AVR_BUILTIN_COUNT); \ + avr_bdesc[ID].fndecl \ + = add_builtin_function (NAME, TYPE, ID, BUILT_IN_MD, NULL, NULL_TREE); #include "builtins.def" #undef DEF_BUILTIN @@ -10356,27 +10395,6 @@ avr_init_builtins (void) } -struct avr_builtin_description -{ - enum insn_code icode; - const char *name; - enum avr_builtin_id id; - int n_args; -}; - -static const struct avr_builtin_description -avr_bdesc[] = - { - -#define DEF_BUILTIN(NAME, N_ARGS, ID, TYPE, ICODE) \ - { ICODE, NAME, ID, N_ARGS }, -#include "builtins.def" -#undef DEF_BUILTIN - - { CODE_FOR_nothing, NULL, 0, -1 } - }; - - /* Subroutine of avr_expand_builtin to take care of unop insns. */ static rtx @@ -10545,6 +10563,7 @@ avr_expand_triop_builtin (enum insn_code icode, tree exp, rtx target) } +/* Implement `TARGET_EXPAND_BUILTIN'. */ /* Expand an expression EXP that calls a built-in function, with result going to TARGET if that's convenient (and in mode MODE if that's convenient). @@ -10557,13 +10576,15 @@ avr_expand_builtin (tree exp, rtx target, enum machine_mode mode ATTRIBUTE_UNUSED, int ignore ATTRIBUTE_UNUSED) { - size_t i; tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0); const char* bname = IDENTIFIER_POINTER (DECL_NAME (fndecl)); unsigned int id = DECL_FUNCTION_CODE (fndecl); + const struct avr_builtin_description *d = &avr_bdesc[id]; tree arg0; rtx op0; + gcc_assert (id < AVR_BUILTIN_COUNT); + switch (id) { case AVR_BUILTIN_NOP: @@ -10597,29 +10618,22 @@ avr_expand_builtin (tree exp, rtx target, } } - for (i = 0; avr_bdesc[i].name; i++) + /* No special treatment needed: vanilla expand. */ + + switch (d->n_args) { - const struct avr_builtin_description *d = &avr_bdesc[i]; + case 0: + emit_insn ((GEN_FCN (d->icode)) (target)); + return 0; - if (d->id == id) - switch (d->n_args) - { - case 0: - emit_insn ((GEN_FCN (d->icode)) (target)); - return 0; - - case 1: - return avr_expand_unop_builtin (d->icode, exp, target); - - case 2: - return avr_expand_binop_builtin (d->icode, exp, target); - - case 3: - return avr_expand_triop_builtin (d->icode, exp, target); - - default: - gcc_unreachable(); - } + case 1: + return avr_expand_unop_builtin (d->icode, exp, target); + + case 2: + return avr_expand_binop_builtin (d->icode, exp, target); + + case 3: + return avr_expand_triop_builtin (d->icode, exp, target); } gcc_unreachable (); @@ -10878,6 +10892,9 @@ avr_fold_builtin (tree fndecl, int n_args ATTRIBUTE_UNUSED, tree *arg, #undef TARGET_INIT_BUILTINS #define TARGET_INIT_BUILTINS avr_init_builtins +#undef TARGET_BUILTIN_DECL +#define TARGET_BUILTIN_DECL avr_builtin_decl + #undef TARGET_EXPAND_BUILTIN #define TARGET_EXPAND_BUILTIN avr_expand_builtin diff --git a/gcc/config/avr/avr.h b/gcc/config/avr/avr.h index 8488e15dcad..bd5241c9fad 100644 --- a/gcc/config/avr/avr.h +++ b/gcc/config/avr/avr.h @@ -188,7 +188,26 @@ enum #define AVR_HAVE_RAMPZ (avr_current_arch->have_elpm \ || avr_current_arch->have_rampd) #define AVR_HAVE_EIJMP_EICALL (avr_current_arch->have_eijmp_eicall) -#define AVR_HAVE_8BIT_SP (avr_current_device->short_sp || TARGET_TINY_STACK) + +/* Handling of 8-bit SP versus 16-bit SP is as follows: + + -msp8 is used internally to select the right multilib for targets with + 8-bit SP. -msp8 is set automatically by DRIVER_SELF_SPECS for devices + with 8-bit SP or by multilib generation machinery. If a frame pointer is + needed and SP is only 8 bits wide, SP is zero-extended to get FP. + + TARGET_TINY_STACK is triggered by -mtiny-stack which is a user option. + This option has no effect on multilib selection. It serves to save some + bytes on 16-bit SP devices by only changing SP_L and leaving SP_H alone. + + These two properties are reflected by built-in macros __AVR_SP8__ resp. + __AVR_HAVE_8BIT_SP__ and __AVR_HAVE_16BIT_SP__. During multilib generation + there is always __AVR_SP8__ == __AVR_HAVE_8BIT_SP__. */ + +#define AVR_HAVE_8BIT_SP \ + (avr_current_device->short_sp || TARGET_TINY_STACK || avr_sp8) + +#define AVR_HAVE_SPH (!avr_sp8) #define AVR_2_BYTE_PC (!AVR_HAVE_EIJMP_EICALL) #define AVR_3_BYTE_PC (AVR_HAVE_EIJMP_EICALL) @@ -577,13 +596,16 @@ extern const char *avr_device_to_arch (int argc, const char **argv); extern const char *avr_device_to_data_start (int argc, const char **argv); extern const char *avr_device_to_startfiles (int argc, const char **argv); extern const char *avr_device_to_devicelib (int argc, const char **argv); +extern const char *avr_device_to_sp8 (int argc, const char **argv); -#define EXTRA_SPEC_FUNCTIONS \ - { "device_to_arch", avr_device_to_arch }, \ +#define EXTRA_SPEC_FUNCTIONS \ + { "device_to_arch", avr_device_to_arch }, \ { "device_to_data_start", avr_device_to_data_start }, \ - { "device_to_startfile", avr_device_to_startfiles }, \ - { "device_to_devicelib", avr_device_to_devicelib }, + { "device_to_startfile", avr_device_to_startfiles }, \ + { "device_to_devicelib", avr_device_to_devicelib }, \ + { "device_to_sp8", avr_device_to_sp8 }, +#define DRIVER_SELF_SPECS " %:device_to_sp8(%{mmcu=*:%*}) " #define CPP_SPEC "" #define CC1_SPEC "" diff --git a/gcc/config/avr/avr.opt b/gcc/config/avr/avr.opt index d6e73ee0914..d4d6b7826d8 100644 --- a/gcc/config/avr/avr.opt +++ b/gcc/config/avr/avr.opt @@ -73,3 +73,7 @@ Accumulate outgoing function arguments and acquire/release the needed stack spac mstrict-X Target Report Var(avr_strict_X) Init(0) When accessing RAM, use X as imposed by the hardware, i.e. just use pre-decrement, post-increment and indirect addressing with the X register. Without this option, the compiler may assume that there is an addressing mode X+const similar to Y+const and Z+const and emit instructions to emulate such an addressing mode for X. + +;; For rationale behind -msp8 see explanation in avr.h. +msp8 +Target Report RejectNegative Undocumented Var(avr_sp8) Init(0) diff --git a/gcc/config/avr/driver-avr.c b/gcc/config/avr/driver-avr.c index 6ab0bb822ef..26c21412c3f 100644 --- a/gcc/config/avr/driver-avr.c +++ b/gcc/config/avr/driver-avr.c @@ -112,3 +112,24 @@ avr_device_to_devicelib (int argc, const char **argv) return concat ("-l", avr_current_device->library_name, NULL); } +const char* +avr_device_to_sp8 (int argc, const char **argv) +{ + if (0 == argc) + return NULL; + + avr_set_current_device (argv[0]); + + /* Leave "avr2" and "avr25" alone. These two architectures are + the only ones that mix devices with 8-bit SP and 16-bit SP. + -msp8 is set by mmultilib machinery. */ + + if (avr_current_device->macro == NULL + && (avr_current_device->arch == ARCH_AVR2 + || avr_current_device->arch == ARCH_AVR25)) + return ""; + + return avr_current_device->short_sp + ? "-msp8" + : "%<msp8"; +} diff --git a/gcc/config/avr/genmultilib.awk b/gcc/config/avr/genmultilib.awk index 7bc3b4af225..0aab49a407f 100644 --- a/gcc/config/avr/genmultilib.awk +++ b/gcc/config/avr/genmultilib.awk @@ -26,9 +26,6 @@ # FORMAT = "Makefile": Generate Makefile Snipet that sets some # MULTILIB_* Variables as needed. # -# FORMAT = "multilib.h": Generate C Header intended to override -# (parts of) multilib.h used in gcc.c. -# ################################################################## BEGIN { @@ -41,7 +38,7 @@ BEGIN { mtiny[0] = "" mtiny[1] = "tiny-stack" - option["tiny-stack"] = "mtiny-stack" + option["tiny-stack"] = "msp8" } ################################################################## @@ -54,18 +51,6 @@ BEGIN { next else if (comment == 1) { - if (FORMAT == "multilib.h") - { - print "/*" - print " Auto-generated C header" - print " Generated by : ./gcc/config/avr/genmultilib.awk" - print " Generated from : ./gcc/config/avr/avr-mcus.def" - print " Used by : ./gcc/gcc.c via tm.h" - print " Purpose : Override multilib_raw[] from multilib.h" - print "*/" - print "/*" - } - if (FORMAT == "Makefile") { print "# Auto-generated Makefile Snip" @@ -78,15 +63,12 @@ BEGIN { comment = 2; - if (FORMAT == "multilib.h") - gsub ("#", " ") - print } /^$/ { - if (comment && FORMAT == "multilib.h") - print "*/" + # The first empty line stops copy-pasting the GPL comments + # from this file to the generated file. comment = 0 } @@ -144,7 +126,6 @@ BEGIN { # m_dirnames <-> MULTILIB_DIRNAMES " # m_exceptions <-> MULTILIB_EXCEPTIONS " # m_matches <-> MULTILIB_MATCHES " -# m_raw <-> avr_multilib_raw multilib.h # ################################################################## @@ -154,11 +135,9 @@ END { m_exceptions = "\nMULTILIB_EXCEPTIONS =" m_matches = "\nMULTILIB_MATCHES =" - m_raw = "" - ############################################################## # Compose MULTILIB_OPTIONS. This represents the Cross-Product - # (avr2, avr25, ...) x mtiny-stack + # (avr2, avr25, ...) x msp8 sep = "" for (c = 0; c < n_cores; c++) @@ -167,54 +146,25 @@ END { sep = "/" } - # The ... x mtiny-stack + # The ... x msp8 m_options = m_options " " option[mtiny[1]] ############################################################## # Map Device to its multilib - # All Mappings that cannot be represented by GCC's genmultilib - # Machinery must be handcrafted. - - dot_excludes = "" - m_raw_sp8 = "" - for (t = 0; t < n_mcu; t++) { core = toCore[mcu[t]] - if (tiny_stack[mcu[t]] == 1) - { - if (core == "avr2") - dir = mtiny[1] - else - dir = core "/" mtiny[1] - - m_raw_sp8 = m_raw_sp8 " \"" dir " " option[mcu[t]] ";\",\n" - dot_excludes = dot_excludes " !" option[mcu[t]] - - line = option[mcu[t]] ":" option[mcu[t]] - gsub ("=", "?", line) - gsub (":", "=", line) - - m_matches = m_matches " \\\n\t" line - } + line = option[core] ":" option[mcu[t]] + gsub ("=", "?", line) + gsub (":", "=", line) - # The SP = 16 Devices are vanilla: Do the same as - # MULTILIB_MATCHES would yield. Don't list avr2 (default) - - if (core != "avr2") - { - line = option[core] ":" option[mcu[t]] - gsub ("=", "?", line) - gsub (":", "=", line) - - m_matches = m_matches " \\\n\t" line - } + m_matches = m_matches " \\\n\t" line } #################################################################### - # Compose MULTILIB_DIRNAMES, MULTILIB_EXEPTIONS and avr_multilib_raw + # Compose MULTILIB_DIRNAMES and MULTILIB_EXEPTIONS n_mtiny = 2 for (t = 0; t < n_mtiny; t++) @@ -248,38 +198,6 @@ END { if (core != "avr2" || mtiny[t] == "") m_dirnames = m_dirnames " " mdir - - # Remainder deals with avr_multilib_raw Entries. - # Each Entry looks like - # "multilib-dir option-to-match !option-to-avoid-match;" - # for Example: - # "avr25/tiny-stack !mmcu=avr2 mmcu=avr25 !mmcu=avr3 ... mtiny-stack;" - - if (mdir == "") - mdir = "." - - line = mdir - - for (s = 0; s < n_cores; s++) - { - if (cores[s] == core) - line = line " " option[cores[s]] - else - line = line " !" option[cores[s]] - } - - if (tiny_stack[core] != 0) - { - if (mtiny[t] == "") - line = line " !" option[mtiny[1]] - else - line = line " " option[mtiny[1]] - } - - if (mdir == ".") - line = line dot_excludes - - m_raw = m_raw " \"" line ";\",\n" } ############################################################ @@ -295,21 +213,4 @@ END { print m_exceptions print m_matches } - - if (FORMAT == "multilib.h") - { - # Intended Target: ./gcc/config/avr/multilib.h - - print "#if defined NULL && !defined AVR_MULTILIB_H" - print "#define AVR_MULTILIB_H" - - print "static const char* const avr_multilib_raw[] = {" - print m_raw_sp8 - print m_raw - print " NULL\n};" - - print "#undef multilib_raw" - print "#define multilib_raw avr_multilib_raw" - print "#endif /* AVR_MULTILIB_H */" - } } diff --git a/gcc/config/avr/multilib.h b/gcc/config/avr/multilib.h deleted file mode 100644 index 582c6dae6f7..00000000000 --- a/gcc/config/avr/multilib.h +++ /dev/null @@ -1,70 +0,0 @@ -/* - Auto-generated C header - Generated by : ./gcc/config/avr/genmultilib.awk - Generated from : ./gcc/config/avr/avr-mcus.def - Used by : ./gcc/gcc.c via tm.h - Purpose : Override multilib_raw[] from multilib.h -*/ -/* - Copyright (C) 2011 Free Software Foundation, Inc. - - This file is part of GCC. - - GCC is free software; you can redistribute it and/or modify it under - the terms of the GNU General Public License as published by the Free - Software Foundation; either version 3, or (at your option) any later - version. - - GCC is distributed in the hope that it will be useful, but WITHOUT ANY - WARRANTY; without even the implied warranty of MERCHANTABILITY or - FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License - for more details. - - You should have received a copy of the GNU General Public License - along with GCC; see the file COPYING3. If not see - <http://www.gnu.org/licenses/>. -*/ -#if defined NULL && !defined AVR_MULTILIB_H -#define AVR_MULTILIB_H -static const char* const avr_multilib_raw[] = { - "tiny-stack mmcu=at90s2313;", - "tiny-stack mmcu=at90s2323;", - "tiny-stack mmcu=at90s2333;", - "tiny-stack mmcu=at90s2343;", - "tiny-stack mmcu=attiny22;", - "tiny-stack mmcu=attiny26;", - "tiny-stack mmcu=at90s4433;", - "avr25/tiny-stack mmcu=attiny13;", - "avr25/tiny-stack mmcu=attiny13a;", - "avr25/tiny-stack mmcu=attiny2313;", - "avr25/tiny-stack mmcu=attiny2313a;", - "avr25/tiny-stack mmcu=attiny24;", - "avr25/tiny-stack mmcu=attiny24a;", - "avr25/tiny-stack mmcu=attiny25;", - "avr25/tiny-stack mmcu=attiny261;", - "avr25/tiny-stack mmcu=attiny261a;", - - ". !mmcu=avr2 !mmcu=avr25 !mmcu=avr3 !mmcu=avr31 !mmcu=avr35 !mmcu=avr4 !mmcu=avr5 !mmcu=avr51 !mmcu=avr6 !mmcu=avrxmega2 !mmcu=avrxmega4 !mmcu=avrxmega5 !mmcu=avrxmega6 !mmcu=avrxmega7 !mtiny-stack !mmcu=at90s2313 !mmcu=at90s2323 !mmcu=at90s2333 !mmcu=at90s2343 !mmcu=attiny22 !mmcu=attiny26 !mmcu=at90s4433 !mmcu=attiny13 !mmcu=attiny13a !mmcu=attiny2313 !mmcu=attiny2313a !mmcu=attiny24 !mmcu=attiny24a !mmcu=attiny25 !mmcu=attiny261 !mmcu=attiny261a;", - "avr2 mmcu=avr2 !mmcu=avr25 !mmcu=avr3 !mmcu=avr31 !mmcu=avr35 !mmcu=avr4 !mmcu=avr5 !mmcu=avr51 !mmcu=avr6 !mmcu=avrxmega2 !mmcu=avrxmega4 !mmcu=avrxmega5 !mmcu=avrxmega6 !mmcu=avrxmega7 !mtiny-stack;", - "avr25 !mmcu=avr2 mmcu=avr25 !mmcu=avr3 !mmcu=avr31 !mmcu=avr35 !mmcu=avr4 !mmcu=avr5 !mmcu=avr51 !mmcu=avr6 !mmcu=avrxmega2 !mmcu=avrxmega4 !mmcu=avrxmega5 !mmcu=avrxmega6 !mmcu=avrxmega7 !mtiny-stack;", - "avr3 !mmcu=avr2 !mmcu=avr25 mmcu=avr3 !mmcu=avr31 !mmcu=avr35 !mmcu=avr4 !mmcu=avr5 !mmcu=avr51 !mmcu=avr6 !mmcu=avrxmega2 !mmcu=avrxmega4 !mmcu=avrxmega5 !mmcu=avrxmega6 !mmcu=avrxmega7;", - "avr31 !mmcu=avr2 !mmcu=avr25 !mmcu=avr3 mmcu=avr31 !mmcu=avr35 !mmcu=avr4 !mmcu=avr5 !mmcu=avr51 !mmcu=avr6 !mmcu=avrxmega2 !mmcu=avrxmega4 !mmcu=avrxmega5 !mmcu=avrxmega6 !mmcu=avrxmega7;", - "avr35 !mmcu=avr2 !mmcu=avr25 !mmcu=avr3 !mmcu=avr31 mmcu=avr35 !mmcu=avr4 !mmcu=avr5 !mmcu=avr51 !mmcu=avr6 !mmcu=avrxmega2 !mmcu=avrxmega4 !mmcu=avrxmega5 !mmcu=avrxmega6 !mmcu=avrxmega7;", - "avr4 !mmcu=avr2 !mmcu=avr25 !mmcu=avr3 !mmcu=avr31 !mmcu=avr35 mmcu=avr4 !mmcu=avr5 !mmcu=avr51 !mmcu=avr6 !mmcu=avrxmega2 !mmcu=avrxmega4 !mmcu=avrxmega5 !mmcu=avrxmega6 !mmcu=avrxmega7;", - "avr5 !mmcu=avr2 !mmcu=avr25 !mmcu=avr3 !mmcu=avr31 !mmcu=avr35 !mmcu=avr4 mmcu=avr5 !mmcu=avr51 !mmcu=avr6 !mmcu=avrxmega2 !mmcu=avrxmega4 !mmcu=avrxmega5 !mmcu=avrxmega6 !mmcu=avrxmega7;", - "avr51 !mmcu=avr2 !mmcu=avr25 !mmcu=avr3 !mmcu=avr31 !mmcu=avr35 !mmcu=avr4 !mmcu=avr5 mmcu=avr51 !mmcu=avr6 !mmcu=avrxmega2 !mmcu=avrxmega4 !mmcu=avrxmega5 !mmcu=avrxmega6 !mmcu=avrxmega7;", - "avr6 !mmcu=avr2 !mmcu=avr25 !mmcu=avr3 !mmcu=avr31 !mmcu=avr35 !mmcu=avr4 !mmcu=avr5 !mmcu=avr51 mmcu=avr6 !mmcu=avrxmega2 !mmcu=avrxmega4 !mmcu=avrxmega5 !mmcu=avrxmega6 !mmcu=avrxmega7;", - "avrxmega2 !mmcu=avr2 !mmcu=avr25 !mmcu=avr3 !mmcu=avr31 !mmcu=avr35 !mmcu=avr4 !mmcu=avr5 !mmcu=avr51 !mmcu=avr6 mmcu=avrxmega2 !mmcu=avrxmega4 !mmcu=avrxmega5 !mmcu=avrxmega6 !mmcu=avrxmega7;", - "avrxmega4 !mmcu=avr2 !mmcu=avr25 !mmcu=avr3 !mmcu=avr31 !mmcu=avr35 !mmcu=avr4 !mmcu=avr5 !mmcu=avr51 !mmcu=avr6 !mmcu=avrxmega2 mmcu=avrxmega4 !mmcu=avrxmega5 !mmcu=avrxmega6 !mmcu=avrxmega7;", - "avrxmega5 !mmcu=avr2 !mmcu=avr25 !mmcu=avr3 !mmcu=avr31 !mmcu=avr35 !mmcu=avr4 !mmcu=avr5 !mmcu=avr51 !mmcu=avr6 !mmcu=avrxmega2 !mmcu=avrxmega4 mmcu=avrxmega5 !mmcu=avrxmega6 !mmcu=avrxmega7;", - "avrxmega6 !mmcu=avr2 !mmcu=avr25 !mmcu=avr3 !mmcu=avr31 !mmcu=avr35 !mmcu=avr4 !mmcu=avr5 !mmcu=avr51 !mmcu=avr6 !mmcu=avrxmega2 !mmcu=avrxmega4 !mmcu=avrxmega5 mmcu=avrxmega6 !mmcu=avrxmega7;", - "avrxmega7 !mmcu=avr2 !mmcu=avr25 !mmcu=avr3 !mmcu=avr31 !mmcu=avr35 !mmcu=avr4 !mmcu=avr5 !mmcu=avr51 !mmcu=avr6 !mmcu=avrxmega2 !mmcu=avrxmega4 !mmcu=avrxmega5 !mmcu=avrxmega6 mmcu=avrxmega7;", - "tiny-stack !mmcu=avr2 !mmcu=avr25 !mmcu=avr3 !mmcu=avr31 !mmcu=avr35 !mmcu=avr4 !mmcu=avr5 !mmcu=avr51 !mmcu=avr6 !mmcu=avrxmega2 !mmcu=avrxmega4 !mmcu=avrxmega5 !mmcu=avrxmega6 !mmcu=avrxmega7 mtiny-stack;", - "avr2/tiny-stack mmcu=avr2 !mmcu=avr25 !mmcu=avr3 !mmcu=avr31 !mmcu=avr35 !mmcu=avr4 !mmcu=avr5 !mmcu=avr51 !mmcu=avr6 !mmcu=avrxmega2 !mmcu=avrxmega4 !mmcu=avrxmega5 !mmcu=avrxmega6 !mmcu=avrxmega7 mtiny-stack;", - "avr25/tiny-stack !mmcu=avr2 mmcu=avr25 !mmcu=avr3 !mmcu=avr31 !mmcu=avr35 !mmcu=avr4 !mmcu=avr5 !mmcu=avr51 !mmcu=avr6 !mmcu=avrxmega2 !mmcu=avrxmega4 !mmcu=avrxmega5 !mmcu=avrxmega6 !mmcu=avrxmega7 mtiny-stack;", - - NULL -}; -#undef multilib_raw -#define multilib_raw avr_multilib_raw -#endif /* AVR_MULTILIB_H */ diff --git a/gcc/config/avr/t-avr b/gcc/config/avr/t-avr index e6b4adee182..99638333204 100644 --- a/gcc/config/avr/t-avr +++ b/gcc/config/avr/t-avr @@ -49,16 +49,10 @@ $(srcdir)/config/avr/avr-tables.opt: $(srcdir)/config/avr/genopt.sh $(AVR_MCUS) # MULTILIB_MATCHES $(srcdir)/config/avr/t-multilib: s-avr-mlib; @true -# Override multilib_raw[] from multilib.h -$(srcdir)/config/avr/multilib.h: s-avr-mlib; @true - s-mlib: $(srcdir)/config/avr/t-multilib s-avr-mlib: $(srcdir)/config/avr/genmultilib.awk $(AVR_MCUS) $(AWK) -f $< -v FORMAT=Makefile $< $(AVR_MCUS) > tmp-avr-mlib - $(AWK) -f $< -v FORMAT=multilib.h $< $(AVR_MCUS) > tmp-avr-mlib.h - $(SHELL) $(srcdir)/../move-if-change \ - tmp-avr-mlib.h $(srcdir)/config/avr/multilib.h $(SHELL) $(srcdir)/../move-if-change \ tmp-avr-mlib $(srcdir)/config/avr/t-multilib $(STAMP) $@ diff --git a/gcc/config/avr/t-multilib b/gcc/config/avr/t-multilib index 886d5507c5c..497f63b4ea8 100644 --- a/gcc/config/avr/t-multilib +++ b/gcc/config/avr/t-multilib @@ -21,57 +21,53 @@ # along with GCC; see the file COPYING3. If not see # <http://www.gnu.org/licenses/>. -MULTILIB_OPTIONS = mmcu=avr2/mmcu=avr25/mmcu=avr3/mmcu=avr31/mmcu=avr35/mmcu=avr4/mmcu=avr5/mmcu=avr51/mmcu=avr6/mmcu=avrxmega2/mmcu=avrxmega4/mmcu=avrxmega5/mmcu=avrxmega6/mmcu=avrxmega7 mtiny-stack +MULTILIB_OPTIONS = mmcu=avr2/mmcu=avr25/mmcu=avr3/mmcu=avr31/mmcu=avr35/mmcu=avr4/mmcu=avr5/mmcu=avr51/mmcu=avr6/mmcu=avrxmega2/mmcu=avrxmega4/mmcu=avrxmega5/mmcu=avrxmega6/mmcu=avrxmega7 msp8 MULTILIB_DIRNAMES = avr2 avr25 avr3 avr31 avr35 avr4 avr5 avr51 avr6 avrxmega2 avrxmega4 avrxmega5 avrxmega6 avrxmega7 tiny-stack avr25/tiny-stack MULTILIB_EXCEPTIONS = \ - mmcu=avr3/mtiny-stack \ - mmcu=avr31/mtiny-stack \ - mmcu=avr35/mtiny-stack \ - mmcu=avr4/mtiny-stack \ - mmcu=avr5/mtiny-stack \ - mmcu=avr51/mtiny-stack \ - mmcu=avr6/mtiny-stack \ - mmcu=avrxmega2/mtiny-stack \ - mmcu=avrxmega4/mtiny-stack \ - mmcu=avrxmega5/mtiny-stack \ - mmcu=avrxmega6/mtiny-stack \ - mmcu=avrxmega7/mtiny-stack + mmcu=avr3/msp8 \ + mmcu=avr31/msp8 \ + mmcu=avr35/msp8 \ + mmcu=avr4/msp8 \ + mmcu=avr5/msp8 \ + mmcu=avr51/msp8 \ + mmcu=avr6/msp8 \ + mmcu=avrxmega2/msp8 \ + mmcu=avrxmega4/msp8 \ + mmcu=avrxmega5/msp8 \ + mmcu=avrxmega6/msp8 \ + mmcu=avrxmega7/msp8 MULTILIB_MATCHES = \ - mmcu?at90s2313=mmcu?at90s2313 \ - mmcu?at90s2323=mmcu?at90s2323 \ - mmcu?at90s2333=mmcu?at90s2333 \ - mmcu?at90s2343=mmcu?at90s2343 \ - mmcu?attiny22=mmcu?attiny22 \ - mmcu?attiny26=mmcu?attiny26 \ - mmcu?at90s4433=mmcu?at90s4433 \ + mmcu?avr2=mmcu?at90s2313 \ + mmcu?avr2=mmcu?at90s2323 \ + mmcu?avr2=mmcu?at90s2333 \ + mmcu?avr2=mmcu?at90s2343 \ + mmcu?avr2=mmcu?attiny22 \ + mmcu?avr2=mmcu?attiny26 \ + mmcu?avr2=mmcu?at90s4414 \ + mmcu?avr2=mmcu?at90s4433 \ + mmcu?avr2=mmcu?at90s4434 \ + mmcu?avr2=mmcu?at90s8515 \ + mmcu?avr2=mmcu?at90c8534 \ + mmcu?avr2=mmcu?at90s8535 \ mmcu?avr25=mmcu?ata6289 \ - mmcu?attiny13=mmcu?attiny13 \ mmcu?avr25=mmcu?attiny13 \ - mmcu?attiny13a=mmcu?attiny13a \ mmcu?avr25=mmcu?attiny13a \ - mmcu?attiny2313=mmcu?attiny2313 \ mmcu?avr25=mmcu?attiny2313 \ - mmcu?attiny2313a=mmcu?attiny2313a \ mmcu?avr25=mmcu?attiny2313a \ - mmcu?attiny24=mmcu?attiny24 \ mmcu?avr25=mmcu?attiny24 \ - mmcu?attiny24a=mmcu?attiny24a \ mmcu?avr25=mmcu?attiny24a \ mmcu?avr25=mmcu?attiny4313 \ mmcu?avr25=mmcu?attiny44 \ mmcu?avr25=mmcu?attiny44a \ mmcu?avr25=mmcu?attiny84 \ mmcu?avr25=mmcu?attiny84a \ - mmcu?attiny25=mmcu?attiny25 \ mmcu?avr25=mmcu?attiny25 \ mmcu?avr25=mmcu?attiny45 \ mmcu?avr25=mmcu?attiny85 \ - mmcu?attiny261=mmcu?attiny261 \ mmcu?avr25=mmcu?attiny261 \ - mmcu?attiny261a=mmcu?attiny261a \ mmcu?avr25=mmcu?attiny261a \ mmcu?avr25=mmcu?attiny461 \ mmcu?avr25=mmcu?attiny461a \ diff --git a/gcc/config/cris/linux.opt b/gcc/config/cris/linux.opt index a57c48d7ce8..e93bb53a6fd 100644 --- a/gcc/config/cris/linux.opt +++ b/gcc/config/cris/linux.opt @@ -23,7 +23,7 @@ mlinux Target Report RejectNegative Undocumented mno-gotplt -Target Report RejectNegative Mask(AVOID_GOTPLT) MaskExists +Target Report RejectNegative Mask(AVOID_GOTPLT) Together with -fpic and -fPIC, do not use GOTPLT references ; There's a small added setup cost with using GOTPLT references diff --git a/gcc/config/h8300/h8300-protos.h b/gcc/config/h8300/h8300-protos.h index aeac904031c..428a86a316c 100644 --- a/gcc/config/h8300/h8300-protos.h +++ b/gcc/config/h8300/h8300-protos.h @@ -96,6 +96,7 @@ extern int h8300_can_use_return_insn_p (void); extern void h8300_expand_prologue (void); extern void h8300_expand_epilogue (void); extern int h8300_current_function_interrupt_function_p (void); +extern int h8300_current_function_monitor_function_p (void); extern int h8300_initial_elimination_offset (int, int); extern int h8300_regs_ok_for_stm (int, rtx[]); extern int h8300_hard_regno_rename_ok (unsigned int, unsigned int); diff --git a/gcc/config/h8300/h8300.c b/gcc/config/h8300/h8300.c index 3911cd4dda4..7eaaf202f00 100644 --- a/gcc/config/h8300/h8300.c +++ b/gcc/config/h8300/h8300.c @@ -316,6 +316,14 @@ h8300_option_override (void) static const char *const h8_pop_ops[2] = { "pop" , "pop.l" }; static const char *const h8_mov_ops[2] = { "mov.w", "mov.l" }; +#ifndef OBJECT_FORMAT_ELF + if (TARGET_H8300SX) + { + error ("-msx is not supported in coff"); + target_flags |= MASK_H8300S; + } +#endif + if (TARGET_H8300) { cpu_type = (int) CPU_H8300; @@ -339,10 +347,34 @@ h8300_option_override (void) if (TARGET_H8300 && TARGET_NORMAL_MODE) { - error ("-mn is used without -mh or -ms"); + error ("-mn is used without -mh or -ms or -msx"); target_flags ^= MASK_NORMAL_MODE; } + if (! TARGET_H8300S && TARGET_EXR) + { + error ("-mexr is used without -ms"); + target_flags |= MASK_H8300S_1; + } + + if (TARGET_H8300 && TARGET_INT32) + { + error ("-mint32 is not supported for H8300 and H8300L targets"); + target_flags ^= MASK_INT32; + } + + if ((!TARGET_H8300S && TARGET_EXR) && (!TARGET_H8300SX && TARGET_EXR)) + { + error ("-mexr is used without -ms or -msx"); + target_flags |= MASK_H8300S_1; + } + + if ((!TARGET_H8300S && TARGET_NEXR) && (!TARGET_H8300SX && TARGET_NEXR)) + { + warning (OPT_mno_exr, "-mno-exr valid only with -ms or -msx \ + - Option ignored!"); + } + /* Some of the shifts are optimized for speed by default. See http://gcc.gnu.org/ml/gcc-patches/2002-07/msg01858.html If optimizing for size, change shift_alg for those shift to @@ -795,9 +827,9 @@ h8300_expand_prologue (void) return; if (h8300_monitor_function_p (current_function_decl)) - /* My understanding of monitor functions is they act just like - interrupt functions, except the prologue must mask - interrupts. */ + /* The monitor function act as normal functions, which means it + can accept parameters and return values. In addition to this, + interrupts are masked in prologue and return with "rte" in epilogue. */ emit_insn (gen_monitor_prologue ()); if (frame_pointer_needed) @@ -925,8 +957,13 @@ h8300_expand_epilogue (void) int h8300_current_function_interrupt_function_p (void) { - return (h8300_interrupt_function_p (current_function_decl) - || h8300_monitor_function_p (current_function_decl)); + return (h8300_interrupt_function_p (current_function_decl)); +} + +int +h8300_current_function_monitor_function_p () +{ + return (h8300_monitor_function_p (current_function_decl)); } /* Output assembly code for the start of the file. */ diff --git a/gcc/config/h8300/h8300.md b/gcc/config/h8300/h8300.md index bf41e6669a6..df983e13634 100644 --- a/gcc/config/h8300/h8300.md +++ b/gcc/config/h8300/h8300.md @@ -2609,7 +2609,8 @@ { operands[3] = SET_DEST (XVECEXP (operands[0], 0, XVECLEN (operands[0], 0) - 2)); - if (h8300_current_function_interrupt_function_p ()) + if (h8300_current_function_interrupt_function_p () + || h8300_current_function_monitor_function_p ()) return "rte/l\t%S1-%S3"; else return "rts/l\t%S1-%S3"; @@ -2628,7 +2629,8 @@ "reload_completed" "* { - if (h8300_current_function_interrupt_function_p ()) + if (h8300_current_function_interrupt_function_p () + || h8300_current_function_monitor_function_p ()) return \"rte\"; else return \"rts\"; @@ -2654,8 +2656,16 @@ { if (TARGET_H8300) return \"subs\\t#2,r7\;mov.w\\tr0,@-r7\;stc\\tccr,r0l\;mov.b\tr0l,@(2,r7)\;mov.w\\t@r7+,r0\;orc\t#128,ccr\"; + else if (TARGET_H8300H && TARGET_NORMAL_MODE) + return \"subs\\t#2,er7\;mov.l\\ter0,@-er7\;stc\\tccr,r0l\;mov.b\\tr0l,@(4,er7)\;mov.l\\t@er7+,er0\;orc\\t#128,ccr\"; else if (TARGET_H8300H) return \"mov.l\\ter0,@-er7\;stc\\tccr,r0l\;mov.b\\tr0l,@(4,er7)\;mov.l\\t@er7+,er0\;orc\\t#128,ccr\"; + else if (TARGET_H8300S && TARGET_NEXR ) + return \"mov.l\\ter0,@-er7\;stc\tccr,r0l\;mov.b\tr0l,@(4,er7)\;mov.l\\t@er7+,er0\;orc\t#128,ccr\"; + else if (TARGET_H8300S && TARGET_NEXR && TARGET_NORMAL_MODE) + return \"subs\\t#2,er7\;mov.l\\ter0,@-er7\;stc\tccr,r0l\;mov.b\tr0l,@(4,er7)\;mov.l\\t@er7+,er0\;orc\t#128,ccr\"; + else if (TARGET_H8300S && TARGET_NORMAL_MODE) + return \"subs\\t#2,er7\;stc\texr,@-er7\;mov.l\\ter0,@-er7\;stc\tccr,r0l\;mov.b\tr0l,@(6,er7)\;mov.l\\t@er7+,er0\;orc\t#128,ccr\"; else if (TARGET_H8300S) return \"stc\texr,@-er7\;mov.l\\ter0,@-er7\;stc\tccr,r0l\;mov.b\tr0l,@(6,er7)\;mov.l\\t@er7+,er0\;orc\t#128,ccr\"; gcc_unreachable (); @@ -6199,3 +6209,5 @@ && !reg_overlap_mentioned_p (operands[0], operands[2])" [(set (match_dup 2) (match_dup 1))]) + + diff --git a/gcc/config/h8300/h8300.opt b/gcc/config/h8300/h8300.opt index 989375e152c..16c6ef5e029 100644 --- a/gcc/config/h8300/h8300.opt +++ b/gcc/config/h8300/h8300.opt @@ -60,3 +60,12 @@ Enable the normal mode malign-300 Target RejectNegative Mask(ALIGN_300) Use H8/300 alignment rules + +mexr +Target Mask(EXR) +Push extended registers on stack in monitor functions + +mno-exr +Target Mask(NEXR) +Do not push extended registers on stack in monitor functions + diff --git a/gcc/config/i386/biarch64.h b/gcc/config/i386/biarch64.h index 629ec980d19..0c3811e3f33 100644 --- a/gcc/config/i386/biarch64.h +++ b/gcc/config/i386/biarch64.h @@ -25,5 +25,5 @@ a copy of the GCC Runtime Library Exception along with this program; see the files COPYING3 and COPYING.RUNTIME respectively. If not, see <http://www.gnu.org/licenses/>. */ -#define TARGET_64BIT_DEFAULT OPTION_MASK_ISA_64BIT +#define TARGET_64BIT_DEFAULT (OPTION_MASK_ISA_64BIT | OPTION_MASK_ABI_64) #define TARGET_BI_ARCH 1 diff --git a/gcc/config/i386/biarchx32.h b/gcc/config/i386/biarchx32.h new file mode 100644 index 00000000000..69d672216ac --- /dev/null +++ b/gcc/config/i386/biarchx32.h @@ -0,0 +1,28 @@ +/* Make configure files to produce biarch compiler defaulting to x32 mode. + This file must be included very first, while the OS specific file later + to overwrite otherwise wrong defaults. + Copyright (C) 2012 Free Software Foundation, Inc. + +This file is part of GCC. + +GCC is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 3, or (at your option) +any later version. + +GCC is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +Under Section 7 of GPL version 3, you are granted additional +permissions described in the GCC Runtime Library Exception, version +3.1, as published by the Free Software Foundation. + +You should have received a copy of the GNU General Public License and +a copy of the GCC Runtime Library Exception along with this program; +see the files COPYING3 and COPYING.RUNTIME respectively. If not, see +<http://www.gnu.org/licenses/>. */ + +#define TARGET_64BIT_DEFAULT (OPTION_MASK_ISA_64BIT | OPTION_MASK_ABI_X32) +#define TARGET_BI_ARCH 2 diff --git a/gcc/config/i386/gnu-user64.h b/gcc/config/i386/gnu-user64.h index 954f3b2ff24..6f7b5de2ab8 100644 --- a/gcc/config/i386/gnu-user64.h +++ b/gcc/config/i386/gnu-user64.h @@ -58,8 +58,13 @@ see the files COPYING3 and COPYING.RUNTIME respectively. If not, see #if TARGET_64BIT_DEFAULT #define SPEC_32 "m32" +#if TARGET_BI_ARCH == 2 +#define SPEC_64 "m64" +#define SPEC_X32 "m32|m64:;" +#else #define SPEC_64 "m32|mx32:;" #define SPEC_X32 "mx32" +#endif #else #define SPEC_32 "m64|mx32:;" #define SPEC_64 "m64" @@ -95,7 +100,11 @@ see the files COPYING3 and COPYING.RUNTIME respectively. If not, see %{shared|pie:crtendS.o%s;:crtend.o%s} crtn.o%s" #if TARGET_64BIT_DEFAULT +#if TARGET_BI_ARCH == 2 +#define MULTILIB_DEFAULTS { "mx32" } +#else #define MULTILIB_DEFAULTS { "m64" } +#endif #else #define MULTILIB_DEFAULTS { "m32" } #endif diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c index f37eb54a184..8384231e1d1 100644 --- a/gcc/config/i386/i386.c +++ b/gcc/config/i386/i386.c @@ -2657,7 +2657,6 @@ ix86_target_string (HOST_WIDE_INT isa, int flags, const char *arch, preceding options while match those first. */ static struct ix86_target_opts isa_opts[] = { - { "-m64", OPTION_MASK_ISA_64BIT }, { "-mfma4", OPTION_MASK_ISA_FMA4 }, { "-mfma", OPTION_MASK_ISA_FMA }, { "-mxop", OPTION_MASK_ISA_XOP }, @@ -2730,6 +2729,7 @@ ix86_target_string (HOST_WIDE_INT isa, int flags, const char *arch, size_t len; size_t line_len; size_t sep_len; + const char *abi; memset (opts, '\0', sizeof (opts)); @@ -2747,6 +2747,21 @@ ix86_target_string (HOST_WIDE_INT isa, int flags, const char *arch, opts[num++][1] = tune; } + /* Add -m32/-m64/-mx32. */ + if ((isa & OPTION_MASK_ISA_64BIT) != 0) + { + if ((isa & OPTION_MASK_ABI_64) != 0) + abi = "-m64"; + else + abi = "-mx32"; + isa &= ~ (OPTION_MASK_ISA_64BIT + | OPTION_MASK_ABI_64 + | OPTION_MASK_ABI_X32); + } + else + abi = "-m32"; + opts[num++][0] = abi; + /* Pick out the options in isa options. */ for (i = 0; i < ARRAY_SIZE (isa_opts); i++) { @@ -3102,8 +3117,45 @@ ix86_option_override_internal (bool main_args_p) SUBSUBTARGET_OVERRIDE_OPTIONS; #endif + /* Turn off both OPTION_MASK_ABI_64 and OPTION_MASK_ABI_X32 if + TARGET_64BIT_DEFAULT is true and TARGET_64BIT is false. */ + if (TARGET_64BIT_DEFAULT && !TARGET_64BIT) + ix86_isa_flags &= ~(OPTION_MASK_ABI_64 | OPTION_MASK_ABI_X32); +#ifdef TARGET_BI_ARCH + else + { +#if TARGET_BI_ARCH == 1 + /* When TARGET_BI_ARCH == 1, by default, OPTION_MASK_ABI_64 + is on and OPTION_MASK_ABI_X32 is off. We turn off + OPTION_MASK_ABI_64 if OPTION_MASK_ABI_X32 is turned on by + -mx32. */ + if (TARGET_X32) + ix86_isa_flags &= ~OPTION_MASK_ABI_64; +#else + /* When TARGET_BI_ARCH == 2, by default, OPTION_MASK_ABI_X32 is + on and OPTION_MASK_ABI_64 is off. We turn off + OPTION_MASK_ABI_X32 if OPTION_MASK_ABI_64 is turned on by + -m64. */ + if (TARGET_LP64) + ix86_isa_flags &= ~OPTION_MASK_ABI_X32; +#endif + } +#endif + if (TARGET_X32) - ix86_isa_flags |= OPTION_MASK_ISA_64BIT; + { + /* Always turn on OPTION_MASK_ISA_64BIT and turn off + OPTION_MASK_ABI_64 for TARGET_X32. */ + ix86_isa_flags |= OPTION_MASK_ISA_64BIT; + ix86_isa_flags &= ~OPTION_MASK_ABI_64; + } + else if (TARGET_LP64) + { + /* Always turn on OPTION_MASK_ISA_64BIT and turn off + OPTION_MASK_ABI_X32 for TARGET_LP64. */ + ix86_isa_flags |= OPTION_MASK_ISA_64BIT; + ix86_isa_flags &= ~OPTION_MASK_ABI_X32; + } /* -fPIC is the default for x86_64. */ if (TARGET_MACHO && TARGET_64BIT) @@ -15823,17 +15875,18 @@ ix86_expand_vector_move_misalign (enum machine_mode mode, rtx operands[]) switch (GET_MODE_SIZE (mode)) { case 16: - /* If we're optimizing for size, movups is the smallest. */ if (TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL) { op0 = gen_lowpart (V4SFmode, op0); op1 = gen_lowpart (V4SFmode, op1); emit_insn (gen_sse_movups (op0, op1)); - return; } - op0 = gen_lowpart (V16QImode, op0); - op1 = gen_lowpart (V16QImode, op1); - emit_insn (gen_sse2_movdqu (op0, op1)); + else + { + op0 = gen_lowpart (V16QImode, op0); + op1 = gen_lowpart (V16QImode, op1); + emit_insn (gen_sse2_movdqu (op0, op1)); + } break; case 32: op0 = gen_lowpart (V32QImode, op0); @@ -15845,27 +15898,22 @@ ix86_expand_vector_move_misalign (enum machine_mode mode, rtx operands[]) } break; case MODE_VECTOR_FLOAT: - op0 = gen_lowpart (mode, op0); - op1 = gen_lowpart (mode, op1); - switch (mode) { case V4SFmode: emit_insn (gen_sse_movups (op0, op1)); break; - case V8SFmode: - ix86_avx256_split_vector_move_misalign (op0, op1); - break; case V2DFmode: if (TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL) { op0 = gen_lowpart (V4SFmode, op0); op1 = gen_lowpart (V4SFmode, op1); emit_insn (gen_sse_movups (op0, op1)); - return; } - emit_insn (gen_sse2_movupd (op0, op1)); + else + emit_insn (gen_sse2_movupd (op0, op1)); break; + case V8SFmode: case V4DFmode: ix86_avx256_split_vector_move_misalign (op0, op1); break; @@ -15910,8 +15958,6 @@ ix86_expand_vector_move_misalign (enum machine_mode mode, rtx operands[]) if (TARGET_SSE_UNALIGNED_LOAD_OPTIMAL) { - op0 = gen_lowpart (V2DFmode, op0); - op1 = gen_lowpart (V2DFmode, op1); emit_insn (gen_sse2_movupd (op0, op1)); return; } @@ -15976,8 +16022,8 @@ ix86_expand_vector_move_misalign (enum machine_mode mode, rtx operands[]) return; } - /* ??? Similar to above, only less clear because of quote - typeless stores unquote. */ + /* ??? Similar to above, only less clear + because of typeless stores. */ if (TARGET_SSE2 && !TARGET_SSE_TYPELESS_STORES && GET_MODE_CLASS (mode) == MODE_VECTOR_INT) { @@ -15990,11 +16036,7 @@ ix86_expand_vector_move_misalign (enum machine_mode mode, rtx operands[]) if (TARGET_SSE2 && mode == V2DFmode) { if (TARGET_SSE_UNALIGNED_STORE_OPTIMAL) - { - op0 = gen_lowpart (V2DFmode, op0); - op1 = gen_lowpart (V2DFmode, op1); - emit_insn (gen_sse2_movupd (op0, op1)); - } + emit_insn (gen_sse2_movupd (op0, op1)); else { m = adjust_address (op0, DFmode, 0); @@ -31391,6 +31433,10 @@ ix86_modes_tieable_p (enum machine_mode mode1, enum machine_mode mode2) /* If MODE2 is only appropriate for an SSE register, then tie with any other mode acceptable to SSE registers. */ + if (GET_MODE_SIZE (mode2) == 32 + && ix86_hard_regno_mode_ok (FIRST_SSE_REG, mode2)) + return (GET_MODE_SIZE (mode1) == 32 + && ix86_hard_regno_mode_ok (FIRST_SSE_REG, mode1)); if (GET_MODE_SIZE (mode2) == 16 && ix86_hard_regno_mode_ok (FIRST_SSE_REG, mode2)) return (GET_MODE_SIZE (mode1) == 16 @@ -32884,6 +32930,7 @@ struct expand_vec_perm_d unsigned char perm[MAX_VECT_LEN]; enum machine_mode vmode; unsigned char nelt; + bool one_operand_p; bool testing_p; }; @@ -32984,6 +33031,7 @@ ix86_expand_vector_init_duplicate (bool mmx_ok, enum machine_mode mode, dperm.vmode = mode; dperm.nelt = GET_MODE_NUNITS (mode); dperm.op0 = dperm.op1 = gen_reg_rtx (mode); + dperm.one_operand_p = true; /* Extend to SImode using a paradoxical SUBREG. */ tmp1 = gen_reg_rtx (SImode); @@ -35681,7 +35729,7 @@ expand_vec_perm_blend (struct expand_vec_perm_d *d) rtx target, op0, op1, x; rtx rperm[32], vperm; - if (d->op0 == d->op1) + if (d->one_operand_p) return false; if (TARGET_AVX2 && GET_MODE_SIZE (vmode) == 32) ; @@ -35868,7 +35916,7 @@ expand_vec_perm_vpermil (struct expand_vec_perm_d *d) rtx rperm[8], vperm; unsigned i; - if (!TARGET_AVX || d->vmode != V8SFmode || d->op0 != d->op1) + if (!TARGET_AVX || d->vmode != V8SFmode || !d->one_operand_p) return false; /* We can only permute within the 128-bit lane. */ @@ -35944,7 +35992,7 @@ expand_vec_perm_pshufb (struct expand_vec_perm_d *d) nelt = d->nelt; - if (d->op0 != d->op1) + if (!d->one_operand_p) { if (!TARGET_XOP || GET_MODE_SIZE (d->vmode) != 16) { @@ -36032,7 +36080,7 @@ expand_vec_perm_pshufb (struct expand_vec_perm_d *d) else { eltsz = GET_MODE_SIZE (GET_MODE_INNER (d->vmode)); - if (d->op0 != d->op1) + if (!d->one_operand_p) mask = 2 * nelt - 1; else if (vmode == V16QImode) mask = nelt - 1; @@ -36059,7 +36107,7 @@ expand_vec_perm_pshufb (struct expand_vec_perm_d *d) target = gen_lowpart (vmode, d->target); op0 = gen_lowpart (vmode, d->op0); - if (d->op0 == d->op1) + if (d->one_operand_p) { if (vmode == V16QImode) emit_insn (gen_ssse3_pshufbv16qi3 (target, op0, vperm)); @@ -36091,7 +36139,7 @@ expand_vec_perm_1 (struct expand_vec_perm_d *d) /* Check plain VEC_SELECT first, because AVX has instructions that could match both SEL and SEL+CONCAT, but the plain SEL will allow a memory input where SEL+CONCAT may not. */ - if (d->op0 == d->op1) + if (d->one_operand_p) { int mask = nelt - 1; bool identity_perm = true; @@ -36188,7 +36236,7 @@ expand_vec_perm_1 (struct expand_vec_perm_d *d) return true; /* Recognize interleave style patterns with reversed operands. */ - if (d->op0 != d->op1) + if (!d->one_operand_p) { for (i = 0; i < nelt; ++i) { @@ -36231,7 +36279,7 @@ expand_vec_perm_pshuflw_pshufhw (struct expand_vec_perm_d *d) unsigned i; bool ok; - if (d->vmode != V8HImode || d->op0 != d->op1) + if (d->vmode != V8HImode || !d->one_operand_p) return false; /* The two permutations only operate in 64-bit lanes. */ @@ -36303,6 +36351,7 @@ expand_vec_perm_palignr (struct expand_vec_perm_d *d) gen_lowpart (TImode, d->op0), shift)); d->op0 = d->op1 = d->target; + d->one_operand_p = true; in_order = true; for (i = 0; i < nelt; ++i) @@ -36342,14 +36391,14 @@ expand_vec_perm_interleave2 (struct expand_vec_perm_d *d) if (GET_MODE_SIZE (d->vmode) == 16) { - if (d->op0 == d->op1) + if (d->one_operand_p) return false; } else if (GET_MODE_SIZE (d->vmode) == 32) { if (!TARGET_AVX) return false; - /* For 32-byte modes allow even d->op0 == d->op1. + /* For 32-byte modes allow even d->one_operand_p. The lack of cross-lane shuffling in some instructions might prevent a single insn shuffle. */ dfinal = *d; @@ -36474,11 +36523,11 @@ expand_vec_perm_interleave2 (struct expand_vec_perm_d *d) if (nzcnt == 1) { - gcc_assert (d->op0 == d->op1); + gcc_assert (d->one_operand_p); nonzero_halves[1] = nonzero_halves[0]; same_halves = true; } - else if (d->op0 == d->op1) + else if (d->one_operand_p) { gcc_assert (nonzero_halves[0] == 0); gcc_assert (nonzero_halves[1] == 1); @@ -36517,7 +36566,7 @@ expand_vec_perm_interleave2 (struct expand_vec_perm_d *d) } } } - else if (d->op0 == d->op1) + else if (d->one_operand_p) return false; else if (TARGET_AVX2 && (contents & (q[0] | q[2] | q[4] | q[6])) == contents) @@ -36574,6 +36623,7 @@ expand_vec_perm_interleave2 (struct expand_vec_perm_d *d) } dfinal.op0 = gen_reg_rtx (dfinal.vmode); dfinal.op1 = dfinal.op0; + dfinal.one_operand_p = true; dremap.target = dfinal.op0; /* Test if the final remap can be done with a single insn. For V4SFmode or @@ -36617,7 +36667,7 @@ expand_vec_perm_vpermq_perm_1 (struct expand_vec_perm_d *d) if (!(TARGET_AVX2 && (d->vmode == V32QImode || d->vmode == V16HImode) - && d->op0 == d->op1)) + && d->one_operand_p)) return false; contents[0] = 0; @@ -36645,6 +36695,7 @@ expand_vec_perm_vpermq_perm_1 (struct expand_vec_perm_d *d) dremap.target = gen_reg_rtx (V4DImode); dremap.op0 = gen_lowpart (V4DImode, d->op0); dremap.op1 = dremap.op0; + dremap.one_operand_p = true; for (i = 0; i < 2; ++i) { unsigned int cnt = 0; @@ -36658,6 +36709,7 @@ expand_vec_perm_vpermq_perm_1 (struct expand_vec_perm_d *d) dfinal = *d; dfinal.op0 = gen_lowpart (dfinal.vmode, dremap.target); dfinal.op1 = dfinal.op0; + dfinal.one_operand_p = true; for (i = 0, j = 0; i < nelt; ++i) { if (i == nelt2) @@ -36697,8 +36749,7 @@ expand_vec_perm_vperm2f128 (struct expand_vec_perm_d *d) return false; dsecond = *d; - if (d->op0 == d->op1) - dsecond.op1 = gen_reg_rtx (d->vmode); + dsecond.one_operand_p = false; dsecond.testing_p = true; /* ((perm << 2)|perm) & 0x33 is the vperm2[fi]128 @@ -36767,10 +36818,7 @@ expand_vec_perm_vperm2f128 (struct expand_vec_perm_d *d) vperm2f128 on d->op0 and d->op1. */ dsecond.testing_p = false; dfirst = *d; - if (d->op0 == d->op1) - dfirst.target = dsecond.op1; - else - dfirst.target = gen_reg_rtx (d->vmode); + dfirst.target = gen_reg_rtx (d->vmode); for (i = 0; i < nelt; i++) dfirst.perm[i] = (i & (nelt2 - 1)) + ((perm >> (2 * (i >= nelt2))) & 3) * nelt2; @@ -36791,9 +36839,8 @@ expand_vec_perm_vperm2f128 (struct expand_vec_perm_d *d) return true; } - /* For d->op0 == d->op1 the only useful vperm2f128 permutation - is 0x10. */ - if (d->op0 == d->op1) + /* For one operand, the only useful vperm2f128 permutation is 0x10. */ + if (d->one_operand_p) return false; } @@ -36810,7 +36857,7 @@ expand_vec_perm_interleave3 (struct expand_vec_perm_d *d) unsigned i, nelt; rtx (*gen) (rtx, rtx, rtx); - if (d->op0 == d->op1) + if (d->one_operand_p) return false; if (TARGET_AVX2 && GET_MODE_SIZE (d->vmode) == 32) ; @@ -36893,7 +36940,7 @@ expand_vec_perm_vperm2f128_vblend (struct expand_vec_perm_d *d) if (!TARGET_AVX || TARGET_AVX2 || (d->vmode != V8SFmode && d->vmode != V4DFmode) - || d->op0 != d->op1) + || !d->one_operand_p) return false; dfirst = *d; @@ -36931,6 +36978,7 @@ expand_vec_perm_vperm2f128_vblend (struct expand_vec_perm_d *d) dsecond = *d; dsecond.op0 = dfirst.target; dsecond.op1 = dfirst.target; + dsecond.one_operand_p = true; dsecond.target = gen_reg_rtx (dsecond.vmode); for (i = 0; i < nelt; i++) dsecond.perm[i] = i ^ nelt2; @@ -36955,7 +37003,7 @@ expand_vec_perm_pshufb2 (struct expand_vec_perm_d *d) if (!TARGET_SSSE3 || GET_MODE_SIZE (d->vmode) != 16) return false; - gcc_assert (d->op0 != d->op1); + gcc_assert (!d->one_operand_p); nelt = d->nelt; eltsz = GET_MODE_SIZE (GET_MODE_INNER (d->vmode)); @@ -37010,7 +37058,7 @@ expand_vec_perm_vpshufb2_vpermq (struct expand_vec_perm_d *d) unsigned int i, nelt, eltsz; if (!TARGET_AVX2 - || d->op0 != d->op1 + || !d->one_operand_p || (d->vmode != V32QImode && d->vmode != V16HImode)) return false; @@ -37078,7 +37126,7 @@ expand_vec_perm_vpshufb2_vpermq_even_odd (struct expand_vec_perm_d *d) unsigned int i, nelt, eltsz; if (!TARGET_AVX2 - || d->op0 == d->op1 + || d->one_operand_p || (d->vmode != V32QImode && d->vmode != V16HImode)) return false; @@ -37437,7 +37485,7 @@ expand_vec_perm_broadcast (struct expand_vec_perm_d *d) { unsigned i, elt, nelt = d->nelt; - if (d->op0 != d->op1) + if (!d->one_operand_p) return false; elt = d->perm[0]; @@ -37460,7 +37508,7 @@ expand_vec_perm_vpshufb4_vpermq2 (struct expand_vec_perm_d *d) bool used[4]; if (!TARGET_AVX2 - || d->op0 == d->op1 + || d->one_operand_p || (d->vmode != V32QImode && d->vmode != V16HImode)) return false; @@ -37661,6 +37709,7 @@ ix86_expand_vec_perm_const (rtx operands[4]) perm[i] = ei; } + d.one_operand_p = true; switch (which) { default: @@ -37668,51 +37717,39 @@ ix86_expand_vec_perm_const (rtx operands[4]) case 3: if (!rtx_equal_p (d.op0, d.op1)) - break; - + { + d.one_operand_p = false; + break; + } /* The elements of PERM do not suggest that only the first operand is used, but both operands are identical. Allow easier matching of the permutation by folding the permutation into the single input vector. */ - for (i = 0; i < nelt; ++i) - if (d.perm[i] >= nelt) - d.perm[i] -= nelt; /* FALLTHRU */ - case 1: - d.op1 = d.op0; - break; - case 2: for (i = 0; i < nelt; ++i) - d.perm[i] -= nelt; + d.perm[i] &= nelt - 1; d.op0 = d.op1; break; + + case 1: + d.op1 = d.op0; + break; } if (ix86_expand_vec_perm_const_1 (&d)) return true; - /* If the mask says both arguments are needed, but they are the same, - the above tried to expand with d.op0 == d.op1. If that didn't work, - retry with d.op0 != d.op1 as that is what testing has been done with. */ - if (which == 3 && d.op0 == d.op1) + /* If the selector says both arguments are needed, but the operands are the + same, the above tried to expand with one_operand_p and flattened selector. + If that didn't work, retry without one_operand_p; we succeeded with that + during testing. */ + if (which == 3 && d.one_operand_p) { - rtx seq; - bool ok; - + d.one_operand_p = false; memcpy (d.perm, perm, sizeof (perm)); - d.op1 = gen_reg_rtx (d.vmode); - start_sequence (); - ok = ix86_expand_vec_perm_const_1 (&d); - seq = get_insns (); - end_sequence (); - if (ok) - { - emit_move_insn (d.op1, d.op0); - emit_insn (seq); - return true; - } + return ix86_expand_vec_perm_const_1 (&d); } return false; @@ -37726,7 +37763,7 @@ ix86_vectorize_vec_perm_const_ok (enum machine_mode vmode, { struct expand_vec_perm_d d; unsigned int i, nelt, which; - bool ret, one_vec; + bool ret; d.vmode = vmode; d.nelt = nelt = GET_MODE_NUNITS (d.vmode); @@ -37763,17 +37800,17 @@ ix86_vectorize_vec_perm_const_ok (enum machine_mode vmode, d.perm[i] -= nelt; /* Check whether the mask can be applied to the vector type. */ - one_vec = (which != 3); + d.one_operand_p = (which != 3); /* Implementable with shufps or pshufd. */ - if (one_vec && (d.vmode == V4SFmode || d.vmode == V4SImode)) + if (d.one_operand_p && (d.vmode == V4SFmode || d.vmode == V4SImode)) return true; /* Otherwise we have to go through the motions and see if we can figure out how to generate the requested permutation. */ d.target = gen_raw_REG (d.vmode, LAST_VIRTUAL_REGISTER + 1); d.op1 = d.op0 = gen_raw_REG (d.vmode, LAST_VIRTUAL_REGISTER + 2); - if (!one_vec) + if (!d.one_operand_p) d.op1 = gen_raw_REG (d.vmode, LAST_VIRTUAL_REGISTER + 3); start_sequence (); @@ -37794,6 +37831,7 @@ ix86_expand_vec_extract_even_odd (rtx targ, rtx op0, rtx op1, unsigned odd) d.op1 = op1; d.vmode = GET_MODE (targ); d.nelt = nelt = GET_MODE_NUNITS (d.vmode); + d.one_operand_p = false; d.testing_p = false; for (i = 0; i < nelt; ++i) diff --git a/gcc/config/i386/i386.h b/gcc/config/i386/i386.h index a53c70a31dc..7ba90c764f9 100644 --- a/gcc/config/i386/i386.h +++ b/gcc/config/i386/i386.h @@ -42,7 +42,6 @@ see the files COPYING3 and COPYING.RUNTIME respectively. If not, see /* Redefines for option macros. */ #define TARGET_64BIT OPTION_ISA_64BIT -#define TARGET_X32 OPTION_ISA_X32 #define TARGET_MMX OPTION_ISA_MMX #define TARGET_3DNOW OPTION_ISA_3DNOW #define TARGET_3DNOW_A OPTION_ISA_3DNOW_A @@ -77,7 +76,8 @@ see the files COPYING3 and COPYING.RUNTIME respectively. If not, see #define TARGET_F16C OPTION_ISA_F16C #define TARGET_RTM OPTION_ISA_RTM -#define TARGET_LP64 (TARGET_64BIT && !TARGET_X32) +#define TARGET_LP64 OPTION_ABI_64 +#define TARGET_X32 OPTION_ABI_X32 /* SSE4.1 defines round instructions */ #define OPTION_MASK_ISA_ROUND OPTION_MASK_ISA_SSE4_1 diff --git a/gcc/config/i386/i386.opt b/gcc/config/i386/i386.opt index 29f1082b2d1..bf50aed47a8 100644 --- a/gcc/config/i386/i386.opt +++ b/gcc/config/i386/i386.opt @@ -218,7 +218,7 @@ EnumValue Enum(fpmath_unit) String(both) Value({(enum fpmath_unit) (FPMATH_SSE | FPMATH_387)}) mhard-float -Target RejectNegative Mask(80387) MaskExists Save +Target RejectNegative Mask(80387) Save Use hardware fp mieee-fp @@ -425,11 +425,11 @@ Target RejectNegative Negative(m64) Report InverseMask(ISA_64BIT) Var(ix86_isa_f Generate 32bit i386 code m64 -Target RejectNegative Negative(mx32) Report Mask(ISA_64BIT) Var(ix86_isa_flags) Save +Target RejectNegative Negative(mx32) Report Mask(ABI_64) Var(ix86_isa_flags) Save Generate 64bit x86-64 code mx32 -Target RejectNegative Negative(m32) Report Mask(ISA_X32) Var(ix86_isa_flags) Save +Target RejectNegative Negative(m32) Report Mask(ABI_X32) Var(ix86_isa_flags) Save Generate 32bit x86-64 code mmmx @@ -469,11 +469,11 @@ Target Report Mask(ISA_SSE4_2) Var(ix86_isa_flags) Save Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1 and SSE4.2 built-in functions and code generation msse4 -Target RejectNegative Report Mask(ISA_SSE4_2) MaskExists Var(ix86_isa_flags) Save +Target RejectNegative Report Mask(ISA_SSE4_2) Var(ix86_isa_flags) Save Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1 and SSE4.2 built-in functions and code generation mno-sse4 -Target RejectNegative Report InverseMask(ISA_SSE4_1) MaskExists Var(ix86_isa_flags) Save +Target RejectNegative Report InverseMask(ISA_SSE4_1) Var(ix86_isa_flags) Save Do not support SSE4.1 and SSE4.2 built-in functions and code generation msse5 diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md index 9a4728c0092..b63d774e43f 100644 --- a/gcc/config/i386/sse.md +++ b/gcc/config/i386/sse.md @@ -1175,14 +1175,14 @@ (parallel [(const_int 0)])) (vec_select:DF (match_dup 1) (parallel [(const_int 1)]))) (plusminus:DF - (vec_select:DF (match_dup 1) (parallel [(const_int 2)])) - (vec_select:DF (match_dup 1) (parallel [(const_int 3)])))) - (vec_concat:V2DF - (plusminus:DF (vec_select:DF (match_operand:V4DF 2 "nonimmediate_operand" "xm") (parallel [(const_int 0)])) - (vec_select:DF (match_dup 2) (parallel [(const_int 1)]))) + (vec_select:DF (match_dup 2) (parallel [(const_int 1)])))) + (vec_concat:V2DF + (plusminus:DF + (vec_select:DF (match_dup 1) (parallel [(const_int 2)])) + (vec_select:DF (match_dup 1) (parallel [(const_int 3)]))) (plusminus:DF (vec_select:DF (match_dup 2) (parallel [(const_int 2)])) (vec_select:DF (match_dup 2) (parallel [(const_int 3)]))))))] @@ -4901,7 +4901,7 @@ (vec_select:DF (match_dup 0) (parallel [(const_int 1)]))))] "TARGET_SSE2 && reload_completed" [(set (match_dup 0) (match_dup 1))] - "operands[0] = adjust_address (operands[0], DFmode, 8);") + "operands[0] = adjust_address (operands[0], DFmode, 0);") (define_insn "sse2_movsd" [(set (match_operand:V2DF 0 "nonimmediate_operand" "=x,x,x,x,m,x,x,x,o") diff --git a/gcc/config/ia64/ia64.c b/gcc/config/ia64/ia64.c index 98a6120c975..4b8a6929b1e 100644 --- a/gcc/config/ia64/ia64.c +++ b/gcc/config/ia64/ia64.c @@ -740,9 +740,6 @@ ia64_handle_model_attribute (tree *node, tree name, tree args, return NULL_TREE; } -/* The section must have global and overlaid attributes. */ -#define SECTION_VMS_OVERLAY SECTION_MACH_DEP - /* Part of the low level implementation of DEC Ada pragma Common_Object which enables the shared use of variables stored in overlaid linker areas corresponding to the use of Fortran COMMON. */ @@ -753,24 +750,18 @@ ia64_vms_common_object_attribute (tree *node, tree name, tree args, bool *no_add_attrs) { tree decl = *node; - tree id, val; - if (! DECL_P (decl)) - abort (); + tree id; + + gcc_assert (DECL_P (decl)); DECL_COMMON (decl) = 1; id = TREE_VALUE (args); - if (TREE_CODE (id) == IDENTIFIER_NODE) - val = build_string (IDENTIFIER_LENGTH (id), IDENTIFIER_POINTER (id)); - else if (TREE_CODE (id) == STRING_CST) - val = id; - else + if (TREE_CODE (id) != IDENTIFIER_NODE && TREE_CODE (id) != STRING_CST) { - warning (OPT_Wattributes, - "%qE attribute requires a string constant argument", name); + error ("%qE attribute requires a string constant argument", name); *no_add_attrs = true; return NULL_TREE; } - DECL_SECTION_NAME (decl) = val; return NULL_TREE; } @@ -783,50 +774,31 @@ ia64_vms_output_aligned_decl_common (FILE *file, tree decl, const char *name, { tree attr = DECL_ATTRIBUTES (decl); - /* As common_object attribute set DECL_SECTION_NAME check it before - looking up the attribute. */ - if (DECL_SECTION_NAME (decl) && attr) + if (attr) attr = lookup_attribute ("common_object", attr); - else - attr = NULL_TREE; - - if (!attr) - { - /* Code from elfos.h. */ - fprintf (file, "%s", COMMON_ASM_OP); - assemble_name (file, name); - fprintf (file, ","HOST_WIDE_INT_PRINT_UNSIGNED",%u\n", - size, align / BITS_PER_UNIT); - } - else + if (attr) { - ASM_OUTPUT_ALIGN (file, floor_log2 (align / BITS_PER_UNIT)); - ASM_OUTPUT_LABEL (file, name); - ASM_OUTPUT_SKIP (file, size ? size : 1); - } -} + tree id = TREE_VALUE (TREE_VALUE (attr)); + const char *name; -/* Definition of TARGET_ASM_NAMED_SECTION for VMS. */ + if (TREE_CODE (id) == IDENTIFIER_NODE) + name = IDENTIFIER_POINTER (id); + else if (TREE_CODE (id) == STRING_CST) + name = TREE_STRING_POINTER (id); + else + abort (); -void -ia64_vms_elf_asm_named_section (const char *name, unsigned int flags, - tree decl) -{ - if (!(flags & SECTION_VMS_OVERLAY)) - { - default_elf_asm_named_section (name, flags, decl); - return; + fprintf (file, "\t.vms_common\t\"%s\",", name); } - if (flags != (SECTION_VMS_OVERLAY | SECTION_WRITE)) - abort (); + else + fprintf (file, "%s", COMMON_ASM_OP); - if (flags & SECTION_DECLARED) - { - fprintf (asm_out_file, "\t.section\t%s\n", name); - return; - } + /* Code from elfos.h. */ + assemble_name (file, name); + fprintf (file, ","HOST_WIDE_INT_PRINT_UNSIGNED",%u", + size, align / BITS_PER_UNIT); - fprintf (asm_out_file, "\t.section\t%s,\"awgO\"\n", name); + fputc ('\n', file); } static void @@ -10536,12 +10508,6 @@ ia64_section_type_flags (tree decl, const char *name, int reloc) || strncmp (name, ".gnu.linkonce.sb.", 17) == 0) flags = SECTION_SMALL; -#if TARGET_ABI_OPEN_VMS - if (decl && DECL_ATTRIBUTES (decl) - && lookup_attribute ("common_object", DECL_ATTRIBUTES (decl))) - flags |= SECTION_VMS_OVERLAY; -#endif - flags |= default_section_type_flags (decl, name, reloc); return flags; } diff --git a/gcc/config/ia64/vms.h b/gcc/config/ia64/vms.h index 11f017663b5..3e81d769897 100644 --- a/gcc/config/ia64/vms.h +++ b/gcc/config/ia64/vms.h @@ -121,9 +121,6 @@ STATIC func_ptr __CTOR_LIST__[1] \ #undef TARGET_VALID_POINTER_MODE #define TARGET_VALID_POINTER_MODE ia64_vms_valid_pointer_mode -#undef TARGET_ASM_NAMED_SECTION -#define TARGET_ASM_NAMED_SECTION ia64_vms_elf_asm_named_section - /* Define this macro if it is advisable to hold scalars in registers in a wider mode than that declared by the program. In such cases, the value is constrained to be within the bounds of the declared diff --git a/gcc/config/linux-android.h b/gcc/config/linux-android.h index 94c52748fdb..acbc6627f95 100644 --- a/gcc/config/linux-android.h +++ b/gcc/config/linux-android.h @@ -53,8 +53,8 @@ "%{!static: -ldl}" #define ANDROID_STARTFILE_SPEC \ - "%{!shared:" \ + "%{shared: crtbegin_so%O%s;:" \ " %{static: crtbegin_static%O%s;: crtbegin_dynamic%O%s}}" #define ANDROID_ENDFILE_SPEC \ - "%{!shared: crtend_android%O%s}" + "%{shared: crtend_so%O%s;: crtend_android%O%s}" diff --git a/gcc/config/m68k/m68k.opt b/gcc/config/m68k/m68k.opt index 14428fc4ccc..00bc2d541ef 100644 --- a/gcc/config/m68k/m68k.opt +++ b/gcc/config/m68k/m68k.opt @@ -136,7 +136,7 @@ Target RejectNegative Generate code for a Fido A mhard-float -Target RejectNegative Mask(HARD_FLOAT) MaskExists +Target RejectNegative Mask(HARD_FLOAT) Generate code which uses hardware floating point instructions mid-shared-library diff --git a/gcc/config/mep/mep.opt b/gcc/config/mep/mep.opt index 38b8f80527b..0ea19e6efaa 100644 --- a/gcc/config/mep/mep.opt +++ b/gcc/config/mep/mep.opt @@ -55,7 +55,7 @@ Target Mask(COP) Enable MeP Coprocessor mcop32 -Target Mask(COP) MaskExists RejectNegative +Target Mask(COP) RejectNegative Enable MeP Coprocessor with 32-bit registers mcop64 diff --git a/gcc/config/pa/pa-hpux.opt b/gcc/config/pa/pa-hpux.opt index ed5d6a4bd79..b709b83bf40 100644 --- a/gcc/config/pa/pa-hpux.opt +++ b/gcc/config/pa/pa-hpux.opt @@ -23,7 +23,7 @@ Variable int flag_pa_unix = TARGET_HPUX_11_31 ? 2003 : TARGET_HPUX_11_11 ? 1998 : TARGET_HPUX_10_10 ? 1995 : 1993 msio -Target RejectNegative Mask(SIO) MaskExists +Target RejectNegative Mask(SIO) Generate cpp defines for server IO munix=93 diff --git a/gcc/config/pa/pa64-hpux.opt b/gcc/config/pa/pa64-hpux.opt index 36b1c61ea88..56ca35ea9c6 100644 --- a/gcc/config/pa/pa64-hpux.opt +++ b/gcc/config/pa/pa64-hpux.opt @@ -19,7 +19,7 @@ ; <http://www.gnu.org/licenses/>. mgnu-ld -Target RejectNegative Mask(GNU_LD) MaskExists +Target RejectNegative Mask(GNU_LD) Assume code will be linked by GNU ld mhp-ld diff --git a/gcc/config/picochip/picochip.opt b/gcc/config/picochip/picochip.opt index 4726f499377..a4b25e52f50 100644 --- a/gcc/config/picochip/picochip.opt +++ b/gcc/config/picochip/picochip.opt @@ -43,4 +43,4 @@ Target Mask(INEFFICIENT_WARNINGS) Generate warnings when inefficient code is known to be generated. minefficient -Target Mask(INEFFICIENT_WARNINGS) MaskExists Undocumented +Target Mask(INEFFICIENT_WARNINGS) Undocumented diff --git a/gcc/config/rs6000/sysv4.opt b/gcc/config/rs6000/sysv4.opt index 0d8d955af12..474203d6adb 100644 --- a/gcc/config/rs6000/sysv4.opt +++ b/gcc/config/rs6000/sysv4.opt @@ -66,7 +66,7 @@ Target Report RejectNegative Mask(LITTLE_ENDIAN) Produce little endian code mlittle -Target Report RejectNegative Mask(LITTLE_ENDIAN) MaskExists +Target Report RejectNegative Mask(LITTLE_ENDIAN) Produce little endian code mbig-endian diff --git a/gcc/config/sh/sh.c b/gcc/config/sh/sh.c index 68e6034203c..3e85fcf3e6c 100644 --- a/gcc/config/sh/sh.c +++ b/gcc/config/sh/sh.c @@ -6487,7 +6487,9 @@ push_regs (HARD_REG_SET *mask, int interrupt_handler) use_movml = true; } - if (use_movml) + if (sh_cfun_resbank_handler_p ()) + ; /* Do nothing. */ + else if (use_movml) { rtx x, mem, reg, set; rtx sp_reg = gen_rtx_REG (SImode, STACK_POINTER_REGNUM); @@ -7485,7 +7487,9 @@ sh_expand_epilogue (bool sibcall_p) use_movml = true; } - if (use_movml) + if (sh_cfun_resbank_handler_p ()) + ; /* Do nothing. */ + else if (use_movml) { rtx sp_reg = gen_rtx_REG (SImode, STACK_POINTER_REGNUM); @@ -9783,13 +9787,80 @@ legitimize_pic_address (rtx orig, enum machine_mode mode ATTRIBUTE_UNUSED, return orig; } -/* Try machine-dependent ways of modifying an illegitimate address - to be legitimate. If we find one, return the new, valid address. - Otherwise, return X. +/* Given a (logical) mode size and an offset in bytes, try to find a the + appropriate displacement value for a mov insn. On SH the displacements + are limited to max. 60 bytes for SImode, max. 30 bytes in HImode and max. + 15 bytes in QImode. To compensate this we create a new base address by + adding an adjustment value to it. + + If the originally requested offset is greater than 127 we prefer using + values 124..127 over 128..131 to increase opportunities to use the + add #imm, Rn insn. + + In some cases it is possible that a requested offset might seem unaligned + or inappropriate for the mode size, like offset = 2 and mode size = 4. + This is compensated by adjusting the base address so that the effective + address of the displacement move insn will be aligned. + + This is not the best possible way of rebasing the base address, as it + does not look at other present displacement addressings around it. + In some cases this can create more base address adjustments than would + actually be necessary. */ + +struct disp_adjust +{ + rtx offset_adjust; + rtx mov_disp; + int max_mov_disp; +}; + +static struct disp_adjust +sh_find_mov_disp_adjust (int mode_sz, HOST_WIDE_INT offset) +{ + struct disp_adjust res = { NULL_RTX, NULL_RTX, 0 }; + + /* The max. available mode for actual move insns is SImode. + Larger accesses will be split into multiple loads/stores. */ + const int max_mov_sz = GET_MODE_SIZE (SImode); + + const int mov_insn_size = mode_sz >= max_mov_sz ? max_mov_sz : mode_sz; + const HOST_WIDE_INT max_disp = 15 * mov_insn_size; + HOST_WIDE_INT align_modifier = offset > 127 ? mov_insn_size : 0; + + HOST_WIDE_INT offset_adjust; + + /* In some cases this actually does happen and we must check for it. */ + if (mode_sz < 1 || mode_sz > 8) + return res; + + /* FIXME: HImode with displacement addressing is not supported yet. + Make it purposefully fail for now. */ + if (mov_insn_size == 2) + return res; - For the SH, if X is almost suitable for indexing, but the offset is - out of range, convert it into a normal form so that CSE has a chance - of reducing the number of address registers used. */ + /* Keeps the previous behavior for QImode displacement addressing. + This just decides how the offset is re-based. Removing this special + case will result in slightly bigger code on average, but it's not that + bad actually. */ + if (mov_insn_size == 1) + align_modifier = 0; + + res.max_mov_disp = max_disp + mov_insn_size; + + offset_adjust = ((offset + align_modifier) & ~max_disp) - align_modifier; + + if (mode_sz + offset - offset_adjust <= res.max_mov_disp) + { + res.offset_adjust = GEN_INT (offset_adjust); + res.mov_disp = GEN_INT (offset - offset_adjust); + } + + return res; +} + +/* Try to modify an illegitimate address and make it legitimate. + If we find one, return the new, valid address. + Otherwise, return the original address. */ static rtx sh_legitimize_address (rtx x, rtx oldx, enum machine_mode mode) @@ -9797,66 +9868,33 @@ sh_legitimize_address (rtx x, rtx oldx, enum machine_mode mode) if (flag_pic) x = legitimize_pic_address (oldx, mode, NULL_RTX); - if (GET_CODE (x) == PLUS - && (GET_MODE_SIZE (mode) == 4 - || GET_MODE_SIZE (mode) == 8) - && CONST_INT_P (XEXP (x, 1)) - && BASE_REGISTER_RTX_P (XEXP (x, 0)) - && ! TARGET_SHMEDIA - && ! ((TARGET_SH4 || TARGET_SH2A_DOUBLE) && mode == DFmode) - && ! (TARGET_SH2E && mode == SFmode)) - { - rtx index_rtx = XEXP (x, 1); - HOST_WIDE_INT offset = INTVAL (index_rtx), offset_base; - rtx sum; - - /* On rare occasions, we might get an unaligned pointer - that is indexed in a way to give an aligned address. - Therefore, keep the lower two bits in offset_base. */ - /* Instead of offset_base 128..131 use 124..127, so that - simple add suffices. */ - if (offset > 127) - offset_base = ((offset + 4) & ~60) - 4; - else - offset_base = offset & ~60; - - /* Sometimes the normal form does not suit DImode. We - could avoid that by using smaller ranges, but that - would give less optimized code when SImode is - prevalent. */ - if (GET_MODE_SIZE (mode) + offset - offset_base <= 64) - { - sum = expand_binop (Pmode, add_optab, XEXP (x, 0), - GEN_INT (offset_base), NULL_RTX, 0, - OPTAB_LIB_WIDEN); + if (TARGET_SHMEDIA) + return x; - return gen_rtx_PLUS (Pmode, sum, GEN_INT (offset - offset_base)); - } - } + if (((TARGET_SH4 || TARGET_SH2A_DOUBLE) && mode == DFmode) + || (TARGET_SH2E && mode == SFmode)) + return x; - /* This could be generalized for SImode, HImode, QImode displacement - addressing. */ - if (mode == QImode && GET_CODE (x) == PLUS - && BASE_REGISTER_RTX_P (XEXP (x, 0)) && CONST_INT_P (XEXP (x, 1))) + if (GET_CODE (x) == PLUS && CONST_INT_P (XEXP (x, 1)) + && BASE_REGISTER_RTX_P (XEXP (x, 0))) { - rtx index_rtx = XEXP (x, 1); - HOST_WIDE_INT offset = INTVAL (index_rtx); - HOST_WIDE_INT offset_base = offset & ~15; - - if (offset - offset_base <= 16) + const int mode_sz = GET_MODE_SIZE (mode); + struct disp_adjust adj = sh_find_mov_disp_adjust (mode_sz, + INTVAL (XEXP (x, 1))); + + if (adj.offset_adjust != NULL_RTX && adj.mov_disp != NULL_RTX) { rtx sum = expand_binop (Pmode, add_optab, XEXP (x, 0), - GEN_INT (offset_base), NULL_RTX, 0, - OPTAB_LIB_WIDEN); - - return gen_rtx_PLUS (Pmode, sum, GEN_INT (offset - offset_base)); + adj.offset_adjust, NULL_RTX, 0, + OPTAB_LIB_WIDEN); + return gen_rtx_PLUS (Pmode, sum, adj.mov_disp); } } return x; } -/* Attempt to replace *P, which is an address that needs reloading, with +/* Attempt to replace *p, which is an address that needs reloading, with a valid memory address for an operand of mode MODE. Like for sh_legitimize_address, for the SH we try to get a normal form of the address. That will allow inheritance of the address reloads. */ @@ -9866,75 +9904,71 @@ sh_legitimize_reload_address (rtx *p, enum machine_mode mode, int opnum, int itype) { enum reload_type type = (enum reload_type) itype; + const int mode_sz = GET_MODE_SIZE (mode); - if (GET_CODE (*p) == PLUS - && (GET_MODE_SIZE (mode) == 4 || GET_MODE_SIZE (mode) == 8) - && CONST_INT_P (XEXP (*p, 1)) + if (TARGET_SHMEDIA) + return false; + + if (GET_CODE (*p) == PLUS && CONST_INT_P (XEXP (*p, 1)) && MAYBE_BASE_REGISTER_RTX_P (XEXP (*p, 0), true) - && ! TARGET_SHMEDIA - && ! (TARGET_SH4 && mode == DFmode) && ! (mode == PSImode && type == RELOAD_FOR_INPUT_ADDRESS) && (ALLOW_INDEXED_ADDRESS || XEXP (*p, 0) == stack_pointer_rtx || XEXP (*p, 0) == hard_frame_pointer_rtx)) { - rtx index_rtx = XEXP (*p, 1); - HOST_WIDE_INT offset = INTVAL (index_rtx), offset_base; - rtx sum; + const HOST_WIDE_INT offset = INTVAL (XEXP (*p, 1)); + struct disp_adjust adj = sh_find_mov_disp_adjust (mode_sz, offset); if (TARGET_SH2A && mode == DFmode && (offset & 0x7)) { push_reload (*p, NULL_RTX, p, NULL, BASE_REG_CLASS, Pmode, VOIDmode, 0, 0, opnum, type); - goto win; + return true; } + if (TARGET_SH2E && mode == SFmode) { *p = copy_rtx (*p); push_reload (*p, NULL_RTX, p, NULL, BASE_REG_CLASS, Pmode, VOIDmode, 0, 0, opnum, type); - goto win; + return true; } - /* Instead of offset_base 128..131 use 124..127, so that - simple add suffices. */ - if (offset > 127) - offset_base = ((offset + 4) & ~60) - 4; - else - offset_base = offset & ~60; - /* Sometimes the normal form does not suit DImode. We could avoid - that by using smaller ranges, but that would give less optimized - code when SImode is prevalent. */ - if (GET_MODE_SIZE (mode) + offset - offset_base <= 64) - { - sum = gen_rtx_PLUS (Pmode, XEXP (*p, 0), GEN_INT (offset_base)); - *p = gen_rtx_PLUS (Pmode, sum, GEN_INT (offset - offset_base)); + + /* FIXME: Do not allow to legitimize QImode and HImode displacement + moves because then reload has a problem figuring the constraint + that the move insn target/source reg must be R0. + Or maybe some handling is wrong in sh_secondary_reload for this + to work properly? */ + if ((mode_sz == 4 || mode_sz == 8) + && ! (TARGET_SH4 && mode == DFmode) + && adj.offset_adjust != NULL_RTX && adj.mov_disp != NULL_RTX) + { + rtx sum = gen_rtx_PLUS (Pmode, XEXP (*p, 0), adj.offset_adjust); + *p = gen_rtx_PLUS (Pmode, sum, adj.mov_disp); push_reload (sum, NULL_RTX, &XEXP (*p, 0), NULL, BASE_REG_CLASS, Pmode, VOIDmode, 0, 0, opnum, type); - goto win; + return true; } } + /* We must re-recognize what we created before. */ - else if (GET_CODE (*p) == PLUS - && (GET_MODE_SIZE (mode) == 4 || GET_MODE_SIZE (mode) == 8) - && GET_CODE (XEXP (*p, 0)) == PLUS - && CONST_INT_P (XEXP (XEXP (*p, 0), 1)) - && MAYBE_BASE_REGISTER_RTX_P (XEXP (XEXP (*p, 0), 0), true) - && CONST_INT_P (XEXP (*p, 1)) - && ! TARGET_SHMEDIA - && ! (TARGET_SH2E && mode == SFmode)) + if (GET_CODE (*p) == PLUS + && (mode_sz == 4 || mode_sz == 8) + && GET_CODE (XEXP (*p, 0)) == PLUS + && CONST_INT_P (XEXP (XEXP (*p, 0), 1)) + && MAYBE_BASE_REGISTER_RTX_P (XEXP (XEXP (*p, 0), 0), true) + && CONST_INT_P (XEXP (*p, 1)) + && ! (TARGET_SH2E && mode == SFmode)) { /* Because this address is so complex, we know it must have been created by LEGITIMIZE_RELOAD_ADDRESS before; thus, it is already unshared, and needs no further unsharing. */ push_reload (XEXP (*p, 0), NULL_RTX, &XEXP (*p, 0), NULL, BASE_REG_CLASS, Pmode, VOIDmode, 0, 0, opnum, type); - goto win; + return true; } return false; - - win: - return true; } /* In the name of slightly smaller debug output, and to cater to diff --git a/gcc/config/sh/sh.opt b/gcc/config/sh/sh.opt index 7f7af999299..3ab2c51be4a 100644 --- a/gcc/config/sh/sh.opt +++ b/gcc/config/sh/sh.opt @@ -316,7 +316,7 @@ Target Report RejectNegative Mask(RELAX) Shorten address references during linking mrenesas -Target Mask(HITACHI) MaskExists +Target Mask(HITACHI) Follow Renesas (formerly Hitachi) / SuperH calling conventions msoft-atomic diff --git a/gcc/config/sparc/long-double-switch.opt b/gcc/config/sparc/long-double-switch.opt index eb3c1a00f68..8ad32bd6fe1 100644 --- a/gcc/config/sparc/long-double-switch.opt +++ b/gcc/config/sparc/long-double-switch.opt @@ -19,7 +19,7 @@ ; <http://www.gnu.org/licenses/>. mlong-double-128 -Target Report RejectNegative Mask(LONG_DOUBLE_128) MaskExists +Target Report RejectNegative Mask(LONG_DOUBLE_128) Use 128-bit long double mlong-double-64 diff --git a/gcc/config/sparc/sparc.opt b/gcc/config/sparc/sparc.opt index 01f3d43b2ca..58ba6b79da1 100644 --- a/gcc/config/sparc/sparc.opt +++ b/gcc/config/sparc/sparc.opt @@ -30,7 +30,7 @@ Target Report Mask(FPU) Use hardware FP mhard-float -Target RejectNegative Mask(FPU) MaskExists +Target RejectNegative Mask(FPU) Use hardware FP msoft-float diff --git a/gcc/config/v850/v850.opt b/gcc/config/v850/v850.opt index 12b0937391d..8fe244b0312 100644 --- a/gcc/config/v850/v850.opt +++ b/gcc/config/v850/v850.opt @@ -102,7 +102,7 @@ Target RejectNegative Mask(V850E1) Compile for the v850e1 processor mv850es -Target RejectNegative Mask(V850E1) MaskExists +Target RejectNegative Mask(V850E1) Compile for the v850es variant of the v850e1 mv850e2 diff --git a/gcc/config/vax/vax.opt b/gcc/config/vax/vax.opt index 82d6dee6422..83527adfbea 100644 --- a/gcc/config/vax/vax.opt +++ b/gcc/config/vax/vax.opt @@ -31,7 +31,7 @@ Target RejectNegative Mask(G_FLOAT) Generate GFLOAT double precision code mg-float -Target RejectNegative Mask(G_FLOAT) MaskExists +Target RejectNegative Mask(G_FLOAT) Generate GFLOAT double precision code mgnu diff --git a/gcc/config/vms/make-crtlmap.awk b/gcc/config/vms/make-crtlmap.awk index 6f82dee7aa8..63be6e708ab 100644 --- a/gcc/config/vms/make-crtlmap.awk +++ b/gcc/config/vms/make-crtlmap.awk @@ -40,13 +40,13 @@ BEGIN { print "{ \"" $1 "\", " if (NF == 1) print "0 }" - else if (NF == 2) - printf "VMS_CRTL_" $2 " }" - else if (NF == 3) - printf "VMS_CRTL_" $2 " | VMS_CRTL_" $3 " }" else - # To be fixed. - exit 1 + { + printf "VMS_CRTL_" $2 + for (i = 3; i <= NF; i++) + printf " | VMS_CRTL_" $i + printf " }" + } } END { diff --git a/gcc/config/vms/t-vms b/gcc/config/vms/t-vms index 4e20bde8070..f2161b7861b 100644 --- a/gcc/config/vms/t-vms +++ b/gcc/config/vms/t-vms @@ -34,3 +34,8 @@ vms-c.o: $(srcdir)/config/vms/vms-c.c $(CONFIG_H) $(SYSTEM_H) coretypes.h \ $(TM_P_H) $(COMPILER) -c $(ALL_COMPILERFLAGS) $(ALL_CPPFLAGS) $(INCLUDES) \ $(PREPROCESSOR_DEFINES) $< -o $@ + +vms-f.o: $(srcdir)/config/vms/vms-f.c $(CONFIG_H) $(SYSTEM_H) coretypes.h \ + $(TM_H) + $(COMPILER) -c $(ALL_COMPILERFLAGS) $(ALL_CPPFLAGS) $(INCLUDES) \ + $(PREPROCESSOR_DEFINES) $< -o $@ diff --git a/gcc/config/vms/vms-c.c b/gcc/config/vms/vms-c.c index 6f8a1cf6138..09172b261ab 100644 --- a/gcc/config/vms/vms-c.c +++ b/gcc/config/vms/vms-c.c @@ -120,7 +120,9 @@ vms_pragma_nomember_alignment (cpp_reader *pfile ATTRIBUTE_UNUSED) if (arg[0] == '_' && arg[1] == '_') arg += 2; - if (strcmp (arg, "word") == 0) + if (strcmp (arg, "byte") == 0) + maximum_field_alignment = 1 * BITS_PER_UNIT; + else if (strcmp (arg, "word") == 0) maximum_field_alignment = 2 * BITS_PER_UNIT; else if (strcmp (arg, "longword") == 0) maximum_field_alignment = 4 * BITS_PER_UNIT; @@ -453,6 +455,9 @@ vms_c_register_includes (const char *sysroot, void vms_c_common_override_options (void) { + /* Allow variadic functions without parameters (as declared in starlet). */ + flag_allow_parameterless_variadic_functions = TRUE; + /* Initialize c_default_pointer_mode. */ switch (flag_vms_pointer_size) { diff --git a/gcc/config/vms/vms-crtlmap.map b/gcc/config/vms/vms-crtlmap.map index d98afacc17f..e80e2afe493 100644 --- a/gcc/config/vms/vms-crtlmap.map +++ b/gcc/config/vms/vms-crtlmap.map @@ -12,130 +12,483 @@ # - Comment lines start with '#' in the first column. # - map lines consist in an identifier optionnaly followed by at most 2 # space-separated flags. -# Flags are: -# FLOAT: will be prefixed by 't'/'g'/'d'. -# 64: There is a 64-bit variant. -# GLOBAL: name will be prefixed by ga_ -# BSD44: name will be prefixed by __bsd44__. -# LDBL: a 'x' prefix will be added if 128 bit long doubles are enabled. -# MALLOC: malloc related function. +# Flags are described in vms.c (prefixed by VMS_CRTL_). # # Keep entries alpha-sorted - this is enforced by the awk script. # +__32_getpwent +__32_getpwnam +__32_getpwuid +__32_sigaction __32_signal __32_ssignal +__64_getpwent +__64_getpwnam +__64_getpwuid +__64_sigaction __64_signal __64_ssignal +__assert +__dl__xpv +__freeaddrinfo32 +__freeaddrinfo64 +__getaddrinfo32 +__getaddrinfo64 +__getaddrinfo_compat4332 +__getaddrinfo_compat4364 +__getgrent64 +__getgrgid64 +__getgrgid_r64 +__getgrnam64 +__getgrnam_r64 +__lgamma FLOAT64 FLOATV2 +__lgammaf FLOAT32 FLOATV2 +__lgammal FLOAT64 FLOAT128 FLOATV2 +__long_gid___32_getpwnam +__long_gid___32_getpwuid +__long_gid___64_getpwnam +__long_gid___64_getpwuid +__long_gid_access +__long_gid_chmod +__long_gid_chown +__long_gid_fchmod +__long_gid_fchown +__long_gid_fstat +__long_gid_ftw +__long_gid_getegid +__long_gid_geteuid +__long_gid_getgid +__long_gid_getgroups +__long_gid_getpwnam +__long_gid_getpwnam_r 64 +__long_gid_getpwuid +__long_gid_getpwuid_r 64 +__long_gid_getuid +__long_gid_lchown +__long_gid_lstat +__long_gid_setgid +__long_gid_setuid +__long_gid_stat +__non_utc_ftw +__nw__xui +__off64_fcntl +__off64_fseeko +__off64_fstat +__off64_ftello +__off64_ftruncate +__off64_ftw +__off64_long_gid_fstat +__off64_long_gid_ftw +__off64_long_gid_lstat +__off64_long_gid_stat +__off64_lseek +__off64_lstat +__off64_mmap 64 +__off64_non_utc_ftw +__off64_pread +__off64_pwrite +__off64_stat +__off64_truncate +__off64_utc_fstat +__off64_utc_lstat +__off64_utc_stat +__pdam_wcsftime +__pdam_wcstok 64 __posix__exit __posix_exit __posix_kill __posix_long_gid_kill +__posix_system +__posix_wait +__read_rnd +__recvmsg32 BSD44 +__recvmsg64 BSD44 +__sendmsg32 BSD44 +__sendmsg64 BSD44 +__short_gid___32_getpwent +__short_gid___64_getpwent +__short_gid_getpwent +__std_fstat +__std_ftw +__std_lstat +__std_stat +__unix_geteuid __unix_getuid +__utc_ctime +__utc_ctime_r __utc_fstat +__utc_ftime +__utc_gmtime +__utc_gmtime_r __utc_localtime __utc_localtime_r __utc_lstat +__utc_mktime +__utc_pdam_wcsftime __utc_stat __utc_strftime __utc_time +__utc_utime +__utc_utimes +__utc_wcsftime __utctz_gmtime +__utctz_gmtime_r __utctz_localtime __utctz_localtime_r +__vms_pclose +__vms_wait3 +__vms_wait4 +__vms_waitpid +__writev32 +__writev64 +_exit +_fstat +a64l abort abs -accept +accept BSD44 access -acos FLOAT +acos FLOAT64 DPML +acosd FLOAT64_VAXD DPML +acosdl FLOAT64_VAXD +acosh FLOAT64_VAXD DPML +acoshl FLOAT64_VAXD +acosl FLOAT64_VAXD alarm asctime asctime_r -asin FLOAT -atan FLOAT -atan2 FLOAT +asin FLOAT64 DPML +asind FLOAT64_VAXD DPML +asindl FLOAT64_VAXD +asinh FLOAT64_VAXD DPML +asinhl FLOAT64_VAXD +asinl FLOAT64_VAXD +atan FLOAT64 DPML +atan2 FLOAT64 DPML +atan2l FLOAT64_VAXD +atand FLOAT64_VAXD DPML +atand2 FLOAT64_VAXD DPML +atand2l FLOAT64_VAXD +atandl FLOAT64_VAXD +atanh FLOAT64_VAXD DPML +atanhl FLOAT64_VAXD +atanl FLOAT64_VAXD atexit -atof FLOAT +atof FLOAT64 atoi atol atoll atoq -basename 64 +basename 64 bcmp bcopy -bsearch 64 +bind BSD44 +box +# brk +bsd_mh GA +bsd_waddbytes +bsd_waddstr +bsearch 64 +btowc bzero -calloc 64 MALLOC -ceil FLOAT +cabs FLOAT64 FLOATV2 +cabsf FLOAT32 FLOATV2 +cabsl FLOAT64 FLOAT128 FLOATV2 +cacos DPML +cacosh DPML +calloc 64 MALLOC +calloc_opt +carg DPML +casin DPML +casinh DPML +catan DPML +catanh DPML +catclose +catgets 64 +catopen +cbrt FLOAT64_VAXD +cbrtl FLOAT64_VAXD +ccos DPML +ccosh DPML +cdiv DPML +ceil FLOAT64 DPML +ceill FLOAT64_VAXD +cexp DPML +cfree +cfree_opt chdir chmod chown clearerr +clearerr_unlocked clock +clock_getres +clock_gettime +clock_settime +clog DPML close closedir -connect -cos FLOAT -ctermid 64 +cmul DPML +cols GA +confstr +connect BSD44 +copysign FLOAT64_VAXD DPML +copysignl FLOAT64_VAXD +cos FLOAT64 DPML +cosd FLOAT64_VAXD DPML +cosdl FLOAT64_VAXD +cosh FLOAT64 DPML +coshl FLOAT64_VAXD +cosl FLOAT64_VAXD +cot FLOAT64_VAXD DPML +cotd FLOAT64_VAXD DPML +cotdl FLOAT64_VAXD +cotl FLOAT64_VAXD +cpow DPML +creat +crtl_init +crypt 64 +csin DPML +csinh DPML +csqrt DPML +ctan DPML +ctanh DPML +ctermid 64 ctime +ctime_r +cuserid 64 +daylight GL +delete +delwin +difftime FLOAT64 +dirname 64 +div dlclose dlerror dlopen dlsym +drand48 FLOAT64 +drem DPML dup dup2 -environ GLOBAL +ecvt FLOAT64 +encrypt +endgrent +endhostent +endnetent +endprotoent +endpwent +endservent +endwin +environ GA +erand48 FLOAT64 +erf FLOAT64_VAXD DPML +erfc FLOAT64_VAXD DPML +erfcl FLOAT64_VAXD +erfl FLOAT64_VAXD +errno GA +execl +execle +execlp execv execve execvp exit -exp FLOAT -fabs FLOAT +exp FLOAT64 DPML +expl FLOAT64_VAXD +expm1 FLOAT64_VAXD DPML +expm1l FLOAT64_VAXD +fabs FLOAT64 DPML +fabsl FLOAT64_VAXD +fchmod +fchown fclose fcntl +fcvt FLOAT64 fdopen feof +feof_unlocked ferror +ferror_unlocked fflush ffs fgetc -fgetname 64 MALLOC -fgets 64 +fgetc_unlocked +fgetname 64 +fgetpos +fgets 64 +fgetwc +fgetws 64 fileno -floor FLOAT +finite FLOAT64_VAXD DPML +finitel FLOAT64_VAXD +flockfile +floor FLOAT64 DPML +floorl FLOAT64_VAXD +fmod FLOAT64 DPML NODPML FLOATV2 +fmodf FLOAT32 NODPML FLOATV2 +fmodl FLOAT64 FLOAT128 NODPML FLOATV2 +# fnmatch # Overridden by libiberty. fopen +fp_class FLOAT64_VAXD DPML +fp_classl FLOAT64_VAXD fpathconf -fprintf FLOAT LDBL +fprintf FLOAT64 FLOAT128 +fprintf__cf FLOAT64 FLOAT128 fputc +fputc_unlocked fputs +fputwc +fputws fread free +free_opt +freeaddrinfo +freehostent freopen -frexp FLOAT +frexp FLOAT64 DPML +frexpl FLOAT64_VAXD +fscanf FLOAT64 FLOAT128 fseek +fseeko +fsetpos +fstat +fstatvfs +fsync ftell +ftello +ftime +ftruncate +ftrylockfile +ftw +funlockfile +fwait +fwide +fwprintf FLOAT64 FLOAT128 fwrite +fwscanf FLOAT64 FLOAT128 +gai_strerror +gamma FLOAT64 FLOATV2 +gammaf FLOAT32 FLOATV2 +gammal FLOAT64 FLOAT128 FLOATV2 +gbsd_mvprintw +gbsd_mvscanw +gbsd_mvwprintw +gbsd_mvwscanw +gbsd_printw +gbsd_scanw +gbsd_wprintw +gbsd_wscanw +gcvt FLOAT64 64 +get_errno_addr +get_vms_errno_addr +getaddrinfo +getaddrinfo_compat43 getc +getc_unlocked getchar -getcwd 64 +getchar_unlocked +getclock +getcwd 64 +getdtablesize getegid getenv geteuid getgid -gethostbyaddr -gethostbyname -getname +getgrent +getgrgid +getgrgid_r +getgrnam +getgrnam_r +getgroups +gethostaddr +gethostbyaddr BSD44 +gethostbyname BSD44 +gethostent +gethostname +getipnodebyaddr +getipnodebyname +getitimer +getlogin +getlogin_r +getname 64 +getnameinfo +getnetbyaddr +getnetbyname +getnetent +getopt 32ONLY getpagesize +getpeername BSD44 +getpgid +getpgrp getpid +getppid +getprotobyname +getprotobynumber +getprotoent getpwent getpwnam +getpwnam_r 64 +getpwuid +getpwuid_r 64 +gets 64 getservbyname getservbyport +getservent +getsid +getsockname BSD44 getsockopt gettimeofday getuid +getw +getwc +getwchar +glob 64 +globfree 64 gmtime +gmtime_r +gsignal +herror +hostalias +hstrerror +htonl htons +hypot FLOAT64 DPML NODPML FLOATV2 +hypotf FLOAT32 NODPML FLOATV2 +hypotl FLOAT64 FLOAT128 NODPML FLOATV2 iconv -index 64 +iconv_close +iconv_open +if_freenameindex +if_indextoname +if_nameindex +if_nametoindex +ilogb DPML +index 64 +inet6_opt_append +inet6_opt_find +inet6_opt_finish +inet6_opt_get_val +inet6_opt_init +inet6_opt_next +inet6_opt_set_val +inet6_rth_add +inet6_rth_getaddr +inet6_rth_init +inet6_rth_reverse +inet6_rth_segments +inet6_rth_space +inet_addr +inet_aton +inet_lnaof +inet_makeaddr +inet_netof +inet_network +inet_ntoa +inet_ntop +inet_pton +initscr +initstate ioctl isalnum isalpha @@ -146,128 +499,432 @@ iscntrl isdigit isgraph islower +isnan FLOAT64_VAXD DPML +isnanl FLOAT64_VAXD isprint ispunct isspace isupper +iswalnum +iswalpha +iswcntrl +iswctype +iswdigit +iswgraph +iswlower +iswprint +iswpunct +iswspace +iswupper +iswxdigit isxdigit +j0 FLOAT64_VAXD DPML +j0l FLOAT64_VAXD +j1 FLOAT64_VAXD DPML +j1l FLOAT64_VAXD +jn FLOAT64_VAXD DPML +jnl FLOAT64_VAXD +jrand48 kill -ldexp FLOAT +l64a +l64a_r +labs +lchown +lcong48 +ldexp FLOAT64 DPML +ldexpl FLOAT64_VAXD +ldiv +lgamma FLOAT64 DPML NODPML FLOATV2 +lgammaf FLOAT32 NODPML FLOATV2 +lgammal FLOAT64 FLOAT128 NODPML FLOATV2 +lines GA +link +listen +llabs +lldiv locale localeconv localtime localtime_r -log FLOAT -log10 FLOAT +# ln -> log DPML +log FLOAT64 FLOATV2 +log10 FLOAT64 DPML +log10l FLOAT64_VAXD +log1p FLOAT64_VAXD DPML +log1pl FLOAT64_VAXD +log2 FLOAT64_VAXD DPML +log2l FLOAT64_VAXD +logb FLOAT64_VAXD DPML +logbl FLOAT64_VAXD +logf FLOAT32 FLOATV2 +logl FLOAT64 FLOAT128 FLOATV2 longjmp +longname 64 +lrand48 +lround DPML lseek -malloc 64 MALLOC -mbstowcs 64 -memchr 64 +lstat +lwait +malloc 64 MALLOC +malloc_opt +mblen +mbrlen +mbrtowc +mbsinit +mbsrtowcs 64 +mbstowcs +mbtowc +memccpy 64 +memchr 64 memcmp -memcpy 64 -memmove 64 -memset 64 +memcpy 64 +memmove 64 +memset 64 mkdir mkstemp -mktemp 64 -mmap 64 +mktemp 64 +mktime +mmap 64 +modf FLOAT64 DPML +modfl FLOAT64_VAXD +mprotect +mrand48 +msync munmap +mvwaddstr +mvwin nanosleep +newwin +nextafter FLOAT64_VAXD DPML +nextafterl FLOAT64_VAXD +nice +nint FLOAT64_VAXD DPML +nintl FLOAT64_VAXD nl_langinfo +nrand48 +ntohl +ntohs open opendir +optarg GA 32ONLY +opterr GL 32ONLY +optind GL 32ONLY +optopt GL 32ONLY +overlay +overwrite pathconf +pause pclose perror pipe +poll popen -pow FLOAT -printf FLOAT LDBL +# pow DPML version ??? +pow FLOAT64 FLOATV2 +powf FLOAT32 FLOATV2 +powl FLOAT64 FLOAT128 FLOATV2 +pread +printf FLOAT64 FLOAT128 +printf__cf FLOAT64 FLOAT128 +printw FLOAT64 FLOAT128 putc +putc_unlocked putchar +putchar_unlocked putenv puts -qsort 64 +putw +putwc +putwchar +pwrite +qabs +qdiv +qsort 64 raise +rand +rand_r random read readdir -realloc 64 MALLOC +readdir_r 64 +readlink +readv 64 +realloc 64 MALLOC +realloc_opt +realpath 64 +record_read recv -recvfrom -recvmsg BSD44 64 +recvfrom BSD44 +recvmsg BSD44 +remainder DPML remove rename rewind -rindex 64 +rewinddir +rindex 64 +rint FLOAT64_VAXD DPML +rintl FLOAT64_VAXD rmdir -scanf FLOAT LDBL +rtl_private +# sbrk # Makes libiberty/xmalloc.c fails to build. +scalb FLOAT64_VAXD DPML +scalbl FLOAT64_VAXD +scanf FLOAT64 FLOAT128 +scanw FLOAT64 FLOAT128 +scroll +seed48 +seekdir select send -sendmsg BSD44 64 -sendto +sendmsg BSD44 +sendto BSD44 +set_new_handler__xpxv_v setbuf setenv +seteuid +setgid +setgrent +sethostent +setitimer +setkey setlocale +setnetent +setpgid +setpgrp +setprotoent setpwent +setregid +setreuid +setservent +setsid setsockopt +setstate +setuid setvbuf +shm_open +shm_unlink +shutdown +sigaction +sigaddset +sigblock +sigdelset +sigemptyset +sigfillset +sighold +sigignore +sigismember siglongjmp +sigmask signal +signgam GL +sigpause +sigpending +sigprocmask +sigrelse sigsetjmp sigsetmask -sin FLOAT +sigstack +sigsuspend +sigtimedwait +sigvec +sigwait +sigwaitinfo +sin FLOAT64 DPML +sincos DPML +sincosd DPML +sind FLOAT64_VAXD DPML +sindl FLOAT64_VAXD +sinh FLOAT64 DPML +sinhcosh DPML +sinhl FLOAT64_VAXD +sinl FLOAT64_VAXD sleep -snprintf FLOAT LDBL +snprintf FLOAT64 FLOAT128 socket -sprintf FLOAT LDBL -sqrt FLOAT -sscanf FLOAT LDBL +socketpair +sprintf FLOAT64 FLOAT128 +sprintf__cf FLOAT64 FLOAT128 +sqrt FLOAT64 DPML +sqrtl FLOAT64_VAXD +srand +srand48 +srandom +sscanf FLOAT64 FLOAT128 +ssignal stat +statvfs strcasecmp -strcat 64 -strchr 64 +strcat 64 +strchr 64 strcmp -strcpy 64 +strcoll +strcpy 64 strcspn -strdup 64 MALLOC +strdup 64 MALLOC strerror +strfmon FLOAT64 +strftime strlen strncasecmp -strncat 64 +strncat 64 strncmp -strncpy 64 -strpbrk 64 -strrchr 64 +strncpy 64 +strnlen +strpbrk 64 +strptime 64 +strptime_xpg4 +strrchr 64 +strsep 64 strspn -strstr 64 -strtod 64 FLOAT -strtok 64 MALLOC -strtok_r 64 MALLOC -strtol 64 -strtoul 64 +strstr 64 +strtod FLOAT64 64 +strtok 64 +strtok_r 64 +strtol 64 +strtoll 64 +strtoq 64 +strtoul 64 +strtoull 64 +strtouq 64 +strxfrm +subwin +swab +swprintf FLOAT64 FLOAT128 +swscanf FLOAT64 FLOAT128 +symlink +sys_errlist GA +sys_nerr GL sysconf system -tan FLOAT +tan FLOAT64 DPML +tand FLOAT64_VAXD DPML +tandl FLOAT64_VAXD +tanh FLOAT64 DPML +tanhl FLOAT64_VAXD +tanl FLOAT64_VAXD +telldir tempnam +tgamma DPML time times +timezone GL tmpfile -tmpnam 64 +tmpnam 64 +toascii tolower +touchwin toupper +towctrans +towlower +towupper +trunc FLOAT64_VAXD DPML +truncate +truncl FLOAT64_VAXD ttyname +ttyname_r +tzname GA +tzset +ualarm umask +uname ungetc +ungetwc unlink +unordered FLOAT64_VAXD DPML +unorderedl FLOAT64_VAXD +unsetenv usleep utime -vfprintf FLOAT LDBL -vprintf FLOAT LDBL -vsnprintf FLOAT LDBL -vsprintf FLOAT LDBL +utimes +vaxc$calloc_opt +vaxc$cfree_opt +vaxc$crtl_init +vaxc$errno GA +vaxc$free_opt +vaxc$get_sdc +vaxc$malloc_opt +vaxc$realloc_opt +vfprintf FLOAT64 FLOAT128 +vfscanf FLOAT64 FLOAT128 +vfwprintf FLOAT64 FLOAT128 +vfwscanf FLOAT64 FLOAT128 +vprintf FLOAT64 FLOAT128 +vscanf FLOAT64 FLOAT128 +vsnprintf FLOAT64 FLOAT128 +vsprintf FLOAT64 FLOAT128 +vsscanf FLOAT64 FLOAT128 +vswprintf FLOAT64 FLOAT128 +vswscanf FLOAT64 FLOAT128 +vwprintf FLOAT64 FLOAT128 +vwscanf FLOAT64 FLOAT128 +waddch +waddstr wait +wait3 +wait4 waitpid +wclear +wclrattr +wclrtobot +wclrtoeol +wcrtomb +wcscat 64 +wcschr 64 +wcscmp +wcscoll +wcscpy 64 +wcscspn +wcsftime +wcslen +wcsncat 64 +wcsncmp +wcsncpy 64 +wcspbrk 64 +wcsrchr 64 +wcsrtombs 64 +wcsspn +wcsstr 64 +wcstod FLOAT64 64 +wcstok 64 +wcstol 64 +wcstombs +wcstoul 64 +wcswcs 64 wcswidth +wcsxfrm +wctob +wctomb +wctrans +wctype +wcwidth +wdelch +wdeleteln +werase +wgetch +wgetstr +winch +winsch +winsertln +winsstr +wmemchr 64 +wmemcmp +wmemcpy 64 +wmemmove 64 +wmemset 64 +wmove +wprintf FLOAT64 FLOAT128 +wprintw FLOAT64 FLOAT128 +wrefresh write +writev +wscanf FLOAT64 FLOAT128 +wscanw FLOAT64 FLOAT128 +wsetattr +wstandend +wstandout +y0 FLOAT64_VAXD DPML +y0l FLOAT64_VAXD +y1 FLOAT64_VAXD DPML +y1l FLOAT64_VAXD +yn FLOAT64_VAXD DPML +ynl FLOAT64_VAXD diff --git a/gcc/config/vms/vms-f.c b/gcc/config/vms/vms-f.c new file mode 100644 index 00000000000..3c3ba414380 --- /dev/null +++ b/gcc/config/vms/vms-f.c @@ -0,0 +1,31 @@ +/* VMS support needed only by Fortran frontends. + Copyright (C) 2012 Free Software Foundation, Inc. + +This file is part of GCC. + +GCC is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 3, or (at your option) +any later version. + +GCC is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with GCC; see the file COPYING3. If not see +<http://www.gnu.org/licenses/>. */ + +#include "config.h" +#include "system.h" +#include "coretypes.h" +#include "tm.h" + +void +vms_c_register_includes (const char *sysroot ATTRIBUTE_UNUSED, + const char *iprefix ATTRIBUTE_UNUSED, + int stdinc ATTRIBUTE_UNUSED) +{ + /* No-op for fortran. */ +} diff --git a/gcc/config/vms/vms.c b/gcc/config/vms/vms.c index a85fb3fb209..d4ebd18730b 100644 --- a/gcc/config/vms/vms.c +++ b/gcc/config/vms/vms.c @@ -26,6 +26,8 @@ along with GCC; see the file COPYING3. If not see #include "ggc.h" #include "target.h" #include "output.h" +#include "tm.h" +#include "dwarf2out.h" /* Correlation of standard CRTL names with DECCRTL function names. */ @@ -36,19 +38,46 @@ along with GCC; see the file COPYING3. If not see /* If long pointer are enabled, use _NAME64 instead. */ #define VMS_CRTL_64 (1 << 1) -/* Use tNAME instead. To be applied after the previous rule. */ -#define VMS_CRTL_FLOAT (1 << 2) +/* Prepend s/f before the name. To be applied after the previous rule. + use 's' for S float, 'f' for IEEE 32. */ +#define VMS_CRTL_FLOAT32 (1 << 2) -/* Prepend __bsd44__ before the name. To be applied after the P64 - rule. */ -#define VMS_CRTL_BSD44 (1 << 3) +/* Prepend t/g/d before the name. To be applied after the previous rule. + use 'g' for VAX G float, 'd' for VAX D float, 't' for IEEE 64. */ +#define VMS_CRTL_FLOAT64 (1 << 3) + +/* Prepend d before the name, only if using VAX fp. */ +#define VMS_CRTL_FLOAT64_VAXD (1 << 4) /* Prepend x before the name for if 128 bit long doubles are enabled. This concern mostly 'printf'-like functions. */ -#define VMS_CRTL_LDBL (1 << 4) +#define VMS_CRTL_FLOAT128 (1 << 5) + +/* From xxx, create xxx, xxxf, xxxl using MATH$XXX_T, MATH$XXX_S + and MATH$XXX{_X} if DPML is used. */ +#define VMS_CRTL_DPML (1 << 6) -/* Prepend ga_ for global data. */ -#define VMS_CRTL_GLOBAL (1 << 5) +/* Together with DPML, it means that all variant (ie xxx, xxxf and xxxl) are + overridden by decc. Without DPML, it means this is a variant (ie xxxf + or xxxl) of a function. */ +#define VMS_CRTL_NODPML (1 << 7) + +/* Prepend __bsd44_ before the name. To be applied after the P64 + rule. */ +#define VMS_CRTL_BSD44 (1 << 8) + +/* Define only in 32 bits mode, as this has no 64 bit variants. + Concerns getopt/getarg. */ +#define VMS_CRTL_32ONLY (1 << 9) + +/* GLobal data prefix (ga_, gl_...) */ +#define VMS_CRTL_G_MASK (7 << 10) +#define VMS_CRTL_G_NONE (0 << 10) +#define VMS_CRTL_GA (1 << 10) +#define VMS_CRTL_GL (2 << 10) + +/* Append '_2'. Not compatible with 64. */ +#define VMS_CRTL_FLOATV2 (1 << 13) struct vms_crtl_name { @@ -84,14 +113,14 @@ vms_add_crtl_xlat (const char *name, size_t nlen, { tree targ; + /* printf ("vms crtl: %.*s -> %.*s\n", nlen, name, id_len, id_str); */ + targ = get_identifier_with_length (name, nlen); gcc_assert (!IDENTIFIER_TRANSPARENT_ALIAS (targ)); IDENTIFIER_TRANSPARENT_ALIAS (targ) = 1; TREE_CHAIN (targ) = get_identifier_with_length (id_str, id_len); VEC_safe_push (tree, gc, aliases_id, targ); - - /* printf ("vms: %s (%p) -> %.*s\n", name, targ, id_len, id_str); */ } /* Do VMS specific stuff on builtins: disable the ones that are not @@ -116,7 +145,48 @@ vms_patch_builtins (void) const struct vms_crtl_name *n = &vms_crtl_names[i]; char res[VMS_CRTL_MAXLEN + 3 + 9 + 1 + 1]; int rlen; - int nlen; + int nlen = strlen (n->name); + + /* Discard 32ONLY if using 64 bit pointers. */ + if ((n->flags & VMS_CRTL_32ONLY) + && flag_vms_pointer_size == VMS_POINTER_SIZE_64) + continue; + + /* Handle DPML unless overridden by decc. */ + if ((n->flags & VMS_CRTL_DPML) + && !(n->flags & VMS_CRTL_NODPML)) + { + const char *p; + char alt[VMS_CRTL_MAXLEN + 3]; + + memcpy (res, "MATH$", 5); + rlen = 5; + for (p = n->name; *p; p++) + res[rlen++] = TOUPPER (*p); + res[rlen++] = '_'; + res[rlen++] = 'T'; + + /* Double version. */ + if (!(n->flags & VMS_CRTL_FLOAT64)) + vms_add_crtl_xlat (n->name, nlen, res, rlen); + + /* Float version. */ + res[rlen - 1] = 'S'; + memcpy (alt, n->name, nlen); + alt[nlen] = 'f'; + vms_add_crtl_xlat (alt, nlen + 1, res, rlen); + + /* Long double version. */ + res[rlen - 1] = (LONG_DOUBLE_TYPE_SIZE == 128 ? 'X' : 'T'); + alt[nlen] = 'l'; + vms_add_crtl_xlat (alt, nlen + 1, res, rlen); + + if (!(n->flags & (VMS_CRTL_FLOAT32 | VMS_CRTL_FLOAT64))) + continue; + } + + if (n->flags & VMS_CRTL_FLOAT64_VAXD) + continue; /* Add the dec-c prefix. */ memcpy (res, "decc$", 5); @@ -124,27 +194,49 @@ vms_patch_builtins (void) if (n->flags & VMS_CRTL_BSD44) { - memcpy (res + rlen, "__bsd44__", 9); - rlen += 9; + memcpy (res + rlen, "__bsd44_", 8); + rlen += 8; } - if (n->flags & VMS_CRTL_GLOBAL) + if ((n->flags & VMS_CRTL_G_MASK) != VMS_CRTL_G_NONE) { - memcpy (res + rlen, "ga_", 3); - rlen += 3; + res[rlen++] = 'g'; + switch (n->flags & VMS_CRTL_G_MASK) + { + case VMS_CRTL_GA: + res[rlen++] = 'a'; + break; + case VMS_CRTL_GL: + res[rlen++] = 'l'; + break; + default: + gcc_unreachable (); + } + res[rlen++] = '_'; } - if (n->flags & VMS_CRTL_FLOAT) + if (n->flags & VMS_CRTL_FLOAT32) + res[rlen++] = 'f'; + + if (n->flags & VMS_CRTL_FLOAT64) res[rlen++] = 't'; - if (n->flags & VMS_CRTL_LDBL) + if ((n->flags & VMS_CRTL_FLOAT128) && LONG_DOUBLE_TYPE_SIZE == 128) res[rlen++] = 'x'; - nlen = strlen (n->name); memcpy (res + rlen, n->name, nlen); if ((n->flags & VMS_CRTL_64) == 0) - vms_add_crtl_xlat (n->name, nlen, res, rlen + nlen); + { + rlen += nlen; + + if (n->flags & VMS_CRTL_FLOATV2) + { + res[rlen++] = '_'; + res[rlen++] = '2'; + } + vms_add_crtl_xlat (n->name, nlen, res, rlen); + } else { char alt[VMS_CRTL_MAXLEN + 3]; |