diff options
Diffstat (limited to 'gcc/config')
| -rw-r--r-- | gcc/config/i386/i386.c | 4 | ||||
| -rw-r--r-- | gcc/config/i386/i386.md | 4 | ||||
| -rw-r--r-- | gcc/config/i386/sse.md | 14 |
3 files changed, 9 insertions, 13 deletions
diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c index 640e9c089b3..b1dda95adc7 100644 --- a/gcc/config/i386/i386.c +++ b/gcc/config/i386/i386.c @@ -19476,8 +19476,8 @@ ix86_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED, if (! (*insn_data[icode].operand[1].predicate) (op0, mode1)) op0 = copy_to_reg (op0); - op1 = simplify_gen_subreg (TImode, op1, GET_MODE (op1), 0); - if (! (*insn_data[icode].operand[2].predicate) (op1, TImode)) + op1 = simplify_gen_subreg (SImode, op1, GET_MODE (op1), 0); + if (! (*insn_data[icode].operand[2].predicate) (op1, SImode)) op1 = copy_to_reg (op1); target = gen_reg_rtx (tmode); diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md index 3ddf7dc54fa..5b50274fcb8 100644 --- a/gcc/config/i386/i386.md +++ b/gcc/config/i386/i386.md @@ -4983,8 +4983,8 @@ "TARGET_SSE2 && TARGET_SSE_MATH && (!TARGET_USE_VECTOR_CONVERTS || optimize_size)" "@ - cvtsi2sd\t{%1, %0|%0, %1} - cvtsi2sd\t{%1, %0|%0, %1} + cvtsi2sd\t{%1, %0|%0, %1} + cvtsi2sd\t{%1, %0|%0, %1} cvtdq2pd\t{%1, %0|%0, %1}" [(set_attr "type" "sseicvt") (set_attr "mode" "DF,DF,V2DF") diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md index 03b2577b2ce..65207a403d0 100644 --- a/gcc/config/i386/sse.md +++ b/gcc/config/i386/sse.md @@ -3416,7 +3416,7 @@ [(set (match_operand:SSEMODE24 0 "register_operand" "=x") (ashiftrt:SSEMODE24 (match_operand:SSEMODE24 1 "register_operand" "0") - (match_operand:TI 2 "nonmemory_operand" "xn")))] + (match_operand:SI 2 "nonmemory_operand" "xN")))] "TARGET_SSE2" "psra<ssevecsize>\t{%2, %0|%0, %2}" [(set_attr "type" "sseishft") @@ -3427,7 +3427,7 @@ [(set (match_operand:SSEMODE248 0 "register_operand" "=x") (lshiftrt:SSEMODE248 (match_operand:SSEMODE248 1 "register_operand" "0") - (match_operand:TI 2 "nonmemory_operand" "xn")))] + (match_operand:SI 2 "nonmemory_operand" "xN")))] "TARGET_SSE2" "psrl<ssevecsize>\t{%2, %0|%0, %2}" [(set_attr "type" "sseishft") @@ -3438,7 +3438,7 @@ [(set (match_operand:SSEMODE248 0 "register_operand" "=x") (ashift:SSEMODE248 (match_operand:SSEMODE248 1 "register_operand" "0") - (match_operand:TI 2 "nonmemory_operand" "xn")))] + (match_operand:SI 2 "nonmemory_operand" "xN")))] "TARGET_SSE2" "psll<ssevecsize>\t{%2, %0|%0, %2}" [(set_attr "type" "sseishft") @@ -3448,11 +3448,9 @@ (define_expand "vec_shl_<mode>" [(set (match_operand:SSEMODEI 0 "register_operand" "") (ashift:TI (match_operand:SSEMODEI 1 "register_operand" "") - (match_operand:SI 2 "general_operand" "")))] + (match_operand:SI 2 "const_0_to_255_mul_8_operand" "")))] "TARGET_SSE2" { - if (!const_0_to_255_mul_8_operand (operands[2], SImode)) - FAIL; operands[0] = gen_lowpart (TImode, operands[0]); operands[1] = gen_lowpart (TImode, operands[1]); }) @@ -3460,11 +3458,9 @@ (define_expand "vec_shr_<mode>" [(set (match_operand:SSEMODEI 0 "register_operand" "") (lshiftrt:TI (match_operand:SSEMODEI 1 "register_operand" "") - (match_operand:SI 2 "general_operand" "")))] + (match_operand:SI 2 "const_0_to_255_mul_8_operand" "")))] "TARGET_SSE2" { - if (!const_0_to_255_mul_8_operand (operands[2], SImode)) - FAIL; operands[0] = gen_lowpart (TImode, operands[0]); operands[1] = gen_lowpart (TImode, operands[1]); }) |