diff options
Diffstat (limited to 'gcc/config')
| -rw-r--r-- | gcc/config/mips/mips.c | 18 | ||||
| -rw-r--r-- | gcc/config/mips/mips.h | 29 |
2 files changed, 9 insertions, 38 deletions
diff --git a/gcc/config/mips/mips.c b/gcc/config/mips/mips.c index ef9a8c068ca..a7adf170cbc 100644 --- a/gcc/config/mips/mips.c +++ b/gcc/config/mips/mips.c @@ -10164,17 +10164,17 @@ int mips_register_move_cost (enum machine_mode mode ATTRIBUTE_UNUSED, enum reg_class to, enum reg_class from) { - if (from == M16_REGS && GR_REG_CLASS_P (to)) + if (from == M16_REGS && reg_class_subset_p (to, GENERAL_REGS)) return 2; - else if (from == M16_NA_REGS && GR_REG_CLASS_P (to)) + else if (from == M16_NA_REGS && reg_class_subset_p (to, GENERAL_REGS)) return 2; - else if (GR_REG_CLASS_P (from)) + else if (reg_class_subset_p (from, GENERAL_REGS)) { if (to == M16_REGS) return 2; else if (to == M16_NA_REGS) return 2; - else if (GR_REG_CLASS_P (to)) + else if (reg_class_subset_p (to, GENERAL_REGS)) { if (TARGET_MIPS16) return 4; @@ -10190,14 +10190,14 @@ mips_register_move_cost (enum machine_mode mode ATTRIBUTE_UNUSED, else return 6; } - else if (COP_REG_CLASS_P (to)) + else if (reg_class_subset_p (to, ALL_COP_REGS)) { return 5; } } else if (from == FP_REGS) { - if (GR_REG_CLASS_P (to)) + if (reg_class_subset_p (to, GENERAL_REGS)) return 4; else if (to == FP_REGS) return 2; @@ -10206,7 +10206,7 @@ mips_register_move_cost (enum machine_mode mode ATTRIBUTE_UNUSED, } else if (reg_class_subset_p (from, ACC_REGS)) { - if (GR_REG_CLASS_P (to)) + if (reg_class_subset_p (to, GENERAL_REGS)) { if (TARGET_MIPS16) return 12; @@ -10214,9 +10214,9 @@ mips_register_move_cost (enum machine_mode mode ATTRIBUTE_UNUSED, return 6; } } - else if (from == ST_REGS && GR_REG_CLASS_P (to)) + else if (from == ST_REGS && reg_class_subset_p (to, GENERAL_REGS)) return 4; - else if (COP_REG_CLASS_P (from)) + else if (reg_class_subset_p (from, ALL_COP_REGS)) { return 5; } diff --git a/gcc/config/mips/mips.h b/gcc/config/mips/mips.h index 46fa592ed8c..dbc947d4b6b 100644 --- a/gcc/config/mips/mips.h +++ b/gcc/config/mips/mips.h @@ -1688,17 +1688,6 @@ extern const enum reg_class mips_regno_to_class[]; #define SMALL_REGISTER_CLASSES (TARGET_MIPS16) -/* This macro is used later on in the file. */ -#define GR_REG_CLASS_P(CLASS) \ - ((CLASS) == GR_REGS || (CLASS) == M16_REGS || (CLASS) == T_REG \ - || (CLASS) == M16_T_REGS || (CLASS) == M16_NA_REGS \ - || (CLASS) == V1_REG \ - || (CLASS) == PIC_FN_ADDR_REG || (CLASS) == LEA_REGS) - -/* This macro is also used later on in the file. */ -#define COP_REG_CLASS_P(CLASS) \ - ((CLASS) == COP0_REGS || (CLASS) == COP2_REGS || (CLASS) == COP3_REGS) - /* REG_ALLOC_ORDER is to order in which to allocate registers. This is the default value (allocate the registers in numeric order). We define it just so that we can override it for the mips16 target in @@ -1768,24 +1757,6 @@ extern const enum reg_class mips_regno_to_class[]; #define PREFERRED_RELOAD_CLASS(X,CLASS) \ mips_preferred_reload_class (X, CLASS) -/* Certain machines have the property that some registers cannot be - copied to some other registers without using memory. Define this - macro on those machines to be a C expression that is nonzero if - objects of mode MODE in registers of CLASS1 can only be copied to - registers of class CLASS2 by storing a register of CLASS1 into - memory and loading that memory location into a register of CLASS2. - - Do not define this macro if its value would always be zero. */ -#if 0 -#define SECONDARY_MEMORY_NEEDED(CLASS1, CLASS2, MODE) \ - ((!TARGET_DEBUG_H_MODE \ - && GET_MODE_CLASS (MODE) == MODE_INT \ - && ((CLASS1 == FP_REGS && GR_REG_CLASS_P (CLASS2)) \ - || (GR_REG_CLASS_P (CLASS1) && CLASS2 == FP_REGS))) \ - || (TARGET_FLOAT64 && !TARGET_64BIT && (MODE) == DFmode \ - && ((GR_REG_CLASS_P (CLASS1) && CLASS2 == FP_REGS) \ - || (GR_REG_CLASS_P (CLASS2) && CLASS1 == FP_REGS)))) -#endif /* The HI and LO registers can only be reloaded via the general registers. Condition code registers can only be loaded to the general registers, and from the floating point registers. */ |