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-rw-r--r--gcc/config/i386/i386.c10
-rw-r--r--gcc/config/ia64/ia64.c41
-rw-r--r--gcc/config/rs6000/rs6000.c17
3 files changed, 32 insertions, 36 deletions
diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c
index 415e31b5606..24c6f82c4b2 100644
--- a/gcc/config/i386/i386.c
+++ b/gcc/config/i386/i386.c
@@ -26383,7 +26383,7 @@ static int min_insn_size (rtx);
static void
core2i7_first_cycle_multipass_filter_ready_try
(const_ix86_first_cycle_multipass_data_t data,
- char *ready_try, int n_ready, bool first_cycle_insn_p)
+ signed char *ready_try, int n_ready, bool first_cycle_insn_p)
{
while (n_ready--)
{
@@ -26415,7 +26415,8 @@ core2i7_first_cycle_multipass_filter_ready_try
/* Prepare for a new round of multipass lookahead scheduling. */
static void
-core2i7_first_cycle_multipass_begin (void *_data, char *ready_try, int n_ready,
+core2i7_first_cycle_multipass_begin (void *_data,
+ signed char *ready_try, int n_ready,
bool first_cycle_insn_p)
{
ix86_first_cycle_multipass_data_t data
@@ -26436,7 +26437,8 @@ core2i7_first_cycle_multipass_begin (void *_data, char *ready_try, int n_ready,
/* INSN is being issued in current solution. Account for its impact on
the decoder model. */
static void
-core2i7_first_cycle_multipass_issue (void *_data, char *ready_try, int n_ready,
+core2i7_first_cycle_multipass_issue (void *_data,
+ signed char *ready_try, int n_ready,
rtx insn, const void *_prev_data)
{
ix86_first_cycle_multipass_data_t data
@@ -26474,7 +26476,7 @@ core2i7_first_cycle_multipass_issue (void *_data, char *ready_try, int n_ready,
/* Revert the effect on ready_try. */
static void
core2i7_first_cycle_multipass_backtrack (const void *_data,
- char *ready_try,
+ signed char *ready_try,
int n_ready ATTRIBUTE_UNUSED)
{
const_ix86_first_cycle_multipass_data_t data
diff --git a/gcc/config/ia64/ia64.c b/gcc/config/ia64/ia64.c
index 7118146998a..d6e4cf4961f 100644
--- a/gcc/config/ia64/ia64.c
+++ b/gcc/config/ia64/ia64.c
@@ -169,8 +169,7 @@ static int ia64_first_cycle_multipass_dfa_lookahead (void);
static void ia64_dependencies_evaluation_hook (rtx, rtx);
static void ia64_init_dfa_pre_cycle_insn (void);
static rtx ia64_dfa_pre_cycle_insn (void);
-static int ia64_first_cycle_multipass_dfa_lookahead_guard (rtx);
-static bool ia64_first_cycle_multipass_dfa_lookahead_guard_spec (const_rtx);
+static int ia64_first_cycle_multipass_dfa_lookahead_guard (rtx, int);
static int ia64_dfa_new_cycle (FILE *, int, rtx, int, int, int *);
static void ia64_h_i_d_extended (void);
static void * ia64_alloc_sched_context (void);
@@ -496,10 +495,6 @@ static const struct attribute_spec ia64_attribute_table[] =
#undef TARGET_SCHED_GEN_SPEC_CHECK
#define TARGET_SCHED_GEN_SPEC_CHECK ia64_gen_spec_check
-#undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD_GUARD_SPEC
-#define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD_GUARD_SPEC\
- ia64_first_cycle_multipass_dfa_lookahead_guard_spec
-
#undef TARGET_SCHED_SKIP_RTX_P
#define TARGET_SCHED_SKIP_RTX_P ia64_skip_rtx_p
@@ -7531,32 +7526,28 @@ ia64_variable_issue (FILE *dump ATTRIBUTE_UNUSED,
return 1;
}
-/* We are choosing insn from the ready queue. Return nonzero if INSN
+/* We are choosing insn from the ready queue. Return zero if INSN
can be chosen. */
static int
-ia64_first_cycle_multipass_dfa_lookahead_guard (rtx insn)
+ia64_first_cycle_multipass_dfa_lookahead_guard (rtx insn, int ready_index)
{
gcc_assert (insn && INSN_P (insn));
- return ((!reload_completed
- || !safe_group_barrier_needed (insn))
- && ia64_first_cycle_multipass_dfa_lookahead_guard_spec (insn)
- && (!mflag_sched_mem_insns_hard_limit
- || !is_load_p (insn)
- || mem_ops_in_group[current_cycle % 4] < ia64_max_memory_insns));
-}
-/* We are choosing insn from the ready queue. Return nonzero if INSN
- can be chosen. */
+ /* Size of ALAT is 32. As far as we perform conservative
+ data speculation, we keep ALAT half-empty. */
+ if ((TODO_SPEC (insn) & BEGIN_DATA) && pending_data_specs >= 16)
+ return ready_index == 0 ? -1 : 1;
-static bool
-ia64_first_cycle_multipass_dfa_lookahead_guard_spec (const_rtx insn)
-{
- gcc_assert (insn && INSN_P (insn));
- /* Size of ALAT is 32. As far as we perform conservative data speculation,
- we keep ALAT half-empty. */
- return (pending_data_specs < 16
- || !(TODO_SPEC (insn) & BEGIN_DATA));
+ if (ready_index == 0)
+ return 0;
+
+ if ((!reload_completed
+ || !safe_group_barrier_needed (insn))
+ && (!mflag_sched_mem_insns_hard_limit
+ || !is_load_p (insn)
+ || mem_ops_in_group[current_cycle % 4] < ia64_max_memory_insns))
+ return 0;
}
/* The following variable value is pseudo-insn used by the DFA insn
diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c
index cd7b8c1f49d..f58ccd0936c 100644
--- a/gcc/config/rs6000/rs6000.c
+++ b/gcc/config/rs6000/rs6000.c
@@ -26796,22 +26796,25 @@ rs6000_use_sched_lookahead (void)
}
}
-/* We are choosing insn from the ready queue. Return nonzero if INSN can be chosen. */
+/* We are choosing insn from the ready queue. Return zero if INSN can be
+ chosen. */
static int
-rs6000_use_sched_lookahead_guard (rtx insn)
+rs6000_use_sched_lookahead_guard (rtx insn, int ready_index)
{
+ if (ready_index == 0)
+ return 0;
+
if (rs6000_cpu_attr != CPU_CELL)
- return 1;
+ return 0;
- if (insn == NULL_RTX || !INSN_P (insn))
- abort ();
+ gcc_assert (insn != NULL_RTX && INSN_P (insn));
if (!reload_completed
|| is_nonpipeline_insn (insn)
|| is_microcoded_insn (insn))
- return 0;
+ return 1;
- return 1;
+ return 0;
}
/* Determine if PAT refers to memory. If so, set MEM_REF to the MEM rtx
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