diff options
Diffstat (limited to 'gcc/config')
29 files changed, 319 insertions, 266 deletions
diff --git a/gcc/config/a29k/a29k.c b/gcc/config/a29k/a29k.c index c6d7ba28e4a..65c6240a3bc 100644 --- a/gcc/config/a29k/a29k.c +++ b/gcc/config/a29k/a29k.c @@ -262,9 +262,10 @@ gpc_reg_operand (op, mode) regno = REGNO (op); else if (GET_CODE (op) == SUBREG && GET_CODE (SUBREG_REG (op)) == REG) { - regno = REGNO (SUBREG_REG (op)); - if (regno < FIRST_PSEUDO_REGISTER) - regno += SUBREG_WORD (op); + if (REGNO (SUBREG_REG (op)) < FIRST_PSEUDO_REGISTER) + regno = subreg_regno (op); + else + regno = REGNO (SUBREG_REG (op)); } else return 0; @@ -467,7 +468,7 @@ a29k_get_reloaded_address (op) { if (GET_CODE (op) == SUBREG) { - if (SUBREG_WORD (op) != 0) + if (SUBREG_BYTE (op) != 0) abort (); op = SUBREG_REG (op); @@ -1187,7 +1188,8 @@ print_operand (file, x, code) if (GET_MODE (SUBREG_REG (XEXP (x, 0))) == SFmode) fprintf (file, "$float"); else - fprintf (file, "$double%d", SUBREG_WORD (XEXP (x, 0))); + fprintf (file, "$double%d", + (SUBREG_BYTE (XEXP (x, 0)) / GET_MODE_SIZE (GET_MODE (x)))); memcpy ((char *) &u, (char *) &CONST_DOUBLE_LOW (SUBREG_REG (XEXP (x, 0))), sizeof u); fprintf (file, "(%.20e)", u.d); diff --git a/gcc/config/alpha/alpha.c b/gcc/config/alpha/alpha.c index 18a61d6c7f6..c6aa2eec7fa 100644 --- a/gcc/config/alpha/alpha.c +++ b/gcc/config/alpha/alpha.c @@ -4098,7 +4098,8 @@ print_operand_address (file, addr) basereg = REGNO (addr); else if (GET_CODE (addr) == SUBREG && GET_CODE (SUBREG_REG (addr)) == REG) - basereg = REGNO (SUBREG_REG (addr)) + SUBREG_WORD (addr); + basereg = REGNO (SUBREG_REG (addr)) + + SUBREG_BYTE (addr) / GET_MODE_SIZE (GET_MODE (addr)); else if (GET_CODE (addr) == CONST_INT) offset = INTVAL (addr); else diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c index 0f0c5e9d9a3..b89392efad2 100644 --- a/gcc/config/arm/arm.c +++ b/gcc/config/arm/arm.c @@ -4748,11 +4748,7 @@ arm_reload_in_hi (operands) if (GET_CODE (ref) == SUBREG) { - offset = SUBREG_WORD (ref) * UNITS_PER_WORD; - if (BYTES_BIG_ENDIAN) - offset -= (MIN (UNITS_PER_WORD, GET_MODE_SIZE (GET_MODE (ref))) - - MIN (UNITS_PER_WORD, - GET_MODE_SIZE (GET_MODE (SUBREG_REG (ref))))); + offset = SUBREG_BYTE (ref); ref = SUBREG_REG (ref); } @@ -4865,11 +4861,7 @@ arm_reload_out_hi (operands) if (GET_CODE (ref) == SUBREG) { - offset = SUBREG_WORD (ref) * UNITS_PER_WORD; - if (BYTES_BIG_ENDIAN) - offset -= (MIN (UNITS_PER_WORD, GET_MODE_SIZE (GET_MODE (ref))) - - MIN (UNITS_PER_WORD, - GET_MODE_SIZE (GET_MODE (SUBREG_REG (ref))))); + offset = SUBREG_BYTE (ref); ref = SUBREG_REG (ref); } diff --git a/gcc/config/d30v/d30v.c b/gcc/config/d30v/d30v.c index a4f5e8d8473..b8f30aa7c5f 100644 --- a/gcc/config/d30v/d30v.c +++ b/gcc/config/d30v/d30v.c @@ -2667,10 +2667,13 @@ d30v_split_double (value, p_high, p_low) switch (GET_CODE (value)) { case SUBREG: - offset = SUBREG_WORD (value); - value = SUBREG_REG (value); - if (GET_CODE (value) != REG) + if (GET_CODE (SUBREG_REG (value)) != REG) abort (); + offset = subreg_regno_offset (REGNO (SUBREG_REG (value)), + GET_MODE (SUBREG_REG (value)), + SUBREG_BYTE (value), + GET_MODE (value)); + value = SUBREG_REG (value); /* fall through */ @@ -2795,7 +2798,10 @@ d30v_print_operand_memory_reference (stream, x) if (GET_CODE (x0) == SUBREG) { - offset0 = SUBREG_WORD (x0); + offset0 = subreg_regno_offset (REGNO (SUBREG_REG (x0)), + GET_MODE (SUBREG_REG (x0)), + SUBREG_BYTE (x0), + GET_MODE (x0)); x0 = SUBREG_REG (x0); } @@ -2828,7 +2834,10 @@ d30v_print_operand_memory_reference (stream, x) switch (GET_CODE (x1)) { case SUBREG: - offset1 = SUBREG_WORD (x1); + offset1 = subreg_regno_offset (REGNO (SUBREG_REG (x1)), + GET_MODE (SUBREG_REG (x1)), + SUBREG_BYTE (x1), + GET_MODE (x1)); x1 = SUBREG_REG (x1); if (GET_CODE (x1) != REG) fatal_insn ("Bad insn to d30v_print_operand_memory_reference:", x); diff --git a/gcc/config/dsp16xx/dsp16xx.md b/gcc/config/dsp16xx/dsp16xx.md index ce7fb96b850..4c65a89bfbe 100644 --- a/gcc/config/dsp16xx/dsp16xx.md +++ b/gcc/config/dsp16xx/dsp16xx.md @@ -1258,7 +1258,7 @@ " { operands[2] = gen_reg_rtx (HImode); - operands[3] = gen_rtx_SUBREG (QImode, operands[2], 1); + operands[3] = gen_rtx_SUBREG (QImode, operands[2], GET_MODE_SIZE (QImode)); }") ;;(define_insn "extendqihi2" @@ -1308,7 +1308,7 @@ " { operands[2] = gen_reg_rtx (HImode); - operands[3] = gen_rtx_SUBREG (QImode, operands[2], 1); + operands[3] = gen_rtx_SUBREG (QImode, operands[2], GET_MODE_SIZE (QImode)); }") diff --git a/gcc/config/h8300/h8300.md b/gcc/config/h8300/h8300.md index 2ea2463f91b..d79750aeb23 100644 --- a/gcc/config/h8300/h8300.md +++ b/gcc/config/h8300/h8300.md @@ -1925,7 +1925,7 @@ (subreg:HI (zero_extract:SI (match_operand:HI 1 "register_operand" "r") (const_int 1) - (match_operand:HI 2 "immediate_operand" "n")) 1))] + (match_operand:HI 2 "immediate_operand" "n")) 2))] "" "sub.w %0,%0\;bld %Z2,%Y1\;bst #0,%X0" [(set_attr "cc" "clobber") @@ -1966,7 +1966,7 @@ (subreg:HI (lshiftrt:SI (match_operand:SI 1 "register_operand" "Ur") - (match_operand:SI 2 "const_int_operand" "n")) 1)) + (match_operand:SI 2 "const_int_operand" "n")) 2)) (const_int 1)))] "INTVAL (operands[2]) < 16" "sub.w %0,%0\;bild %Z2,%Y1\;bst #0,%X0" diff --git a/gcc/config/i370/i370.md b/gcc/config/i370/i370.md index 614e3d6fb6b..5de8931d21b 100644 --- a/gcc/config/i370/i370.md +++ b/gcc/config/i370/i370.md @@ -537,12 +537,12 @@ check_label_emit (); emit_insn (gen_rtx_CLOBBER (VOIDmode, reg1)); emit_move_insn (gen_rtx_SUBREG (SImode, reg1, 0), force_operand (XEXP (mem1, 0), NULL_RTX)); - emit_move_insn (gen_rtx_SUBREG (SImode, reg1, 1), len); + emit_move_insn (gen_rtx_SUBREG (SImode, reg1, GET_MODE_SIZE (SImode)), len); emit_insn (gen_rtx_CLOBBER (VOIDmode, reg2)); emit_move_insn (gen_rtx_SUBREG (SImode, reg2, 0), force_operand (XEXP (mem2, 0), NULL_RTX)); - emit_move_insn (gen_rtx_SUBREG (SImode, reg2, 1), len); + emit_move_insn (gen_rtx_SUBREG (SImode, reg2, GET_MODE_SIZE (SImode)), len); /* Compare! */ emit_insn (gen_cmpstrsi_1 (result, reg1, reg2)); @@ -1409,11 +1409,11 @@ check_label_emit (); emit_insn (gen_rtx_CLOBBER (VOIDmode, reg1)); emit_move_insn (gen_rtx_SUBREG (SImode, reg1, 0), force_operand (XEXP (mem1, 0), NULL_RTX)); - emit_move_insn (gen_rtx_SUBREG (SImode, reg1, 1), len); + emit_move_insn (gen_rtx_SUBREG (SImode, reg1, GET_MODE_SIZE (SImode)), len); emit_insn (gen_rtx_CLOBBER (VOIDmode, reg2)); emit_move_insn (gen_rtx_SUBREG (SImode, reg2, 0), zippo); - emit_move_insn (gen_rtx_SUBREG (SImode, reg2, 1), zippo); + emit_move_insn (gen_rtx_SUBREG (SImode, reg2, GET_MODE_SIZE (SImode)), zippo); /* Copy! */ emit_insn (gen_movstrsi_1 (reg1, reg2)); @@ -1476,12 +1476,12 @@ check_label_emit (); emit_insn (gen_rtx_CLOBBER (VOIDmode, reg1)); emit_move_insn (gen_rtx_SUBREG (SImode, reg1, 0), force_operand (XEXP (mem1, 0), NULL_RTX)); - emit_move_insn (gen_rtx_SUBREG (SImode, reg1, 1), len); + emit_move_insn (gen_rtx_SUBREG (SImode, reg1, GET_MODE_SIZE (SImode)), len); emit_insn (gen_rtx_CLOBBER (VOIDmode, reg2)); emit_move_insn (gen_rtx_SUBREG (SImode, reg2, 0), force_operand (XEXP (mem2, 0), NULL_RTX)); - emit_move_insn (gen_rtx_SUBREG (SImode, reg2, 1), len); + emit_move_insn (gen_rtx_SUBREG (SImode, reg2, GET_MODE_SIZE (SImode)), len); /* Copy! */ emit_insn (gen_movstrsi_1 (reg1, reg2)); @@ -2425,11 +2425,12 @@ check_label_emit (); * Dunno how to untwist it elegantly; but it seems to work for now. */ emit_insn (gen_rtx_SET (VOIDmode, - gen_rtx_SUBREG (SImode, r, 1), operands[1])); + gen_rtx_SUBREG (SImode, r, GET_MODE_SIZE (SImode)), + operands[1])); emit_insn (gen_rtx_SET (VOIDmode, r, gen_rtx_MULT (DImode, r, operands[2]))); emit_insn (gen_rtx_SET (VOIDmode, operands[0], - gen_rtx_SUBREG (SImode, r, 1))); + gen_rtx_SUBREG (SImode, r, GET_MODE_SIZE (SImode)))); } DONE; }") @@ -2534,7 +2535,7 @@ check_label_emit (); emit_insn (gen_rtx_SET (VOIDmode, r, gen_rtx_DIV (DImode, r, operands[2]))); emit_insn (gen_rtx_SET (VOIDmode, operands[0], - gen_rtx_SUBREG (SImode, r, 1))); + gen_rtx_SUBREG (SImode, r, GET_MODE_SIZE (SImode)))); DONE; }") @@ -2552,7 +2553,7 @@ check_label_emit (); { rtx dr = gen_reg_rtx (DImode); rtx dr_0 = gen_rtx_SUBREG (SImode, dr, 0); - rtx dr_1 = gen_rtx_SUBREG (SImode, dr, 1); + rtx dr_1 = gen_rtx_SUBREG (SImode, dr, GET_MODE_SIZE (SImode)); if (GET_CODE (operands[2]) == CONST_INT) diff --git a/gcc/config/i860/i860.c b/gcc/config/i860/i860.c index 7cc9d51e22e..4789f70fe00 100644 --- a/gcc/config/i860/i860.c +++ b/gcc/config/i860/i860.c @@ -340,7 +340,7 @@ single_insn_src_p (op, mode) return 1; case SUBREG: - if (SUBREG_WORD (op) != 0) + if (SUBREG_BYTE (op) != 0) return 0; return single_insn_src_p (SUBREG_REG (op), mode); diff --git a/gcc/config/i860/i860.md b/gcc/config/i860/i860.md index 8cc1fd883f7..5778964f5be 100644 --- a/gcc/config/i860/i860.md +++ b/gcc/config/i860/i860.md @@ -1730,12 +1730,12 @@ }") (define_expand "mulsi3_big" - [(set (subreg:SI (match_dup 4) 1) (match_operand:SI 1 "general_operand" "")) - (set (subreg:SI (match_dup 5) 1) (match_operand:SI 2 "general_operand" "")) + [(set (subreg:SI (match_dup 4) 4) (match_operand:SI 1 "general_operand" "")) + (set (subreg:SI (match_dup 5) 4) (match_operand:SI 2 "general_operand" "")) (clobber (match_dup 3)) - (set (subreg:SI (match_dup 3) 1) - (mult:SI (subreg:SI (match_dup 4) 1) (subreg:SI (match_dup 5) 1))) - (set (match_operand:SI 0 "register_operand" "") (subreg:SI (match_dup 3) 1))] + (set (subreg:SI (match_dup 3) 4) + (mult:SI (subreg:SI (match_dup 4) 4) (subreg:SI (match_dup 5) 4))) + (set (match_operand:SI 0 "register_operand" "") (subreg:SI (match_dup 3) 4))] "WORDS_BIG_ENDIAN" " { @@ -1752,9 +1752,9 @@ "fmlow.dd %2,%1,%0") (define_insn "" - [(set (subreg:SI (match_operand:DI 0 "register_operand" "=f") 1) - (mult:SI (subreg:SI (match_operand:DI 1 "register_operand" "f") 1) - (subreg:SI (match_operand:DI 2 "register_operand" "f") 1)))] + [(set (subreg:SI (match_operand:DI 0 "register_operand" "=f") 4) + (mult:SI (subreg:SI (match_operand:DI 1 "register_operand" "f") 4) + (subreg:SI (match_operand:DI 2 "register_operand" "f") 4)))] "WORDS_BIG_ENDIAN" "fmlow.dd %2,%1,%0") diff --git a/gcc/config/i960/i960.md b/gcc/config/i960/i960.md index b7680e10361..424fb87056e 100644 --- a/gcc/config/i960/i960.md +++ b/gcc/config/i960/i960.md @@ -1211,15 +1211,17 @@ { rtx temp = gen_reg_rtx (SImode); rtx shift_16 = GEN_INT (16); - int op1_subreg_word = 0; + int op1_subreg_byte = 0; if (GET_CODE (operand1) == SUBREG) { - op1_subreg_word = SUBREG_WORD (operand1); + op1_subreg_byte = SUBREG_BYTE (operand1); + op1_subreg_byte /= GET_MODE_SIZE (SImode); + op1_subreg_byte *= GET_MODE_SIZE (SImode); operand1 = SUBREG_REG (operand1); } if (GET_MODE (operand1) != SImode) - operand1 = gen_rtx (SUBREG, SImode, operand1, op1_subreg_word); + operand1 = gen_rtx (SUBREG, SImode, operand1, op1_subreg_byte); emit_insn (gen_ashlsi3 (temp, operand1, shift_16)); emit_insn (gen_ashrsi3 (operand0, temp, shift_16)); @@ -1246,15 +1248,17 @@ { rtx temp = gen_reg_rtx (SImode); rtx shift_24 = GEN_INT (24); - int op1_subreg_word = 0; + int op1_subreg_byte = 0; if (GET_CODE (operand1) == SUBREG) { - op1_subreg_word = SUBREG_WORD (operand1); + op1_subreg_byte = SUBREG_BYTE (operand1); + op1_subreg_byte /= GET_MODE_SIZE (SImode); + op1_subreg_byte *= GET_MODE_SIZE (SImode); operand1 = SUBREG_REG (operand1); } if (GET_MODE (operand1) != SImode) - operand1 = gen_rtx (SUBREG, SImode, operand1, op1_subreg_word); + operand1 = gen_rtx (SUBREG, SImode, operand1, op1_subreg_byte); emit_insn (gen_ashlsi3 (temp, operand1, shift_24)); emit_insn (gen_ashrsi3 (operand0, temp, shift_24)); @@ -1282,24 +1286,28 @@ { rtx temp = gen_reg_rtx (SImode); rtx shift_24 = GEN_INT (24); - int op0_subreg_word = 0; - int op1_subreg_word = 0; + int op0_subreg_byte = 0; + int op1_subreg_byte = 0; if (GET_CODE (operand1) == SUBREG) { - op1_subreg_word = SUBREG_WORD (operand1); + op1_subreg_byte = SUBREG_BYTE (operand1); + op1_subreg_byte /= GET_MODE_SIZE (SImode); + op1_subreg_byte *= GET_MODE_SIZE (SImode); operand1 = SUBREG_REG (operand1); } if (GET_MODE (operand1) != SImode) - operand1 = gen_rtx (SUBREG, SImode, operand1, op1_subreg_word); + operand1 = gen_rtx (SUBREG, SImode, operand1, op1_subreg_byte); if (GET_CODE (operand0) == SUBREG) { - op0_subreg_word = SUBREG_WORD (operand0); + op0_subreg_byte = SUBREG_BYTE (operand0); + op0_subreg_byte /= GET_MODE_SIZE (SImode); + op0_subreg_byte *= GET_MODE_SIZE (SImode); operand0 = SUBREG_REG (operand0); } if (GET_MODE (operand0) != SImode) - operand0 = gen_rtx_SUBREG (SImode, operand0, op0_subreg_word); + operand0 = gen_rtx_SUBREG (SImode, operand0, op0_subreg_byte); emit_insn (gen_ashlsi3 (temp, operand1, shift_24)); emit_insn (gen_ashrsi3 (operand0, temp, shift_24)); @@ -1327,15 +1335,17 @@ { rtx temp = gen_reg_rtx (SImode); rtx shift_16 = GEN_INT (16); - int op1_subreg_word = 0; + int op1_subreg_byte = 0; if (GET_CODE (operand1) == SUBREG) { - op1_subreg_word = SUBREG_WORD (operand1); + op1_subreg_byte = SUBREG_BYTE (operand1); + op1_subreg_byte /= GET_MODE_SIZE (SImode); + op1_subreg_byte *= GET_MODE_SIZE (SImode); operand1 = SUBREG_REG (operand1); } if (GET_MODE (operand1) != SImode) - operand1 = gen_rtx (SUBREG, SImode, operand1, op1_subreg_word); + operand1 = gen_rtx (SUBREG, SImode, operand1, op1_subreg_byte); emit_insn (gen_ashlsi3 (temp, operand1, shift_16)); emit_insn (gen_lshrsi3 (operand0, temp, shift_16)); @@ -1367,15 +1377,17 @@ { rtx temp = gen_reg_rtx (SImode); rtx shift_24 = GEN_INT (24); - int op1_subreg_word = 0; + int op1_subreg_byte = 0; if (GET_CODE (operand1) == SUBREG) { - op1_subreg_word = SUBREG_WORD (operand1); - operand1 = SUBREG_REG (operand1); + op1_subreg_byte = SUBREG_BYTE (operand1); + op1_subreg_byte /= GET_MODE_SIZE (SImode); + op1_subreg_byte *= GET_MODE_SIZE (SImode); + operand1 = SUBREG_REG (operand1); } if (GET_MODE (operand1) != SImode) - operand1 = gen_rtx (SUBREG, SImode, operand1, op1_subreg_word); + operand1 = gen_rtx (SUBREG, SImode, operand1, op1_subreg_byte); emit_insn (gen_ashlsi3 (temp, operand1, shift_24)); emit_insn (gen_lshrsi3 (operand0, temp, shift_24)); @@ -1403,24 +1415,24 @@ { rtx temp = gen_reg_rtx (SImode); rtx shift_24 = GEN_INT (24); - int op0_subreg_word = 0; - int op1_subreg_word = 0; + int op0_subreg_byte = 0; + int op1_subreg_byte = 0; if (GET_CODE (operand1) == SUBREG) { - op1_subreg_word = SUBREG_WORD (operand1); + op1_subreg_byte = SUBREG_BYTE (operand1); operand1 = SUBREG_REG (operand1); } if (GET_MODE (operand1) != SImode) - operand1 = gen_rtx (SUBREG, SImode, operand1, op1_subreg_word); + operand1 = gen_rtx (SUBREG, SImode, operand1, op1_subreg_byte); if (GET_CODE (operand0) == SUBREG) { - op0_subreg_word = SUBREG_WORD (operand0); + op0_subreg_byte = SUBREG_BYTE (operand0); operand0 = SUBREG_REG (operand0); } if (GET_MODE (operand0) != SImode) - operand0 = gen_rtx_SUBREG (SImode, operand0, op0_subreg_word); + operand0 = gen_rtx_SUBREG (SImode, operand0, op0_subreg_byte); emit_insn (gen_ashlsi3 (temp, operand1, shift_24)); emit_insn (gen_lshrsi3 (operand0, temp, shift_24)); diff --git a/gcc/config/m68hc11/m68hc11.c b/gcc/config/m68hc11/m68hc11.c index b1cf541b4c2..0075c39abc6 100644 --- a/gcc/config/m68hc11/m68hc11.c +++ b/gcc/config/m68hc11/m68hc11.c @@ -1739,12 +1739,12 @@ m68hc11_gen_lowpart (mode, x) return gen_rtx (REG, mode, HARD_B_REGNUM); /* gen_lowpart crashes when it is called with a SUBREG. */ - if (GET_CODE (x) == SUBREG && SUBREG_WORD (x) != 0) + if (GET_CODE (x) == SUBREG && SUBREG_BYTE (x) != 0) { if (mode == SImode) - return gen_rtx_SUBREG (mode, SUBREG_REG (x), SUBREG_WORD (x) + 2); + return gen_rtx_SUBREG (mode, SUBREG_REG (x), SUBREG_BYTE (x) + 2); else if (mode == HImode) - return gen_rtx_SUBREG (mode, SUBREG_REG (x), SUBREG_WORD (x) + 1); + return gen_rtx_SUBREG (mode, SUBREG_REG (x), SUBREG_BYTE (x) + 1); else abort (); } @@ -1844,7 +1844,7 @@ m68hc11_gen_highpart (mode, x) } /* gen_highpart crashes when it is called with a SUBREG. */ - if (GET_CODE (x) == SUBREG && SUBREG_WORD (x) != 0) + if (GET_CODE (x) == SUBREG && SUBREG_BYTE (x) != 0) { return gen_rtx (SUBREG, mode, XEXP (x, 0), XEXP (x, 1)); } diff --git a/gcc/config/m68k/m68k.md b/gcc/config/m68k/m68k.md index 1eff7f43723..c74b1424e57 100644 --- a/gcc/config/m68k/m68k.md +++ b/gcc/config/m68k/m68k.md @@ -1554,7 +1554,7 @@ operands[1] = make_safe_from (operands[1], operands[0]); if (GET_CODE (operands[0]) == SUBREG) operands[2] = gen_rtx_SUBREG (HImode, SUBREG_REG (operands[0]), - SUBREG_WORD (operands[0])); + SUBREG_BYTE (operands[0])); else operands[2] = gen_rtx_SUBREG (HImode, operands[0], 0); }") @@ -1570,7 +1570,7 @@ operands[1] = make_safe_from (operands[1], operands[0]); if (GET_CODE (operands[0]) == SUBREG) operands[2] = gen_rtx_SUBREG (QImode, SUBREG_REG (operands[0]), - SUBREG_WORD (operands[0])); + SUBREG_BYTE (operands[0])); else operands[2] = gen_rtx_SUBREG (QImode, operands[0], 0); }") @@ -1586,7 +1586,7 @@ operands[1] = make_safe_from (operands[1], operands[0]); if (GET_CODE (operands[0]) == SUBREG) operands[2] = gen_rtx_SUBREG (QImode, SUBREG_REG (operands[0]), - SUBREG_WORD (operands[0])); + SUBREG_BYTE (operands[0])); else operands[2] = gen_rtx_SUBREG (QImode, operands[0], 0); }") @@ -3096,7 +3096,7 @@ ;; the high-numbered word of the DImode operand[0] and operand[1]. (define_expand "umulsidi3" [(parallel - [(set (subreg:SI (match_operand:DI 0 "register_operand" "") 1) + [(set (subreg:SI (match_operand:DI 0 "register_operand" "") 4) (mult:SI (match_operand:SI 1 "register_operand" "") (match_operand:SI 2 "nonimmediate_operand" ""))) (set (subreg:SI (match_dup 0) 0) @@ -3135,7 +3135,7 @@ (define_expand "mulsidi3" [(parallel - [(set (subreg:SI (match_operand:DI 0 "register_operand" "") 1) + [(set (subreg:SI (match_operand:DI 0 "register_operand" "") 4) (mult:SI (match_operand:SI 1 "register_operand" "") (match_operand:SI 2 "nonimmediate_operand" ""))) (set (subreg:SI (match_dup 0) 0) @@ -4731,7 +4731,7 @@ (define_insn "subreghi1ashrdi_const32" [(set (match_operand:HI 0 "general_operand" "=rm") (subreg:HI (ashiftrt:DI (match_operand:DI 1 "general_operand" "ro") - (const_int 32)) 1))] + (const_int 32)) 4))] "" "* { @@ -4743,7 +4743,7 @@ (define_insn "subregsi1ashrdi_const32" [(set (match_operand:SI 0 "general_operand" "=rm") (subreg:SI (ashiftrt:DI (match_operand:DI 1 "general_operand" "ro") - (const_int 32)) 1))] + (const_int 32)) 4))] "" "* { @@ -4894,10 +4894,10 @@ ;;(define_insn "" ;; [(set (cc0) ;; (subreg:SI (lshiftrt:DI (match_operand:DI 0 "general_operand" "ro") -;; (const_int 32)) 1)) +;; (const_int 32)) 4)) ;; (set (match_operand:SI 1 "general_operand" "=dm") ;; (subreg:SI (lshiftrt:DI (match_dup 0) -;; (const_int 32)) 1))] +;; (const_int 32)) 4))] ;; "" ;; "* ;;{ @@ -4924,7 +4924,7 @@ (define_insn "subreg1lshrdi_const32" [(set (match_operand:SI 0 "general_operand" "=rm") (subreg:SI (lshiftrt:DI (match_operand:DI 1 "general_operand" "ro") - (const_int 32)) 1))] + (const_int 32)) 4))] "" "* { diff --git a/gcc/config/m88k/m88k.md b/gcc/config/m88k/m88k.md index d8e7a738bcf..7a1ac64ed18 100644 --- a/gcc/config/m88k/m88k.md +++ b/gcc/config/m88k/m88k.md @@ -2295,10 +2295,10 @@ ;;- sign extension instructions (define_expand "extendsidi2" - [(set (subreg:SI (match_operand:DI 0 "register_operand" "=r") 1) + [(set (subreg:SI (match_operand:DI 0 "register_operand" "=r") 4) (match_operand:SI 1 "general_operand" "g")) (set (subreg:SI (match_dup 0) 0) - (ashiftrt:SI (subreg:SI (match_dup 0) 1) + (ashiftrt:SI (subreg:SI (match_dup 0) 4) (const_int 31)))] "" "") diff --git a/gcc/config/mips/mips.c b/gcc/config/mips/mips.c index e33cb9b65a3..aeccb3fae20 100644 --- a/gcc/config/mips/mips.c +++ b/gcc/config/mips/mips.c @@ -1833,20 +1833,26 @@ mips_move_1word (operands, insn, unsignedp) enum rtx_code code0 = GET_CODE (op0); enum rtx_code code1 = GET_CODE (op1); enum machine_mode mode = GET_MODE (op0); - int subreg_word0 = 0; - int subreg_word1 = 0; + int subreg_offset0 = 0; + int subreg_offset1 = 0; enum delay_type delay = DELAY_NONE; while (code0 == SUBREG) { - subreg_word0 += SUBREG_WORD (op0); + subreg_offset0 += subreg_regno_offset (REGNO (SUBREG_REG (op0)), + GET_MODE (SUBREG_REG (op0)), + SUBREG_BYTE (op0), + GET_MODE (op0)); op0 = SUBREG_REG (op0); code0 = GET_CODE (op0); } while (code1 == SUBREG) { - subreg_word1 += SUBREG_WORD (op1); + subreg_offset1 += subreg_regno_offset (REGNO (SUBREG_REG (op1)), + GET_MODE (SUBREG_REG (op1)), + SUBREG_BYTE (op1), + GET_MODE (op1)); op1 = SUBREG_REG (op1); code1 = GET_CODE (op1); } @@ -1857,11 +1863,11 @@ mips_move_1word (operands, insn, unsignedp) if (code0 == REG) { - int regno0 = REGNO (op0) + subreg_word0; + int regno0 = REGNO (op0) + subreg_offset0; if (code1 == REG) { - int regno1 = REGNO (op1) + subreg_word1; + int regno1 = REGNO (op1) + subreg_offset1; /* Just in case, don't do anything for assigning a register to itself, unless we are filling a delay slot. */ @@ -2146,7 +2152,7 @@ mips_move_1word (operands, insn, unsignedp) if (code1 == REG) { - int regno1 = REGNO (op1) + subreg_word1; + int regno1 = REGNO (op1) + subreg_offset1; if (GP_REG_P (regno1)) { @@ -2225,13 +2231,16 @@ mips_move_2words (operands, insn) rtx op1 = operands[1]; enum rtx_code code0 = GET_CODE (operands[0]); enum rtx_code code1 = GET_CODE (operands[1]); - int subreg_word0 = 0; - int subreg_word1 = 0; + int subreg_offset0 = 0; + int subreg_offset1 = 0; enum delay_type delay = DELAY_NONE; while (code0 == SUBREG) { - subreg_word0 += SUBREG_WORD (op0); + subreg_offset0 += subreg_regno_offset (REGNO (SUBREG_REG (op0)), + GET_MODE (SUBREG_REG (op0)), + SUBREG_BYTE (op0), + GET_MODE (op0)); op0 = SUBREG_REG (op0); code0 = GET_CODE (op0); } @@ -2244,7 +2253,10 @@ mips_move_2words (operands, insn) while (code1 == SUBREG) { - subreg_word1 += SUBREG_WORD (op1); + subreg_offset1 += subreg_regno_offset (REGNO (SUBREG_REG (op1)), + GET_MODE (SUBREG_REG (op1)), + SUBREG_BYTE (op1), + GET_MODE (op1)); op1 = SUBREG_REG (op1); code1 = GET_CODE (op1); } @@ -2262,11 +2274,11 @@ mips_move_2words (operands, insn) if (code0 == REG) { - int regno0 = REGNO (op0) + subreg_word0; + int regno0 = REGNO (op0) + subreg_offset0; if (code1 == REG) { - int regno1 = REGNO (op1) + subreg_word1; + int regno1 = REGNO (op1) + subreg_offset1; /* Just in case, don't do anything for assigning a register to itself, unless we are filling a delay slot. */ @@ -2603,7 +2615,7 @@ mips_move_2words (operands, insn) { if (code1 == REG) { - int regno1 = REGNO (op1) + subreg_word1; + int regno1 = REGNO (op1) + subreg_offset1; if (FP_REG_P (regno1)) ret = "s.d\t%1,%0"; @@ -7888,7 +7900,10 @@ mips_secondary_reload_class (class, mode, x, in_p) { while (GET_CODE (x) == SUBREG) { - off += SUBREG_WORD (x); + off += subreg_regno_offset (REGNO (SUBREG_REG (x)), + GET_MODE (SUBREG_REG (x)), + SUBREG_BYTE (x), + GET_MODE (x)); x = SUBREG_REG (x); } diff --git a/gcc/config/mips/mips.md b/gcc/config/mips/mips.md index ceb4f6a2b11..d7c421327d6 100644 --- a/gcc/config/mips/mips.md +++ b/gcc/config/mips/mips.md @@ -790,12 +790,12 @@ (ltu:SI (subreg:SI (match_dup 0) 0) (subreg:SI (match_dup 2) 0))) - (set (subreg:SI (match_dup 0) 1) - (plus:SI (subreg:SI (match_dup 1) 1) - (subreg:SI (match_dup 2) 1))) + (set (subreg:SI (match_dup 0) 4) + (plus:SI (subreg:SI (match_dup 1) 4) + (subreg:SI (match_dup 2) 4))) - (set (subreg:SI (match_dup 0) 1) - (plus:SI (subreg:SI (match_dup 0) 1) + (set (subreg:SI (match_dup 0) 4) + (plus:SI (subreg:SI (match_dup 0) 4) (match_dup 3)))] "") @@ -812,13 +812,13 @@ && (REGNO (operands[0]) != REGNO (operands[1]) || REGNO (operands[0]) != REGNO (operands[2]))" - [(set (subreg:SI (match_dup 0) 1) - (plus:SI (subreg:SI (match_dup 1) 1) - (subreg:SI (match_dup 2) 1))) + [(set (subreg:SI (match_dup 0) 4) + (plus:SI (subreg:SI (match_dup 1) 4) + (subreg:SI (match_dup 2) 4))) (set (match_dup 3) - (ltu:SI (subreg:SI (match_dup 0) 1) - (subreg:SI (match_dup 2) 1))) + (ltu:SI (subreg:SI (match_dup 0) 4) + (subreg:SI (match_dup 2) 4))) (set (subreg:SI (match_dup 0) 0) (plus:SI (subreg:SI (match_dup 1) 0) @@ -865,8 +865,8 @@ (ltu:SI (subreg:SI (match_dup 0) 0) (match_dup 2))) - (set (subreg:SI (match_dup 0) 1) - (plus:SI (subreg:SI (match_dup 1) 1) + (set (subreg:SI (match_dup 0) 4) + (plus:SI (subreg:SI (match_dup 1) 4) (match_dup 3)))] "") @@ -881,12 +881,12 @@ && GET_CODE (operands[1]) == REG && GP_REG_P (REGNO (operands[1])) && INTVAL (operands[2]) > 0" - [(set (subreg:SI (match_dup 0) 1) - (plus:SI (subreg:SI (match_dup 1) 1) + [(set (subreg:SI (match_dup 0) 4) + (plus:SI (subreg:SI (match_dup 1) 4) (match_dup 2))) (set (match_dup 3) - (ltu:SI (subreg:SI (match_dup 0) 1) + (ltu:SI (subreg:SI (match_dup 0) 4) (match_dup 2))) (set (subreg:SI (match_dup 0) 0) @@ -1307,12 +1307,12 @@ (minus:SI (subreg:SI (match_dup 1) 0) (subreg:SI (match_dup 2) 0))) - (set (subreg:SI (match_dup 0) 1) - (minus:SI (subreg:SI (match_dup 1) 1) - (subreg:SI (match_dup 2) 1))) + (set (subreg:SI (match_dup 0) 4) + (minus:SI (subreg:SI (match_dup 1) 4) + (subreg:SI (match_dup 2) 4))) - (set (subreg:SI (match_dup 0) 1) - (minus:SI (subreg:SI (match_dup 0) 1) + (set (subreg:SI (match_dup 0) 4) + (minus:SI (subreg:SI (match_dup 0) 4) (match_dup 3)))] "") @@ -1328,12 +1328,12 @@ && GET_CODE (operands[2]) == REG && GP_REG_P (REGNO (operands[2]))" [(set (match_dup 3) - (ltu:SI (subreg:SI (match_dup 1) 1) - (subreg:SI (match_dup 2) 1))) + (ltu:SI (subreg:SI (match_dup 1) 4) + (subreg:SI (match_dup 2) 4))) - (set (subreg:SI (match_dup 0) 1) - (minus:SI (subreg:SI (match_dup 1) 1) - (subreg:SI (match_dup 2) 1))) + (set (subreg:SI (match_dup 0) 4) + (minus:SI (subreg:SI (match_dup 1) 4) + (subreg:SI (match_dup 2) 4))) (set (subreg:SI (match_dup 0) 0) (minus:SI (subreg:SI (match_dup 1) 0) @@ -1378,8 +1378,8 @@ (minus:SI (subreg:SI (match_dup 1) 0) (match_dup 2))) - (set (subreg:SI (match_dup 0) 1) - (minus:SI (subreg:SI (match_dup 1) 1) + (set (subreg:SI (match_dup 0) 4) + (minus:SI (subreg:SI (match_dup 1) 4) (match_dup 3)))] "") @@ -1395,11 +1395,11 @@ && INTVAL (operands[2]) > 0" [(set (match_dup 3) - (ltu:SI (subreg:SI (match_dup 1) 1) + (ltu:SI (subreg:SI (match_dup 1) 4) (match_dup 2))) - (set (subreg:SI (match_dup 0) 1) - (minus:SI (subreg:SI (match_dup 1) 1) + (set (subreg:SI (match_dup 0) 4) + (minus:SI (subreg:SI (match_dup 1) 4) (match_dup 2))) (set (subreg:SI (match_dup 0) 0) @@ -3121,7 +3121,7 @@ move\\t%0,%z4\\n\\ && GET_CODE (operands[1]) == REG && GP_REG_P (REGNO (operands[1]))" [(set (subreg:SI (match_dup 0) 0) (not:SI (subreg:SI (match_dup 1) 0))) - (set (subreg:SI (match_dup 0) 1) (not:SI (subreg:SI (match_dup 1) 1)))] + (set (subreg:SI (match_dup 0) 4) (not:SI (subreg:SI (match_dup 1) 4)))] "") @@ -3224,7 +3224,7 @@ move\\t%0,%z4\\n\\ && GET_CODE (operands[2]) == REG && GP_REG_P (REGNO (operands[2]))" [(set (subreg:SI (match_dup 0) 0) (and:SI (subreg:SI (match_dup 1) 0) (subreg:SI (match_dup 2) 0))) - (set (subreg:SI (match_dup 0) 1) (and:SI (subreg:SI (match_dup 1) 1) (subreg:SI (match_dup 2) 1)))] + (set (subreg:SI (match_dup 0) 4) (and:SI (subreg:SI (match_dup 1) 4) (subreg:SI (match_dup 2) 4)))] "") (define_insn "anddi3_internal1" @@ -3325,7 +3325,7 @@ move\\t%0,%z4\\n\\ && GET_CODE (operands[2]) == REG && GP_REG_P (REGNO (operands[2]))" [(set (subreg:SI (match_dup 0) 0) (ior:SI (subreg:SI (match_dup 1) 0) (subreg:SI (match_dup 2) 0))) - (set (subreg:SI (match_dup 0) 1) (ior:SI (subreg:SI (match_dup 1) 1) (subreg:SI (match_dup 2) 1)))] + (set (subreg:SI (match_dup 0) 4) (ior:SI (subreg:SI (match_dup 1) 4) (subreg:SI (match_dup 2) 4)))] "") (define_expand "xorsi3" @@ -3429,7 +3429,7 @@ move\\t%0,%z4\\n\\ && GET_CODE (operands[2]) == REG && GP_REG_P (REGNO (operands[2]))" [(set (subreg:SI (match_dup 0) 0) (xor:SI (subreg:SI (match_dup 1) 0) (subreg:SI (match_dup 2) 0))) - (set (subreg:SI (match_dup 0) 1) (xor:SI (subreg:SI (match_dup 1) 1) (subreg:SI (match_dup 2) 1)))] + (set (subreg:SI (match_dup 0) 4) (xor:SI (subreg:SI (match_dup 1) 4) (subreg:SI (match_dup 2) 4)))] "") (define_insn "xordi3_immed" @@ -3478,7 +3478,7 @@ move\\t%0,%z4\\n\\ && GET_CODE (operands[2]) == REG && GP_REG_P (REGNO (operands[2]))" [(set (subreg:SI (match_dup 0) 0) (and:SI (not:SI (subreg:SI (match_dup 1) 0)) (not:SI (subreg:SI (match_dup 2) 0)))) - (set (subreg:SI (match_dup 0) 1) (and:SI (not:SI (subreg:SI (match_dup 1) 1)) (not:SI (subreg:SI (match_dup 2) 1))))] + (set (subreg:SI (match_dup 0) 4) (and:SI (not:SI (subreg:SI (match_dup 1) 4)) (not:SI (subreg:SI (match_dup 2) 4))))] "") ;; @@ -4917,7 +4917,7 @@ move\\t%0,%z4\\n\\ && GET_CODE (operands[1]) == REG && GP_REG_P (REGNO (operands[1]))" [(set (subreg:SI (match_dup 0) 0) (subreg:SI (match_dup 1) 0)) - (set (subreg:SI (match_dup 0) 1) (subreg:SI (match_dup 1) 1))] + (set (subreg:SI (match_dup 0) 4) (subreg:SI (match_dup 1) 4))] "") (define_insn "movdi_internal2" @@ -6147,7 +6147,7 @@ move\\t%0,%z4\\n\\ && GET_CODE (operands[0]) == REG && GP_REG_P (REGNO (operands[0])) && GET_CODE (operands[1]) == REG && GP_REG_P (REGNO (operands[1]))" [(set (subreg:SI (match_dup 0) 0) (subreg:SI (match_dup 1) 0)) - (set (subreg:SI (match_dup 0) 1) (subreg:SI (match_dup 1) 1))] + (set (subreg:SI (match_dup 0) 4) (subreg:SI (match_dup 1) 4))] "") ;; Instructions to load the global pointer register. @@ -6516,7 +6516,7 @@ move\\t%0,%z4\\n\\ && GET_CODE (operands[1]) == REG && REGNO (operands[1]) < FIRST_PSEUDO_REGISTER && (INTVAL (operands[2]) & 32) != 0" - [(set (subreg:SI (match_dup 0) 1) (ashift:SI (subreg:SI (match_dup 1) 0) (match_dup 2))) + [(set (subreg:SI (match_dup 0) 4) (ashift:SI (subreg:SI (match_dup 1) 0) (match_dup 2))) (set (subreg:SI (match_dup 0) 0) (const_int 0))] "operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f);") @@ -6533,8 +6533,8 @@ move\\t%0,%z4\\n\\ && GET_CODE (operands[1]) == REG && REGNO (operands[1]) < FIRST_PSEUDO_REGISTER && (INTVAL (operands[2]) & 32) != 0" - [(set (subreg:SI (match_dup 0) 0) (ashift:SI (subreg:SI (match_dup 1) 1) (match_dup 2))) - (set (subreg:SI (match_dup 0) 1) (const_int 0))] + [(set (subreg:SI (match_dup 0) 0) (ashift:SI (subreg:SI (match_dup 1) 4) (match_dup 2))) + (set (subreg:SI (match_dup 0) 4) (const_int 0))] "operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f);") @@ -6574,16 +6574,16 @@ move\\t%0,%z4\\n\\ && (INTVAL (operands[2]) & 63) < 32 && (INTVAL (operands[2]) & 63) != 0" - [(set (subreg:SI (match_dup 0) 1) - (ashift:SI (subreg:SI (match_dup 1) 1) + [(set (subreg:SI (match_dup 0) 4) + (ashift:SI (subreg:SI (match_dup 1) 4) (match_dup 2))) (set (match_dup 3) (lshiftrt:SI (subreg:SI (match_dup 1) 0) (match_dup 4))) - (set (subreg:SI (match_dup 0) 1) - (ior:SI (subreg:SI (match_dup 0) 1) + (set (subreg:SI (match_dup 0) 4) + (ior:SI (subreg:SI (match_dup 0) 4) (match_dup 3))) (set (subreg:SI (match_dup 0) 0) @@ -6614,15 +6614,15 @@ move\\t%0,%z4\\n\\ (match_dup 2))) (set (match_dup 3) - (lshiftrt:SI (subreg:SI (match_dup 1) 1) + (lshiftrt:SI (subreg:SI (match_dup 1) 4) (match_dup 4))) (set (subreg:SI (match_dup 0) 0) (ior:SI (subreg:SI (match_dup 0) 0) (match_dup 3))) - (set (subreg:SI (match_dup 0) 1) - (ashift:SI (subreg:SI (match_dup 1) 1) + (set (subreg:SI (match_dup 0) 4) + (ashift:SI (subreg:SI (match_dup 1) 4) (match_dup 2)))] " { @@ -6871,8 +6871,8 @@ move\\t%0,%z4\\n\\ && GET_CODE (operands[1]) == REG && REGNO (operands[1]) < FIRST_PSEUDO_REGISTER && (INTVAL (operands[2]) & 32) != 0" - [(set (subreg:SI (match_dup 0) 0) (ashiftrt:SI (subreg:SI (match_dup 1) 1) (match_dup 2))) - (set (subreg:SI (match_dup 0) 1) (ashiftrt:SI (subreg:SI (match_dup 1) 1) (const_int 31)))] + [(set (subreg:SI (match_dup 0) 0) (ashiftrt:SI (subreg:SI (match_dup 1) 4) (match_dup 2))) + (set (subreg:SI (match_dup 0) 4) (ashiftrt:SI (subreg:SI (match_dup 1) 4) (const_int 31)))] "operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f);") @@ -6887,7 +6887,7 @@ move\\t%0,%z4\\n\\ && GET_CODE (operands[1]) == REG && REGNO (operands[1]) < FIRST_PSEUDO_REGISTER && (INTVAL (operands[2]) & 32) != 0" - [(set (subreg:SI (match_dup 0) 1) (ashiftrt:SI (subreg:SI (match_dup 1) 0) (match_dup 2))) + [(set (subreg:SI (match_dup 0) 4) (ashiftrt:SI (subreg:SI (match_dup 1) 0) (match_dup 2))) (set (subreg:SI (match_dup 0) 0) (ashiftrt:SI (subreg:SI (match_dup 1) 0) (const_int 31)))] "operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f);") @@ -6932,15 +6932,15 @@ move\\t%0,%z4\\n\\ (match_dup 2))) (set (match_dup 3) - (ashift:SI (subreg:SI (match_dup 1) 1) + (ashift:SI (subreg:SI (match_dup 1) 4) (match_dup 4))) (set (subreg:SI (match_dup 0) 0) (ior:SI (subreg:SI (match_dup 0) 0) (match_dup 3))) - (set (subreg:SI (match_dup 0) 1) - (ashiftrt:SI (subreg:SI (match_dup 1) 1) + (set (subreg:SI (match_dup 0) 4) + (ashiftrt:SI (subreg:SI (match_dup 1) 4) (match_dup 2)))] " { @@ -6962,16 +6962,16 @@ move\\t%0,%z4\\n\\ && (INTVAL (operands[2]) & 63) < 32 && (INTVAL (operands[2]) & 63) != 0" - [(set (subreg:SI (match_dup 0) 1) - (lshiftrt:SI (subreg:SI (match_dup 1) 1) + [(set (subreg:SI (match_dup 0) 4) + (lshiftrt:SI (subreg:SI (match_dup 1) 4) (match_dup 2))) (set (match_dup 3) (ashift:SI (subreg:SI (match_dup 1) 0) (match_dup 4))) - (set (subreg:SI (match_dup 0) 1) - (ior:SI (subreg:SI (match_dup 0) 1) + (set (subreg:SI (match_dup 0) 4) + (ior:SI (subreg:SI (match_dup 0) 4) (match_dup 3))) (set (subreg:SI (match_dup 0) 0) @@ -7255,8 +7255,8 @@ move\\t%0,%z4\\n\\ && GET_CODE (operands[1]) == REG && REGNO (operands[1]) < FIRST_PSEUDO_REGISTER && (INTVAL (operands[2]) & 32) != 0" - [(set (subreg:SI (match_dup 0) 0) (lshiftrt:SI (subreg:SI (match_dup 1) 1) (match_dup 2))) - (set (subreg:SI (match_dup 0) 1) (const_int 0))] + [(set (subreg:SI (match_dup 0) 0) (lshiftrt:SI (subreg:SI (match_dup 1) 4) (match_dup 2))) + (set (subreg:SI (match_dup 0) 4) (const_int 0))] "operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f);") @@ -7272,7 +7272,7 @@ move\\t%0,%z4\\n\\ && GET_CODE (operands[1]) == REG && REGNO (operands[1]) < FIRST_PSEUDO_REGISTER && (INTVAL (operands[2]) & 32) != 0" - [(set (subreg:SI (match_dup 0) 1) (lshiftrt:SI (subreg:SI (match_dup 1) 0) (match_dup 2))) + [(set (subreg:SI (match_dup 0) 4) (lshiftrt:SI (subreg:SI (match_dup 1) 0) (match_dup 2))) (set (subreg:SI (match_dup 0) 0) (const_int 0))] "operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f);") @@ -7317,15 +7317,15 @@ move\\t%0,%z4\\n\\ (match_dup 2))) (set (match_dup 3) - (ashift:SI (subreg:SI (match_dup 1) 1) + (ashift:SI (subreg:SI (match_dup 1) 4) (match_dup 4))) (set (subreg:SI (match_dup 0) 0) (ior:SI (subreg:SI (match_dup 0) 0) (match_dup 3))) - (set (subreg:SI (match_dup 0) 1) - (lshiftrt:SI (subreg:SI (match_dup 1) 1) + (set (subreg:SI (match_dup 0) 4) + (lshiftrt:SI (subreg:SI (match_dup 1) 4) (match_dup 2)))] " { @@ -7347,16 +7347,16 @@ move\\t%0,%z4\\n\\ && (INTVAL (operands[2]) & 63) < 32 && (INTVAL (operands[2]) & 63) != 0" - [(set (subreg:SI (match_dup 0) 1) - (lshiftrt:SI (subreg:SI (match_dup 1) 1) + [(set (subreg:SI (match_dup 0) 4) + (lshiftrt:SI (subreg:SI (match_dup 1) 4) (match_dup 2))) (set (match_dup 3) (ashift:SI (subreg:SI (match_dup 1) 0) (match_dup 4))) - (set (subreg:SI (match_dup 0) 1) - (ior:SI (subreg:SI (match_dup 0) 1) + (set (subreg:SI (match_dup 0) 4) + (ior:SI (subreg:SI (match_dup 0) 4) (match_dup 3))) (set (subreg:SI (match_dup 0) 0) diff --git a/gcc/config/mn10200/mn10200.c b/gcc/config/mn10200/mn10200.c index 1e520a84c60..1a4f9dd0f03 100644 --- a/gcc/config/mn10200/mn10200.c +++ b/gcc/config/mn10200/mn10200.c @@ -162,8 +162,7 @@ print_operand (file, x, code) break; case SUBREG: - fprintf (file, "%s", - reg_names[REGNO (SUBREG_REG (x)) + SUBREG_WORD (x)]); + fprintf (file, "%s", reg_names[subreg_regno (x)]); break; case CONST_DOUBLE: @@ -222,8 +221,7 @@ print_operand (file, x, code) break; case SUBREG: - fprintf (file, "%s", - reg_names[REGNO (SUBREG_REG (x)) + SUBREG_WORD (x)] + 1); + fprintf (file, "%s", reg_names[subreg_regno (x) + 1]); break; case CONST_DOUBLE: @@ -322,8 +320,7 @@ print_operand (file, x, code) break; case SUBREG: - fprintf (file, "%s", - reg_names[REGNO (SUBREG_REG (x)) + SUBREG_WORD (x)]); + fprintf (file, "%s", reg_names[subreg_regno (x)]); break; case CONST_INT: diff --git a/gcc/config/mn10300/mn10300.c b/gcc/config/mn10300/mn10300.c index 225c8789994..7f1c0363587 100644 --- a/gcc/config/mn10300/mn10300.c +++ b/gcc/config/mn10300/mn10300.c @@ -143,8 +143,7 @@ print_operand (file, x, code) break; case SUBREG: - fprintf (file, "%s", - reg_names[REGNO (SUBREG_REG (x)) + SUBREG_WORD (x)]); + fprintf (file, "%s", reg_names[subreg_regno (x)]); break; case CONST_DOUBLE: @@ -204,8 +203,7 @@ print_operand (file, x, code) break; case SUBREG: - fprintf (file, "%s", - reg_names[REGNO (SUBREG_REG (x)) + SUBREG_WORD (x)] + 1); + fprintf (file, "%s", reg_names[subreg_regno (x) + 1]); break; case CONST_DOUBLE: @@ -289,8 +287,7 @@ print_operand (file, x, code) break; case SUBREG: - fprintf (file, "%s", - reg_names[REGNO (SUBREG_REG (x)) + SUBREG_WORD (x)]); + fprintf (file, "%s", reg_names[subreg_regno (x)]); break; /* This will only be single precision.... */ diff --git a/gcc/config/ns32k/ns32k.md b/gcc/config/ns32k/ns32k.md index 2b811621be7..f7646d391d6 100644 --- a/gcc/config/ns32k/ns32k.md +++ b/gcc/config/ns32k/ns32k.md @@ -1275,7 +1275,7 @@ ;; Retain this insn which *does* have a pattern indicating what it does, ;; just in case the compiler is smart enough to recognize a substitution. (define_insn "udivmoddisi4" - [(set (subreg:SI (match_operand:DI 0 "nonimmediate_operand" "=rm") 1) + [(set (subreg:SI (match_operand:DI 0 "nonimmediate_operand" "=rm") 4) (truncate:SI (udiv:DI (match_operand:DI 1 "nonimmediate_operand" "0") (zero_extend:DI (match_operand:SI 2 "nonimmediate_operand" "rm"))))) (set (subreg:SI (match_operand:DI 3 "nonimmediate_operand" "=0") 0) @@ -1338,7 +1338,7 @@ "deiw %2,%0") (define_insn "udivmoddihi4" - [(set (subreg:HI (match_operand:DI 0 "register_operand" "=r") 1) + [(set (subreg:HI (match_operand:DI 0 "register_operand" "=r") 2) (truncate:HI (udiv:DI (match_operand:DI 1 "register_operand" "0") (zero_extend:DI (match_operand:HI 2 "nonimmediate_operand" "rm"))))) (set (subreg:HI (match_operand:DI 3 "register_operand" "=0") 0) diff --git a/gcc/config/pa/pa.c b/gcc/config/pa/pa.c index 26e80966c95..502d204e74d 100644 --- a/gcc/config/pa/pa.c +++ b/gcc/config/pa/pa.c @@ -1192,11 +1192,11 @@ emit_move_sequence (operands, mode, scratch_reg) && GET_CODE (SUBREG_REG (operand0)) == REG && REGNO (SUBREG_REG (operand0)) >= FIRST_PSEUDO_REGISTER) { - /* We must not alter SUBREG_WORD (operand0) since that would confuse + /* We must not alter SUBREG_BYTE (operand0) since that would confuse the code which tracks sets/uses for delete_output_reload. */ rtx temp = gen_rtx_SUBREG (GET_MODE (operand0), reg_equiv_mem [REGNO (SUBREG_REG (operand0))], - SUBREG_WORD (operand0)); + SUBREG_BYTE (operand0)); operand0 = alter_subreg (temp); } @@ -1209,11 +1209,11 @@ emit_move_sequence (operands, mode, scratch_reg) && GET_CODE (SUBREG_REG (operand1)) == REG && REGNO (SUBREG_REG (operand1)) >= FIRST_PSEUDO_REGISTER) { - /* We must not alter SUBREG_WORD (operand0) since that would confuse + /* We must not alter SUBREG_BYTE (operand0) since that would confuse the code which tracks sets/uses for delete_output_reload. */ rtx temp = gen_rtx_SUBREG (GET_MODE (operand1), reg_equiv_mem [REGNO (SUBREG_REG (operand1))], - SUBREG_WORD (operand1)); + SUBREG_BYTE (operand1)); operand1 = alter_subreg (temp); } diff --git a/gcc/config/pa/pa.md b/gcc/config/pa/pa.md index ceea64cfa82..baeef934243 100644 --- a/gcc/config/pa/pa.md +++ b/gcc/config/pa/pa.md @@ -3505,9 +3505,9 @@ (set_attr "length" "4")]) (define_expand "floatunssisf2" - [(set (subreg:SI (match_dup 2) 1) + [(set (subreg:SI (match_dup 2) 4) (match_operand:SI 1 "register_operand" "")) - (set (subreg:SI (match_dup 2) 0) + (set (subreg:SI (match_dup 2) 4) (const_int 0)) (set (match_operand:SF 0 "register_operand" "") (float:SF (match_dup 2)))] @@ -3523,7 +3523,7 @@ }") (define_expand "floatunssidf2" - [(set (subreg:SI (match_dup 2) 1) + [(set (subreg:SI (match_dup 2) 4) (match_operand:SI 1 "register_operand" "")) (set (subreg:SI (match_dup 2) 0) (const_int 0)) @@ -3891,7 +3891,7 @@ } emit_insn (gen_rtx_SET (VOIDmode, operands[0], - gen_rtx_SUBREG (SImode, scratch, 1))); + gen_rtx_SUBREG (SImode, scratch, GET_MODE_SIZE (SImode)))); DONE; } operands[3] = gen_reg_rtx (SImode); diff --git a/gcc/config/pdp11/pdp11.md b/gcc/config/pdp11/pdp11.md index 9171a773386..7fc7f8dc281 100644 --- a/gcc/config/pdp11/pdp11.md +++ b/gcc/config/pdp11/pdp11.md @@ -766,7 +766,7 @@ (define_expand "zero_extendhisi2" [(set (subreg:HI (match_dup 0) - 1) + 2) (match_operand:HI 1 "register_operand" "r")) (set (subreg:HI (match_operand:SI 0 "register_operand" "=r") @@ -1782,16 +1782,16 @@ [(set_attr "length" "2")]) (define_expand "modhi3" - [(set (subreg:HI (match_dup 1) 1) + [(set (subreg:HI (match_dup 1) 2) (mod:HI (match_operand:SI 1 "general_operand" "0") (match_operand:HI 2 "general_operand" "g"))) (set (match_operand:HI 0 "general_operand" "=r") - (subreg:HI (match_dup 1) 1))] + (subreg:HI (match_dup 1) 2))] "TARGET_45" "") (define_insn "" - [(set (subreg:HI (match_operand:SI 0 "general_operand" "=r") 1) + [(set (subreg:HI (match_operand:SI 0 "general_operand" "=r") 4) (mod:HI (match_operand:SI 1 "general_operand" "0") (match_operand:HI 2 "general_operand" "g")))] "TARGET_45" @@ -1802,11 +1802,11 @@ ; [(parallel [(set (subreg:HI (match_dup 1) 0) ; (div:HI (match_operand:SI 1 "general_operand" "0") ; (match_operand:HI 2 "general_operand" "g"))) -; (set (subreg:HI (match_dup 1) 1) +; (set (subreg:HI (match_dup 1) 2) ; (mod:HI (match_dup 1) ; (match_dup 2)))]) ; (set (match_operand:HI 3 "general_operand" "=r") -; (subreg:HI (match_dup 1) 1)) +; (subreg:HI (match_dup 1) 2)) ; (set (match_operand:HI 0 "general_operand" "=r") ; (subreg:HI (match_dup 1) 0))] ; "TARGET_45" @@ -1816,7 +1816,7 @@ ; [(set (subreg:HI (match_operand:SI 0 "general_operand" "=r") 0) ; (div:HI (match_operand:SI 1 "general_operand" "0") ; (match_operand:HI 2 "general_operand" "g"))) -; (set (subreg:HI (match_dup 0) 1) +; (set (subreg:HI (match_dup 0) 2) ; (mod:HI (match_dup 1) ; (match_dup 2)))] ; "TARGET_45" diff --git a/gcc/config/romp/romp.c b/gcc/config/romp/romp.c index 7aedeb60024..8cabb46e825 100644 --- a/gcc/config/romp/romp.c +++ b/gcc/config/romp/romp.c @@ -269,12 +269,7 @@ memory_offset_in_range_p (op, mode, low, high) while (GET_CODE (op) == SUBREG) { - offset += SUBREG_WORD (op) * UNITS_PER_WORD; -#if BYTES_BIG_ENDIAN - offset -= (min (UNITS_PER_WORD, GET_MODE_SIZE (GET_MODE (op))) - - min (UNITS_PER_WORD, - GET_MODE_SIZE (GET_MODE (SUBREG_REG (op))))); -#endif + offset += SUBREG_BYTE (op); op = SUBREG_REG (op); } diff --git a/gcc/config/sh/sh.c b/gcc/config/sh/sh.c index 4cb5cf27fb0..d8d4ef3581b 100644 --- a/gcc/config/sh/sh.c +++ b/gcc/config/sh/sh.c @@ -666,7 +666,7 @@ output_movedouble (insn, operands, mode) if (GET_CODE (inside) == REG) ptrreg = REGNO (inside); else if (GET_CODE (inside) == SUBREG) - ptrreg = REGNO (SUBREG_REG (inside)) + SUBREG_WORD (inside); + ptrreg = subreg_regno (inside); else if (GET_CODE (inside) == PLUS) { ptrreg = REGNO (XEXP (inside, 0)); @@ -1143,13 +1143,13 @@ gen_ashift_hi (type, n, reg) gen_ashift_hi is only called in contexts where we know that the sign extension works out correctly. */ { - int word = 0; + int offset = 0; if (GET_CODE (reg) == SUBREG) { - word = SUBREG_WORD (reg); + offset = SUBREG_BYTE (reg); reg = SUBREG_REG (reg); } - gen_ashift (type, n, gen_rtx_SUBREG (SImode, reg, word)); + gen_ashift (type, n, gen_rtx_SUBREG (SImode, reg, offset)); break; } case ASHIFT: @@ -2516,7 +2516,11 @@ regs_used (x, is_dest) break; if (REGNO (y) < 16) return (((1 << HARD_REGNO_NREGS (0, GET_MODE (x))) - 1) - << (REGNO (y) + SUBREG_WORD (x) + is_dest)); + << (REGNO (y) + + subreg_regno_offset (REGNO (y), + GET_MODE (y), + SUBREG_BYTE (x), + GET_MODE (x)) + is_dest)); return 0; } case SET: @@ -3260,7 +3264,10 @@ machine_dependent_reorg (first) mode = HImode; while (GET_CODE (dst) == SUBREG) { - offset += SUBREG_WORD (dst); + offset += subreg_regno_offset (REGNO (SUBREG_REG (dst)), + GET_MODE (SUBREG_REG (dst)), + SUBREG_BYTE (dst), + GET_MODE (dst)); dst = SUBREG_REG (dst); } dst = gen_rtx_REG (HImode, REGNO (dst) + offset); diff --git a/gcc/config/sh/sh.h b/gcc/config/sh/sh.h index 7045148ae29..a71ba3cc796 100644 --- a/gcc/config/sh/sh.h +++ b/gcc/config/sh/sh.h @@ -1401,7 +1401,7 @@ extern int current_function_anonymous_args; ((GET_CODE (X) == REG && REG_OK_FOR_INDEX_P (X)) \ || (GET_CODE (X) == SUBREG \ && GET_CODE (SUBREG_REG (X)) == REG \ - && SUBREG_OK_FOR_INDEX_P (SUBREG_REG (X), SUBREG_WORD (X)))) + && SUBREG_OK_FOR_INDEX_P (SUBREG_REG (X), SUBREG_BYTE (X)))) /* Jump to LABEL if X is a valid address RTX. This must also take REG_OK_STRICT into account when deciding about valid registers, but it uses diff --git a/gcc/config/sh/sh.md b/gcc/config/sh/sh.md index 3a03c2d7b41..420c33630a8 100644 --- a/gcc/config/sh/sh.md +++ b/gcc/config/sh/sh.md @@ -2591,7 +2591,7 @@ if (GET_CODE (operands[0]) == REG) regno = REGNO (operands[0]); else if (GET_CODE (operands[0]) == SUBREG) - regno = REGNO (SUBREG_REG (operands[0])) + SUBREG_WORD (operands[0]); + regno = subreg_regno (operands[0]); else if (GET_CODE (operands[0]) == MEM) regno = -1; @@ -2729,7 +2729,7 @@ mem = operands[1]; store_p = 0; } - if (GET_CODE (mem) == SUBREG && SUBREG_WORD (mem) == 0) + if (GET_CODE (mem) == SUBREG && SUBREG_BYTE (mem) == 0) mem = SUBREG_REG (mem); if (GET_CODE (mem) == MEM) { @@ -2751,7 +2751,7 @@ mem = copy_rtx (mem); PUT_MODE (mem, SImode); word0 = alter_subreg (gen_rtx (SUBREG, SImode, regop, 0)); - word1 = alter_subreg (gen_rtx (SUBREG, SImode, regop, 1)); + word1 = alter_subreg (gen_rtx (SUBREG, SImode, regop, 4)); if (store_p || ! refers_to_regno_p (REGNO (word0), REGNO (word0) + 1, addr, 0)) { @@ -2963,7 +2963,7 @@ if (GET_CODE (operands[0]) == REG) regno = REGNO (operands[0]); else if (GET_CODE (operands[0]) == SUBREG) - regno = REGNO (SUBREG_REG (operands[0])) + SUBREG_WORD (operands[0]); + regno = subreg_regno (operands[0]); else if (GET_CODE (operands[0]) == MEM) regno = -1; diff --git a/gcc/config/sparc/sparc.c b/gcc/config/sparc/sparc.c index 9cb4c5ccf09..782d2a725d3 100644 --- a/gcc/config/sparc/sparc.c +++ b/gcc/config/sparc/sparc.c @@ -7494,8 +7494,8 @@ ultra_find_type (type_mask, list, start) && GET_CODE (SET_SRC (pat)) == SUBREG && REGNO (SUBREG_REG (SET_DEST (slot_pat))) == REGNO (SUBREG_REG (SET_SRC (pat))) - && SUBREG_WORD (SET_DEST (slot_pat)) == - SUBREG_WORD (SET_SRC (pat))))) + && SUBREG_BYTE (SET_DEST (slot_pat)) == + SUBREG_BYTE (SET_SRC (pat))))) || (check_fpmode_conflict == 1 && GET_CODE (slot_insn) == INSN && GET_CODE (slot_pat) == SET diff --git a/gcc/config/sparc/sparc.h b/gcc/config/sparc/sparc.h index 9e49eadb02d..d65908eb353 100644 --- a/gcc/config/sparc/sparc.h +++ b/gcc/config/sparc/sparc.h @@ -1146,25 +1146,34 @@ while (0) : (GET_MODE_SIZE (MODE) + 3) / 4) \ : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)) -/* A subreg in 64 bit mode will have the wrong offset for a floating point - register. The least significant part is at offset 1, compared to 0 for - integer registers. This only applies when FMODE is a larger mode. - We also need to handle a special case of TF-->DF conversions. */ -#define ALTER_HARD_SUBREG(TMODE, WORD, FMODE, REGNO) \ - (TARGET_ARCH64 \ - && (REGNO) >= SPARC_FIRST_FP_REG \ - && (REGNO) <= SPARC_LAST_V9_FP_REG \ - && (TMODE) == SImode \ - && !((FMODE) == QImode || (FMODE) == HImode) \ - ? ((REGNO) + 1) \ - : ((TMODE) == DFmode && (FMODE) == TFmode) \ - ? ((REGNO) + ((WORD) * 2)) \ - : ((REGNO) + (WORD))) +/* Due to the ARCH64 descrepancy above we must override these + next two macros too. */ +#define REG_SIZE(R) \ + (TARGET_ARCH64 \ + && ((GET_CODE (R) == REG \ + && ((REGNO (R) >= FIRST_PSEUDO_REGISTER \ + && FLOAT_MODE_P (GET_MODE (R))) \ + || (REGNO (R) < FIRST_PSEUDO_REGISTER \ + && REGNO (R) >= 32))) \ + || (GET_CODE (R) == SUBREG \ + && ((REGNO (SUBREG_REG (R)) >= FIRST_PSEUDO_REGISTER \ + && FLOAT_MODE_P (GET_MODE (SUBREG_REG (R)))) \ + || (REGNO (SUBREG_REG (R)) < FIRST_PSEUDO_REGISTER \ + && REGNO (SUBREG_REG (R)) >= 32)))) \ + ? (GET_MODE_SIZE (GET_MODE (R)) + 3) / 4 \ + : (GET_MODE_SIZE (GET_MODE (R)) + UNITS_PER_WORD - 1) / UNITS_PER_WORD) + +#define REGMODE_NATURAL_SIZE(MODE) \ + ((TARGET_ARCH64 && FLOAT_MODE_P (MODE)) ? 4 : UNITS_PER_WORD) /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE. See sparc.c for how we initialize this. */ extern int *hard_regno_mode_classes; extern int sparc_mode_class[]; + +/* ??? Because of the funny way we pass parameters we should allow certain + ??? types of float/complex values to be in integer registers during + ??? RTL generation. This only matters on arch32. */ #define HARD_REGNO_MODE_OK(REGNO, MODE) \ ((hard_regno_mode_classes[REGNO] & sparc_mode_class[MODE]) != 0) diff --git a/gcc/config/sparc/sparc.md b/gcc/config/sparc/sparc.md index 8167af887ec..cf7ae098196 100644 --- a/gcc/config/sparc/sparc.md +++ b/gcc/config/sparc/sparc.md @@ -4546,15 +4546,17 @@ { rtx temp = gen_reg_rtx (SImode); rtx shift_16 = GEN_INT (16); - int op1_subword = 0; + int op1_subbyte = 0; if (GET_CODE (operand1) == SUBREG) { - op1_subword = SUBREG_WORD (operand1); + op1_subbyte = SUBREG_BYTE (operand1); + op1_subbyte /= GET_MODE_SIZE (SImode); + op1_subbyte *= GET_MODE_SIZE (SImode); operand1 = XEXP (operand1, 0); } - emit_insn (gen_ashlsi3 (temp, gen_rtx_SUBREG (SImode, operand1, op1_subword), + emit_insn (gen_ashlsi3 (temp, gen_rtx_SUBREG (SImode, operand1, op1_subbyte), shift_16)); emit_insn (gen_lshrsi3 (operand0, temp, shift_16)); DONE; @@ -4624,15 +4626,17 @@ { rtx temp = gen_reg_rtx (DImode); rtx shift_48 = GEN_INT (48); - int op1_subword = 0; + int op1_subbyte = 0; if (GET_CODE (operand1) == SUBREG) { - op1_subword = SUBREG_WORD (operand1); + op1_subbyte = SUBREG_BYTE (operand1); + op1_subbyte /= GET_MODE_SIZE (DImode); + op1_subbyte *= GET_MODE_SIZE (DImode); operand1 = XEXP (operand1, 0); } - emit_insn (gen_ashldi3 (temp, gen_rtx_SUBREG (DImode, operand1, op1_subword), + emit_insn (gen_ashldi3 (temp, gen_rtx_SUBREG (DImode, operand1, op1_subbyte), shift_48)); emit_insn (gen_lshrdi3 (operand0, temp, shift_48)); DONE; @@ -4794,7 +4798,7 @@ (define_insn "*cmp_siqi_trunc" [(set (reg:CC 100) - (compare:CC (subreg:QI (match_operand:SI 0 "register_operand" "r") 0) + (compare:CC (subreg:QI (match_operand:SI 0 "register_operand" "r") 3) (const_int 0)))] "" "andcc\\t%0, 0xff, %%g0" @@ -4803,10 +4807,10 @@ (define_insn "*cmp_siqi_trunc_set" [(set (reg:CC 100) - (compare:CC (subreg:QI (match_operand:SI 1 "register_operand" "r") 0) + (compare:CC (subreg:QI (match_operand:SI 1 "register_operand" "r") 3) (const_int 0))) (set (match_operand:QI 0 "register_operand" "=r") - (subreg:QI (match_dup 1) 0))] + (subreg:QI (match_dup 1) 3))] "" "andcc\\t%1, 0xff, %0" [(set_attr "type" "compare") @@ -4814,7 +4818,7 @@ (define_insn "*cmp_diqi_trunc" [(set (reg:CC 100) - (compare:CC (subreg:QI (match_operand:DI 0 "register_operand" "r") 0) + (compare:CC (subreg:QI (match_operand:DI 0 "register_operand" "r") 7) (const_int 0)))] "TARGET_ARCH64" "andcc\\t%0, 0xff, %%g0" @@ -4823,10 +4827,10 @@ (define_insn "*cmp_diqi_trunc_set" [(set (reg:CC 100) - (compare:CC (subreg:QI (match_operand:DI 1 "register_operand" "r") 0) + (compare:CC (subreg:QI (match_operand:DI 1 "register_operand" "r") 7) (const_int 0))) (set (match_operand:QI 0 "register_operand" "=r") - (subreg:QI (match_dup 1) 0))] + (subreg:QI (match_dup 1) 7))] "TARGET_ARCH64" "andcc\\t%1, 0xff, %0" [(set_attr "type" "compare") @@ -4846,15 +4850,17 @@ { rtx temp = gen_reg_rtx (SImode); rtx shift_16 = GEN_INT (16); - int op1_subword = 0; + int op1_subbyte = 0; if (GET_CODE (operand1) == SUBREG) { - op1_subword = SUBREG_WORD (operand1); + op1_subbyte = SUBREG_BYTE (operand1); + op1_subbyte /= GET_MODE_SIZE (SImode); + op1_subbyte *= GET_MODE_SIZE (SImode); operand1 = XEXP (operand1, 0); } - emit_insn (gen_ashlsi3 (temp, gen_rtx_SUBREG (SImode, operand1, op1_subword), + emit_insn (gen_ashlsi3 (temp, gen_rtx_SUBREG (SImode, operand1, op1_subbyte), shift_16)); emit_insn (gen_ashrsi3 (operand0, temp, shift_16)); DONE; @@ -4876,23 +4882,27 @@ { rtx temp = gen_reg_rtx (SImode); rtx shift_24 = GEN_INT (24); - int op1_subword = 0; - int op0_subword = 0; + int op1_subbyte = 0; + int op0_subbyte = 0; if (GET_CODE (operand1) == SUBREG) { - op1_subword = SUBREG_WORD (operand1); + op1_subbyte = SUBREG_BYTE (operand1); + op1_subbyte /= GET_MODE_SIZE (SImode); + op1_subbyte *= GET_MODE_SIZE (SImode); operand1 = XEXP (operand1, 0); } if (GET_CODE (operand0) == SUBREG) { - op0_subword = SUBREG_WORD (operand0); + op0_subbyte = SUBREG_BYTE (operand0); + op0_subbyte /= GET_MODE_SIZE (SImode); + op0_subbyte *= GET_MODE_SIZE (SImode); operand0 = XEXP (operand0, 0); } - emit_insn (gen_ashlsi3 (temp, gen_rtx_SUBREG (SImode, operand1, op1_subword), + emit_insn (gen_ashlsi3 (temp, gen_rtx_SUBREG (SImode, operand1, op1_subbyte), shift_24)); if (GET_MODE (operand0) != SImode) - operand0 = gen_rtx_SUBREG (SImode, operand0, op0_subword); + operand0 = gen_rtx_SUBREG (SImode, operand0, op0_subbyte); emit_insn (gen_ashrsi3 (operand0, temp, shift_24)); DONE; }") @@ -4913,15 +4923,17 @@ { rtx temp = gen_reg_rtx (SImode); rtx shift_24 = GEN_INT (24); - int op1_subword = 0; + int op1_subbyte = 0; if (GET_CODE (operand1) == SUBREG) { - op1_subword = SUBREG_WORD (operand1); + op1_subbyte = SUBREG_BYTE (operand1); + op1_subbyte /= GET_MODE_SIZE (SImode); + op1_subbyte *= GET_MODE_SIZE (SImode); operand1 = XEXP (operand1, 0); } - emit_insn (gen_ashlsi3 (temp, gen_rtx_SUBREG (SImode, operand1, op1_subword), + emit_insn (gen_ashlsi3 (temp, gen_rtx_SUBREG (SImode, operand1, op1_subbyte), shift_24)); emit_insn (gen_ashrsi3 (operand0, temp, shift_24)); DONE; @@ -4943,15 +4955,17 @@ { rtx temp = gen_reg_rtx (DImode); rtx shift_56 = GEN_INT (56); - int op1_subword = 0; + int op1_subbyte = 0; if (GET_CODE (operand1) == SUBREG) { - op1_subword = SUBREG_WORD (operand1); + op1_subbyte = SUBREG_BYTE (operand1); + op1_subbyte /= GET_MODE_SIZE (DImode); + op1_subbyte *= GET_MODE_SIZE (DImode); operand1 = XEXP (operand1, 0); } - emit_insn (gen_ashldi3 (temp, gen_rtx_SUBREG (DImode, operand1, op1_subword), + emit_insn (gen_ashldi3 (temp, gen_rtx_SUBREG (DImode, operand1, op1_subbyte), shift_56)); emit_insn (gen_ashrdi3 (operand0, temp, shift_56)); DONE; @@ -4973,15 +4987,17 @@ { rtx temp = gen_reg_rtx (DImode); rtx shift_48 = GEN_INT (48); - int op1_subword = 0; + int op1_subbyte = 0; if (GET_CODE (operand1) == SUBREG) { - op1_subword = SUBREG_WORD (operand1); + op1_subbyte = SUBREG_BYTE (operand1); + op1_subbyte /= GET_MODE_SIZE (DImode); + op1_subbyte *= GET_MODE_SIZE (DImode); operand1 = XEXP (operand1, 0); } - emit_insn (gen_ashldi3 (temp, gen_rtx_SUBREG (DImode, operand1, op1_subword), + emit_insn (gen_ashldi3 (temp, gen_rtx_SUBREG (DImode, operand1, op1_subbyte), shift_48)); emit_insn (gen_ashrdi3 (operand0, temp, shift_48)); DONE; @@ -6275,7 +6291,7 @@ (mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "r,r")) (sign_extend:DI (match_operand:SI 2 "register_operand" "r,r"))) (match_operand:SI 3 "const_int_operand" "i,i")) - 1)) + 4)) (clobber (match_scratch:SI 4 "=X,&h"))] "TARGET_V8PLUS" "@ @@ -8346,7 +8362,7 @@ (define_insn "" [(set (match_operand:SI 0 "register_operand" "=r") (ashiftrt:SI (subreg:SI (lshiftrt:DI (match_operand:DI 1 "register_operand" "r") - (const_int 32)) 0) + (const_int 32)) 4) (match_operand:SI 2 "small_int_or_double" "n")))] "TARGET_ARCH64 && ((GET_CODE (operands[2]) == CONST_INT @@ -8366,7 +8382,7 @@ (define_insn "" [(set (match_operand:SI 0 "register_operand" "=r") (lshiftrt:SI (subreg:SI (ashiftrt:DI (match_operand:DI 1 "register_operand" "r") - (const_int 32)) 0) + (const_int 32)) 4) (match_operand:SI 2 "small_int_or_double" "n")))] "TARGET_ARCH64 && ((GET_CODE (operands[2]) == CONST_INT @@ -8386,7 +8402,7 @@ (define_insn "" [(set (match_operand:SI 0 "register_operand" "=r") (ashiftrt:SI (subreg:SI (ashiftrt:DI (match_operand:DI 1 "register_operand" "r") - (match_operand:SI 2 "small_int_or_double" "n")) 0) + (match_operand:SI 2 "small_int_or_double" "n")) 4) (match_operand:SI 3 "small_int_or_double" "n")))] "TARGET_ARCH64 && GET_CODE (operands[2]) == CONST_INT && GET_CODE (operands[3]) == CONST_INT @@ -8405,7 +8421,7 @@ (define_insn "" [(set (match_operand:SI 0 "register_operand" "=r") (lshiftrt:SI (subreg:SI (lshiftrt:DI (match_operand:DI 1 "register_operand" "r") - (match_operand:SI 2 "small_int_or_double" "n")) 0) + (match_operand:SI 2 "small_int_or_double" "n")) 4) (match_operand:SI 3 "small_int_or_double" "n")))] "TARGET_ARCH64 && GET_CODE (operands[2]) == CONST_INT && GET_CODE (operands[3]) == CONST_INT diff --git a/gcc/config/v850/v850.c b/gcc/config/v850/v850.c index 34369d46325..a074d953604 100644 --- a/gcc/config/v850/v850.c +++ b/gcc/config/v850/v850.c @@ -541,7 +541,7 @@ print_operand (file, x, code) fputs (reg_names[REGNO (x)], file); break; case SUBREG: - fputs (reg_names[REGNO (SUBREG_REG (x)) + SUBREG_WORD (x)], file); + fputs (reg_names[subreg_regno (x)], file); break; case CONST_INT: case SYMBOL_REF: @@ -823,7 +823,7 @@ output_move_double (operands) if (GET_CODE (inside) == REG) ptrreg = REGNO (inside); else if (GET_CODE (inside) == SUBREG) - ptrreg = REGNO (SUBREG_REG (inside)) + SUBREG_WORD (inside); + ptrreg = subreg_regno (inside); else if (GET_CODE (inside) == PLUS) ptrreg = REGNO (XEXP (inside, 0)); else if (GET_CODE (inside) == LO_SUM) |