diff options
Diffstat (limited to 'gcc/config')
| -rw-r--r-- | gcc/config/bfin/bfin.c | 4 | ||||
| -rw-r--r-- | gcc/config/bfin/bfin.md | 22 |
2 files changed, 15 insertions, 11 deletions
diff --git a/gcc/config/bfin/bfin.c b/gcc/config/bfin/bfin.c index 72fc42383ee..22fdfb79b15 100644 --- a/gcc/config/bfin/bfin.c +++ b/gcc/config/bfin/bfin.c @@ -5879,11 +5879,11 @@ static const struct builtin_description bdesc_1arg[] = { CODE_FOR_ones, "__builtin_bfin_ones", BFIN_BUILTIN_ONES, 0 }, - { CODE_FOR_signbitshi2, "__builtin_bfin_norm_fr1x16", BFIN_BUILTIN_NORM_1X16, 0 }, + { CODE_FOR_clrsbhi2, "__builtin_bfin_norm_fr1x16", BFIN_BUILTIN_NORM_1X16, 0 }, { CODE_FOR_ssneghi2, "__builtin_bfin_negate_fr1x16", BFIN_BUILTIN_NEG_1X16, 0 }, { CODE_FOR_abshi2, "__builtin_bfin_abs_fr1x16", BFIN_BUILTIN_ABS_1X16, 0 }, - { CODE_FOR_signbitssi2, "__builtin_bfin_norm_fr1x32", BFIN_BUILTIN_NORM_1X32, 0 }, + { CODE_FOR_clrsbsi2, "__builtin_bfin_norm_fr1x32", BFIN_BUILTIN_NORM_1X32, 0 }, { CODE_FOR_ssroundsi2, "__builtin_bfin_round_fr1x32", BFIN_BUILTIN_ROUND_1X32, 0 }, { CODE_FOR_ssnegsi2, "__builtin_bfin_negate_fr1x32", BFIN_BUILTIN_NEG_1X32, 0 }, { CODE_FOR_ssabssi2, "__builtin_bfin_abs_fr1x32", BFIN_BUILTIN_ABS_1X32, 0 }, diff --git a/gcc/config/bfin/bfin.md b/gcc/config/bfin/bfin.md index 903c8bb076f..a96d1a7bda6 100644 --- a/gcc/config/bfin/bfin.md +++ b/gcc/config/bfin/bfin.md @@ -1461,12 +1461,19 @@ "%0 = ~%1;" [(set_attr "type" "alu0")]) +(define_expand "clrsbsi2" + [(set (match_dup 2) + (clrsb:HI (match_operand:SI 1 "register_operand" "d"))) + (set (match_operand:SI 0 "register_operand") + (zero_extend:SI (match_dup 2)))] + "" +{ + operands[2] = gen_reg_rtx (HImode); +}) + (define_insn "signbitssi2" [(set (match_operand:HI 0 "register_operand" "=d") - (if_then_else:HI - (lt (match_operand:SI 1 "register_operand" "d") (const_int 0)) - (clz:HI (not:SI (match_dup 1))) - (clz:HI (match_dup 1))))] + (clrsb:HI (match_operand:SI 1 "register_operand" "d")))] "" "%h0 = signbits %1%!" [(set_attr "type" "dsp32")]) @@ -1518,12 +1525,9 @@ "%0 = -%1 (V)%!" [(set_attr "type" "dsp32")]) -(define_insn "signbitshi2" +(define_insn "clrsbhi2" [(set (match_operand:HI 0 "register_operand" "=d") - (if_then_else:HI - (lt (match_operand:HI 1 "register_operand" "d") (const_int 0)) - (clz:HI (not:HI (match_dup 1))) - (clz:HI (match_dup 1))))] + (clrsb:HI (match_operand:HI 1 "register_operand" "d")))] "" "%h0 = signbits %h1%!" [(set_attr "type" "dsp32")]) |