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-rw-r--r--gcc/config/bpf/bpf.md7
-rw-r--r--gcc/config/i386/sse.md2
-rw-r--r--gcc/config/pa/pa.c33
-rw-r--r--gcc/config/pa/pa.md140
4 files changed, 147 insertions, 35 deletions
diff --git a/gcc/config/bpf/bpf.md b/gcc/config/bpf/bpf.md
index 41bb4fcd9a7..769d8ea0096 100644
--- a/gcc/config/bpf/bpf.md
+++ b/gcc/config/bpf/bpf.md
@@ -82,10 +82,15 @@
;;;; NOPs
+;; The Linux kernel verifier performs some optimizations that rely on
+;; nop instructions to be encoded as `ja 0', i.e. a jump to offset 0,
+;; which actually means to jump to the next instruction, since in BPF
+;; offsets are expressed in 64-bit words _minus one_.
+
(define_insn "nop"
[(const_int 0)]
""
- "mov\t%%r0,%%r0"
+ "ja\t0"
[(set_attr "type" "alu")])
;;;; Arithmetic/Logical
diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md
index b8c2ca7ec04..eb6a906c8b2 100644
--- a/gcc/config/i386/sse.md
+++ b/gcc/config/i386/sse.md
@@ -22985,7 +22985,7 @@
(match_operand:MASK_DWI 1 "nonimmediate_operand"))]
"TARGET_AVX512VP2INTERSECT"
{
- if (MEM_P (operands[1]) && MEM_P (operands[2]))
+ if (MEM_P (operands[0]) && MEM_P (operands[1]))
operands[1] = force_reg (<MODE>mode, operands[1]);
})
diff --git a/gcc/config/pa/pa.c b/gcc/config/pa/pa.c
index 55185aab650..2461f2ed716 100644
--- a/gcc/config/pa/pa.c
+++ b/gcc/config/pa/pa.c
@@ -1630,13 +1630,16 @@ hppa_rtx_costs (rtx x, machine_mode mode, int outer_code,
case ASHIFT:
if (mode == DImode)
{
- if (TARGET_64BIT)
- *total = COSTS_N_INSNS (3);
- else if (REG_P (XEXP (x, 0)) && CONST_INT_P (XEXP (x, 1)))
+ if (REG_P (XEXP (x, 0)) && CONST_INT_P (XEXP (x, 1)))
{
- *total = COSTS_N_INSNS (2);
+ if (TARGET_64BIT)
+ *total = COSTS_N_INSNS (1);
+ else
+ *total = COSTS_N_INSNS (2);
return true;
}
+ else if (TARGET_64BIT)
+ *total = COSTS_N_INSNS (3);
else if (speed)
*total = COSTS_N_INSNS (13);
else
@@ -1653,13 +1656,16 @@ hppa_rtx_costs (rtx x, machine_mode mode, int outer_code,
case ASHIFTRT:
if (mode == DImode)
{
- if (TARGET_64BIT)
- *total = COSTS_N_INSNS (3);
- else if (REG_P (XEXP (x, 0)) && CONST_INT_P (XEXP (x, 1)))
+ if (REG_P (XEXP (x, 0)) && CONST_INT_P (XEXP (x, 1)))
{
- *total = COSTS_N_INSNS (2);
+ if (TARGET_64BIT)
+ *total = COSTS_N_INSNS (1);
+ else
+ *total = COSTS_N_INSNS (2);
return true;
}
+ else if (TARGET_64BIT)
+ *total = COSTS_N_INSNS (3);
else if (speed)
*total = COSTS_N_INSNS (14);
else
@@ -1676,13 +1682,16 @@ hppa_rtx_costs (rtx x, machine_mode mode, int outer_code,
case LSHIFTRT:
if (mode == DImode)
{
- if (TARGET_64BIT)
- *total = COSTS_N_INSNS (2);
- else if (REG_P (XEXP (x, 0)) && CONST_INT_P (XEXP (x, 1)))
+ if (REG_P (XEXP (x, 0)) && CONST_INT_P (XEXP (x, 1)))
{
- *total = COSTS_N_INSNS (2);
+ if (TARGET_64BIT)
+ *total = COSTS_N_INSNS (1);
+ else
+ *total = COSTS_N_INSNS (2);
return true;
}
+ else if (TARGET_64BIT)
+ *total = COSTS_N_INSNS (2);
else if (speed)
*total = COSTS_N_INSNS (12);
else
diff --git a/gcc/config/pa/pa.md b/gcc/config/pa/pa.md
index 713ff175445..3a82fac85e3 100644
--- a/gcc/config/pa/pa.md
+++ b/gcc/config/pa/pa.md
@@ -6627,32 +6627,82 @@
(set_attr "length" "4")])
; Shift right pair word 0 to 31 bits.
-(define_insn "shrpsi4"
- [(set (match_operand:SI 0 "register_operand" "=r,r")
- (ior:SI (ashift:SI (match_operand:SI 1 "register_operand" "r,r")
- (minus:SI (const_int 32)
- (match_operand:SI 3 "shift5_operand" "q,n")))
- (lshiftrt:SI (match_operand:SI 2 "register_operand" "r,r")
- (match_dup 3))))]
+(define_insn "*shrpsi4_1"
+ [(set (match_operand:SI 0 "register_operand" "=r")
+ (match_operator:SI 4 "plus_xor_ior_operator"
+ [(ashift:SI (match_operand:SI 1 "register_operand" "r")
+ (minus:SI (const_int 32)
+ (match_operand:SI 3 "register_operand" "q")))
+ (lshiftrt:SI (match_operand:SI 2 "register_operand" "r")
+ (match_dup 3))]))]
""
- "@
- {vshd %1,%2,%0|shrpw %1,%2,%%sar,%0}
- {shd|shrpw} %1,%2,%3,%0"
+ "{vshd %1,%2,%0|shrpw %1,%2,%%sar,%0}"
+ [(set_attr "type" "shift")
+ (set_attr "length" "4")])
+
+(define_insn "*shrpsi4_2"
+ [(set (match_operand:SI 0 "register_operand" "=r")
+ (match_operator:SI 4 "plus_xor_ior_operator"
+ [(lshiftrt:SI (match_operand:SI 2 "register_operand" "r")
+ (match_operand:SI 3 "register_operand" "q"))
+ (ashift:SI (match_operand:SI 1 "register_operand" "r")
+ (minus:SI (const_int 32)
+ (match_dup 3)))]))]
+ ""
+ "{vshd %1,%2,%0|shrpw %1,%2,%%sar,%0}"
[(set_attr "type" "shift")
(set_attr "length" "4")])
; Shift right pair doubleword 0 to 63 bits.
-(define_insn "shrpdi4"
- [(set (match_operand:DI 0 "register_operand" "=r,r")
- (ior:DI (ashift:DI (match_operand:SI 1 "register_operand" "r,r")
- (minus:DI (const_int 64)
- (match_operand:DI 3 "shift6_operand" "q,n")))
- (lshiftrt:DI (match_operand:DI 2 "register_operand" "r,r")
- (match_dup 3))))]
+(define_insn "*shrpdi4_1"
+ [(set (match_operand:DI 0 "register_operand" "=r")
+ (match_operator:DI 4 "plus_xor_ior_operator"
+ [(ashift:DI (match_operand:DI 1 "register_operand" "r")
+ (minus:DI (const_int 64)
+ (match_operand:DI 3 "register_operand" "q")))
+ (lshiftrt:DI (match_operand:DI 2 "register_operand" "r")
+ (match_dup 3))]))]
"TARGET_64BIT"
- "@
- shrpd %1,%2,%%sar,%0
- shrpd %1,%2,%3,%0"
+ "shrpd %1,%2,%%sar,%0"
+ [(set_attr "type" "shift")
+ (set_attr "length" "4")])
+
+(define_insn "*shrpdi4_2"
+ [(set (match_operand:DI 0 "register_operand" "=r")
+ (match_operator:DI 4 "plus_xor_ior_operator"
+ [(lshiftrt:DI (match_operand:DI 2 "register_operand" "r")
+ (match_operand:DI 3 "shift6_operand" "q"))
+ (ashift:DI (match_operand:SI 1 "register_operand" "r")
+ (minus:DI (const_int 64)
+ (match_dup 3)))]))]
+ "TARGET_64BIT"
+ "shrpd %1,%2,%%sar,%0"
+ [(set_attr "type" "shift")
+ (set_attr "length" "4")])
+
+(define_insn "*shrpdi4_3"
+ [(set (match_operand:DI 0 "register_operand" "=r")
+ (match_operator:DI 5 "plus_xor_ior_operator"
+ [(ashift:DI (match_operand:DI 1 "register_operand" "r")
+ (match_operand:DI 3 "const_int_operand" "n"))
+ (lshiftrt:DI (match_operand:DI 2 "register_operand" "r")
+ (match_operand:DI 4 "const_int_operand" "n"))]))]
+ "TARGET_64BIT
+ && INTVAL (operands[3]) + INTVAL (operands[4]) == 64"
+ "shrpd %1,%2,%4,%0"
+ [(set_attr "type" "shift")
+ (set_attr "length" "4")])
+
+(define_insn "*shrpdi4_4"
+ [(set (match_operand:DI 0 "register_operand" "=r")
+ (match_operator:DI 5 "plus_xor_ior_operator"
+ [(lshiftrt:DI (match_operand:DI 2 "register_operand" "r")
+ (match_operand:DI 4 "const_int_operand" "n"))
+ (ashift:DI (match_operand:DI 1 "register_operand" "r")
+ (match_operand:DI 3 "const_int_operand" "n"))]))]
+ "TARGET_64BIT
+ && INTVAL (operands[3]) + INTVAL (operands[4]) == 64"
+ "shrpd %1,%2,%4,%0"
[(set_attr "type" "shift")
(set_attr "length" "4")])
@@ -6691,7 +6741,7 @@
/* Else expand normally. */
}")
-(define_insn ""
+(define_insn "*rotlsi3_internal"
[(set (match_operand:SI 0 "register_operand" "=r")
(rotate:SI (match_operand:SI 1 "register_operand" "r")
(match_operand:SI 2 "const_int_operand" "n")))]
@@ -6704,6 +6754,54 @@
[(set_attr "type" "shift")
(set_attr "length" "4")])
+(define_insn "rotrdi3"
+ [(set (match_operand:DI 0 "register_operand" "=r,r")
+ (rotatert:DI (match_operand:DI 1 "register_operand" "r,r")
+ (match_operand:DI 2 "shift6_operand" "q,n")))]
+ "TARGET_64BIT"
+ "*
+{
+ if (GET_CODE (operands[2]) == CONST_INT)
+ {
+ operands[2] = GEN_INT (INTVAL (operands[2]) & 63);
+ return \"shrpd %1,%1,%2,%0\";
+ }
+ else
+ return \"shrpd %1,%1,%%sar,%0\";
+}"
+ [(set_attr "type" "shift")
+ (set_attr "length" "4")])
+
+(define_expand "rotldi3"
+ [(set (match_operand:DI 0 "register_operand" "")
+ (rotate:DI (match_operand:DI 1 "register_operand" "")
+ (match_operand:DI 2 "arith32_operand" "")))]
+ "TARGET_64BIT"
+ "
+{
+ if (GET_CODE (operands[2]) != CONST_INT)
+ {
+ rtx temp = gen_reg_rtx (DImode);
+ emit_insn (gen_subdi3 (temp, GEN_INT (64), operands[2]));
+ emit_insn (gen_rotrdi3 (operands[0], operands[1], temp));
+ DONE;
+ }
+ /* Else expand normally. */
+}")
+
+(define_insn "*rotldi3_internal"
+ [(set (match_operand:DI 0 "register_operand" "=r")
+ (rotate:DI (match_operand:DI 1 "register_operand" "r")
+ (match_operand:DI 2 "const_int_operand" "n")))]
+ "TARGET_64BIT"
+ "*
+{
+ operands[2] = GEN_INT ((64 - INTVAL (operands[2])) & 63);
+ return \"shrpd %1,%1,%2,%0\";
+}"
+ [(set_attr "type" "shift")
+ (set_attr "length" "4")])
+
(define_insn ""
[(set (match_operand:SI 0 "register_operand" "=r")
(match_operator:SI 5 "plus_xor_ior_operator"
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