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-rw-r--r--gcc/config/sh/sh.c4
1 files changed, 2 insertions, 2 deletions
diff --git a/gcc/config/sh/sh.c b/gcc/config/sh/sh.c
index 08ee5b436f5..048a7549739 100644
--- a/gcc/config/sh/sh.c
+++ b/gcc/config/sh/sh.c
@@ -393,7 +393,7 @@ static const struct attribute_spec sh_attribute_table[] =
The insn that frees registers is most likely to be the insn with lowest
LUID (original insn order); but such an insn might be there in the stalled
queue (Q) instead of the ready queue (R). To solve this, we skip cycles
- upto a max of 8 cycles so that such insns may move from Q -> R.
+ up to a max of 8 cycles so that such insns may move from Q -> R.
The description of the hooks are as below:
@@ -11478,7 +11478,7 @@ sh_expand_binop_v2sf (enum rtx_code code, rtx op0, rtx op1, rtx op2)
We could hold SFmode / SCmode values in XD registers, but that
would require a tertiary reload when reloading from / to memory,
and a secondary reload to reload from / to general regs; that
- seems to be a loosing proposition.
+ seems to be a losing proposition.
We want to allow TImode FP regs so that when V4SFmode is loaded as TImode,
it won't be ferried through GP registers first. */