diff options
Diffstat (limited to 'gcc/config/rs6000/rs6000.md')
| -rw-r--r-- | gcc/config/rs6000/rs6000.md | 20 |
1 files changed, 19 insertions, 1 deletions
diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md index 8ddf26d924d..f40e78dfafa 100644 --- a/gcc/config/rs6000/rs6000.md +++ b/gcc/config/rs6000/rs6000.md @@ -106,9 +106,26 @@ ;; Processor type -- this attribute must exactly match the processor_type ;; enumeration in rs6000.h. -(define_attr "cpu" "rios1,rios2,rs64a,mpccore,ppc403,ppc405,ppc440,ppc601,ppc603,ppc604,ppc604e,ppc620,ppc630,ppc750,ppc7400,ppc7450,ppc8540,power4,power5,power6" +(define_attr "cpu" "rios1,rios2,rs64a,mpccore,ppc403,ppc405,ppc440,ppc601,ppc603,ppc604,ppc604e,ppc620,ppc630,ppc750,ppc7400,ppc7450,ppc8540,power4,power5,power6,cell" (const (symbol_ref "rs6000_cpu_attr"))) + +;; If this instruction is microcoded on the CELL processor +; The default for load and stores is conditional +; The default for load extended and the recorded instructions is always microcoded +(define_attr "cell_micro" "not,conditional,always" + (if_then_else (ior (ior (eq_attr "type" "load") + (eq_attr "type" "store")) + (ior (eq_attr "type" "fpload") + (eq_attr "type" "fpstore"))) + (const_string "conditional") + (if_then_else (ior (eq_attr "type" "load_ext") + (ior (eq_attr "type" "compare") + (eq_attr "type" "delayed_compare"))) + (const_string "always") + (const_string "not")))) + + (automata_option "ndfa") (include "rios1.md") @@ -125,6 +142,7 @@ (include "power4.md") (include "power5.md") (include "power6.md") +(include "cell.md") (include "predicates.md") (include "constraints.md") |