diff options
Diffstat (limited to 'gcc/config/rs6000/rs6000.md')
| -rw-r--r-- | gcc/config/rs6000/rs6000.md | 81 |
1 files changed, 41 insertions, 40 deletions
diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md index 9a3907993ba..bb31e41e256 100644 --- a/gcc/config/rs6000/rs6000.md +++ b/gcc/config/rs6000/rs6000.md @@ -183,6 +183,7 @@ brinc, vecsimple,veccomplex,vecdiv,veccmp,veccmpsimple,vecperm, vecfloat,vecfdiv,vecdouble,mffgpr,mftgpr,crypto, + veclogical,veccmpfx,vecexts,vecmove, htm" (const_string "integer")) @@ -4354,7 +4355,7 @@ "@ fabs %0,%1 xsabsdp %x0,%x1" - [(set_attr "type" "fp") + [(set_attr "type" "fpsimple") (set_attr "fp_type" "fp_addsub_<Fs>")]) (define_insn "*nabs<mode>2_fpr" @@ -4366,7 +4367,7 @@ "@ fnabs %0,%1 xsnabsdp %x0,%x1" - [(set_attr "type" "fp") + [(set_attr "type" "fpsimple") (set_attr "fp_type" "fp_addsub_<Fs>")]) (define_expand "neg<mode>2" @@ -4382,7 +4383,7 @@ "@ fneg %0,%1 xsnegdp %x0,%x1" - [(set_attr "type" "fp") + [(set_attr "type" "fpsimple") (set_attr "fp_type" "fp_addsub_<Fs>")]) (define_expand "add<mode>3" @@ -4543,7 +4544,7 @@ emit_note (NOTE_INSN_DELETED); DONE; } - [(set_attr "type" "fp,fp,fpload,fp,fp,fpload,fpload")]) + [(set_attr "type" "fp,fpsimple,fpload,fp,fpsimple,fpload,fpload")]) (define_expand "truncdfsf2" [(set (match_operand:SF 0 "gpc_reg_operand" "") @@ -4633,7 +4634,7 @@ "@ fcpsgn %0,%2,%1 xscpsgndp %x0,%x2,%x1" - [(set_attr "type" "fp")]) + [(set_attr "type" "fpsimple")]) ;; For MIN, MAX, and conditional move, we use DEFINE_EXPAND's that involve a ;; fsel instruction and some auxiliary computations. Then we just have a @@ -4846,7 +4847,7 @@ (match_operand:SFDF 4 "vsx_register_operand" "<Fv>")))] "TARGET_P9_MINMAX" "xxsel %x0,%x1,%x3,%x4" - [(set_attr "type" "vecperm")]) + [(set_attr "type" "vecmove")]) ;; Conversions to and from floating-point. @@ -6092,7 +6093,7 @@ [(set (attr "type") (if_then_else (match_test "vsx_register_operand (operands[0], <MODE>mode)") - (const_string "vecsimple") + (const_string "veclogical") (const_string "integer"))) (set (attr "length") (if_then_else @@ -6128,7 +6129,7 @@ [(set (attr "type") (if_then_else (match_test "vsx_register_operand (operands[0], <MODE>mode)") - (const_string "vecsimple") + (const_string "veclogical") (const_string "integer"))) (set (attr "length") (if_then_else @@ -6166,7 +6167,7 @@ [(set (attr "type") (if_then_else (match_test "vsx_register_operand (operands[0], <MODE>mode)") - (const_string "vecsimple") + (const_string "veclogical") (const_string "integer"))) (set (attr "length") (if_then_else @@ -6226,7 +6227,7 @@ [(set (attr "type") (if_then_else (match_test "vsx_register_operand (operands[0], <MODE>mode)") - (const_string "vecsimple") + (const_string "veclogical") (const_string "integer"))) (set (attr "length") (if_then_else @@ -6284,7 +6285,7 @@ [(set (attr "type") (if_then_else (match_test "vsx_register_operand (operands[0], <MODE>mode)") - (const_string "vecsimple") + (const_string "veclogical") (const_string "integer"))) (set (attr "length") (if_then_else @@ -6340,7 +6341,7 @@ [(set (attr "type") (if_then_else (match_test "vsx_register_operand (operands[0], <MODE>mode)") - (const_string "vecsimple") + (const_string "veclogical") (const_string "integer"))) (set (attr "length") (if_then_else @@ -6655,7 +6656,7 @@ mt%0 %1 mf%1 %0 nop" - [(set_attr "type" "*,load,store,fp,fp,vecsimple,integer,fpload,fpload,fpstore,fpstore,fpload,fpstore,mffgpr,mftgpr,mtjmpr,mfjmpr,*") + [(set_attr "type" "*,load,store,fpsimple,fpsimple,veclogical,integer,fpload,fpload,fpstore,fpstore,fpload,fpstore,mffgpr,mftgpr,mtjmpr,mfjmpr,*") (set_attr "length" "4")]) (define_insn "*mov<mode>_softfloat" @@ -6790,7 +6791,7 @@ # # #" - [(set_attr "type" "fpstore,fpload,fp,fpload,fpstore,fpload,fpstore,vecsimple,vecsimple,two,store,load,two") + [(set_attr "type" "fpstore,fpload,fpsimple,fpload,fpstore,fpload,fpstore,veclogical,veclogical,two,store,load,two") (set_attr "length" "4,4,4,4,4,4,4,4,4,8,8,8,8")]) (define_insn "*mov<mode>_softfloat32" @@ -6835,7 +6836,7 @@ mffgpr %0,%1 mfvsrd %0,%x1 mtvsrd %x0,%1" - [(set_attr "type" "fpstore,fpload,fp,fpload,fpstore,fpload,fpstore,vecsimple,vecsimple,integer,store,load,*,mtjmpr,mfjmpr,*,mftgpr,mffgpr,mftgpr,mffgpr") + [(set_attr "type" "fpstore,fpload,fpsimple,fpload,fpstore,fpload,fpstore,veclogical,veclogical,integer,store,load,*,mtjmpr,mfjmpr,*,mftgpr,mffgpr,mftgpr,mffgpr") (set_attr "length" "4")]) (define_insn "*mov<mode>_softfloat64" @@ -7046,7 +7047,7 @@ emit_note (NOTE_INSN_DELETED); DONE; } - [(set_attr "type" "fp")]) + [(set_attr "type" "fpsimple")]) (define_insn "trunc<mode>df2_internal2" [(set (match_operand:DF 0 "gpc_reg_operand" "=d") @@ -7279,7 +7280,7 @@ else return \"fneg %0,%1\;fneg %L0,%L1\"; }" - [(set_attr "type" "fp") + [(set_attr "type" "fpsimple") (set_attr "length" "8")]) (define_expand "abs<mode>2" @@ -7414,7 +7415,7 @@ (use (match_operand:V16QI 2 "register_operand" "v"))] "TARGET_FLOAT128 && !TARGET_FLOAT128_HW" "xxlxor %x0,%x1,%x2" - [(set_attr "type" "vecsimple")]) + [(set_attr "type" "veclogical")]) ;; IEEE 128-bit absolute value (define_insn_and_split "ieee_128bit_vsx_abs<mode>2" @@ -7443,7 +7444,7 @@ (use (match_operand:V16QI 2 "register_operand" "v"))] "TARGET_FLOAT128 && !TARGET_FLOAT128_HW" "xxlandc %x0,%x1,%x2" - [(set_attr "type" "vecsimple")]) + [(set_attr "type" "veclogical")]) ;; IEEE 128-bit negative absolute value (define_insn_and_split "*ieee_128bit_vsx_nabs<mode>2" @@ -7476,7 +7477,7 @@ (use (match_operand:V16QI 2 "register_operand" "v"))] "TARGET_FLOAT128 && !TARGET_FLOAT128_HW" "xxlor %x0,%x1,%x2" - [(set_attr "type" "vecsimple")]) + [(set_attr "type" "veclogical")]) ;; Float128 conversion functions. These expand to library function calls. ;; We use expand to convert from IBM double double to IEEE 128-bit @@ -7632,7 +7633,7 @@ UNSPEC_P8V_FMRGOW))] "!TARGET_POWERPC64 && TARGET_DIRECT_MOVE" "fmrgow %0,%1,%2" - [(set_attr "type" "vecperm")]) + [(set_attr "type" "fpsimple")]) (define_insn "p8_mtvsrwz" [(set (match_operand:DF 0 "register_operand" "=d") @@ -7884,9 +7885,9 @@ # #" [(set_attr "type" - "store, load, *, fpstore, fpload, fp, - *, fpstore, fpstore, fpload, fpload, vecsimple, - vecsimple, vecsimple, vecsimple, vecsimple, vecsimple, vecsimple, + "store, load, *, fpstore, fpload, fpsimple, + *, fpstore, fpstore, fpload, fpload, veclogical, + vecsimple, vecsimple, vecsimple, veclogical, veclogical, vecsimple, vecsimple")]) (define_split @@ -7970,11 +7971,11 @@ mfvsrd %0,%x1 mtvsrd %x0,%1" [(set_attr "type" - "store, load, *, *, *, *, - fpstore, fpload, fp, fpstore, fpstore, fpload, - fpload, vecsimple, vecsimple, vecsimple, vecsimple, vecsimple, - vecsimple, vecsimple, vecsimple, mfjmpr, mtjmpr, *, - mftgpr, mffgpr, mftgpr, mffgpr") + "store, load, *, *, *, *, + fpstore, fpload, fpsimple, fpstore, fpstore, fpload, + fpload, veclogical, vecsimple, vecsimple, vecsimple, veclogical, + veclogical, vecsimple, vecsimple, mfjmpr, mtjmpr, *, + mftgpr, mffgpr, mftgpr, mffgpr") (set_attr "length" "4, 4, 4, 4, 4, 20, @@ -13391,7 +13392,7 @@ operands[3] = gen_rtx_REG (<FP128_64>mode, dest_hi); operands[4] = gen_rtx_REG (<FP128_64>mode, dest_lo); } - [(set_attr "type" "fp,fp") + [(set_attr "type" "fpsimple,fp") (set_attr "length" "4,8")]) (define_insn "unpack<mode>" @@ -13493,7 +13494,7 @@ UNSPEC_COPYSIGN))] "TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<MODE>mode)" "xscpsgnqp %0,%2,%1" - [(set_attr "type" "vecsimple")]) + [(set_attr "type" "vecmove")]) (define_insn "copysign<mode>3_soft" [(set (match_operand:IEEE128 0 "altivec_register_operand" "=v") @@ -13513,7 +13514,7 @@ (match_operand:IEEE128 1 "altivec_register_operand" "v")))] "TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<MODE>mode)" "xsnegqp %0,%1" - [(set_attr "type" "vecfloat")]) + [(set_attr "type" "vecmove")]) (define_insn "abs<mode>2_hw" @@ -13522,7 +13523,7 @@ (match_operand:IEEE128 1 "altivec_register_operand" "v")))] "TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<MODE>mode)" "xsabsqp %0,%1" - [(set_attr "type" "vecfloat")]) + [(set_attr "type" "vecmove")]) (define_insn "*nabs<mode>2_hw" @@ -13532,7 +13533,7 @@ (match_operand:IEEE128 1 "altivec_register_operand" "v"))))] "TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<MODE>mode)" "xsnabsqp %0,%1" - [(set_attr "type" "vecfloat")]) + [(set_attr "type" "vecmove")]) ;; Initially don't worry about doing fusion (define_insn "*fma<mode>4_hw" @@ -13602,7 +13603,7 @@ emit_note (NOTE_INSN_DELETED); DONE; } - [(set_attr "type" "*,vecsimple") + [(set_attr "type" "*,veclogical") (set_attr "length" "0,4")]) (define_insn_and_split "trunctfkf2" @@ -13618,7 +13619,7 @@ emit_note (NOTE_INSN_DELETED); DONE; } - [(set_attr "type" "*,vecsimple") + [(set_attr "type" "*,veclogical") (set_attr "length" "0,4")]) (define_insn "trunc<mode>df2_hw" @@ -13754,7 +13755,7 @@ mfvsrd %0,%x1 stxsdx %x1,%y0 xxlor %x0,%x1,%x1" - [(set_attr "type" "mftgpr,fpstore,vecsimple")]) + [(set_attr "type" "mftgpr,fpstore,veclogical")]) (define_insn "*ieee128_mfvsrd_32bit" @@ -13765,7 +13766,7 @@ "@ stxsdx %x1,%y0 xxlor %x0,%x1,%x1" - [(set_attr "type" "fpstore,vecsimple")]) + [(set_attr "type" "fpstore,veclogical")]) (define_insn "*ieee128_mfvsrwz" [(set (match_operand:SI 0 "reg_or_indexed_operand" "=r,Z") @@ -13801,7 +13802,7 @@ mtvsrd %x0,%1 lxsdx %x0,%y1 xxlor %x0,%x1,%x1" - [(set_attr "type" "mffgpr,fpload,vecsimple")]) + [(set_attr "type" "mffgpr,fpload,veclogical")]) (define_insn "*ieee128_mtvsrd_32bit" [(set (match_operand:V2DI 0 "altivec_register_operand" "=v,v") @@ -13811,7 +13812,7 @@ "@ lxsdx %x0,%y1 xxlor %x0,%x1,%x1" - [(set_attr "type" "fpload,vecsimple")]) + [(set_attr "type" "fpload,veclogical")]) ;; IEEE 128-bit instructions with round to odd semantics (define_insn "*trunc<mode>df2_odd" |