diff options
Diffstat (limited to 'gcc/config/pdp11/pdp11.md')
| -rw-r--r-- | gcc/config/pdp11/pdp11.md | 229 |
1 files changed, 102 insertions, 127 deletions
diff --git a/gcc/config/pdp11/pdp11.md b/gcc/config/pdp11/pdp11.md index 53097b75a77..2f73390a501 100644 --- a/gcc/config/pdp11/pdp11.md +++ b/gcc/config/pdp11/pdp11.md @@ -25,6 +25,7 @@ (define_constants [ ;; Register numbers + (RETVAL_REGNUM 0) (FRAME_POINTER_REGNUM 5) (STACK_POINTER_REGNUM 6) (PC_REGNUM 7) @@ -42,6 +43,11 @@ ;; HI is 16 bit ;; QI is 8 bit +;; Integer modes supported on the PDP11, with a mapping from machine mode +;; to mnemonic suffix. SImode and DImode always are special cases. +(define_mode_iterator PDPint [QI HI]) +(define_mode_attr isfx [(QI "b") (HI "")]) + ;;- See file "rtl.def" for documentation on define_insn, match_*, et. al. ;;- cpp macro #define NOTICE_UPDATE_CC in file tm.h handles condition code @@ -196,7 +202,7 @@ (define_expand "cbranchdf4" [(set (cc0) (compare (match_operand:DF 1 "general_operand") - (match_operand:DF 2 "general_operand"))) + (match_operand:DF 2 "register_or_const0_operand"))) (set (pc) (if_then_else (match_operator 0 "ordered_comparison_operator" [(cc0) (const_int 0)]) @@ -276,7 +282,7 @@ ;; Move instructions (define_insn "movdi" - [(set (match_operand:DI 0 "general_operand" "=g,rm,o") + [(set (match_operand:DI 0 "nonimmediate_operand" "=g,rm,o") (match_operand:DI 1 "general_operand" "m,r,a"))] "" "* return output_move_quad (operands);" @@ -284,7 +290,7 @@ [(set_attr "length" "32,32,32")]) (define_insn "movsi" - [(set (match_operand:SI 0 "general_operand" "=r,r,r,rm,m") + [(set (match_operand:SI 0 "nonimmediate_operand" "=r,r,r,rm,m") (match_operand:SI 1 "general_operand" "rN,IJ,K,m,r"))] "" "* return output_move_double (operands);" @@ -293,7 +299,7 @@ [(set_attr "length" "4,6,8,16,16")]) (define_insn "movhi" - [(set (match_operand:HI 0 "general_operand" "=rR,rR,Q,Q") + [(set (match_operand:HI 0 "nonimmediate_operand" "=rR,rR,Q,Q") (match_operand:HI 1 "general_operand" "rRN,Qi,rRN,Qi"))] "" "* @@ -306,7 +312,7 @@ [(set_attr "length" "2,4,4,6")]) (define_insn "movqi" - [(set (match_operand:QI 0 "general_operand" "=rR,rR,Q,Q") + [(set (match_operand:QI 0 "nonimmediate_operand" "=rR,rR,Q,Q") (match_operand:QI 1 "general_operand" "rRN,Qi,rRN,Qi"))] "" "* @@ -318,11 +324,9 @@ }" [(set_attr "length" "2,4,4,6")]) -;; do we have to supply all these moves? e.g. to -;; NO_LOAD_FPU_REGs ? (define_insn "movdf" - [(set (match_operand:DF 0 "general_operand" "=a,fR,a,Q,g") - (match_operand:DF 1 "general_operand" "fFR,a,Q,a,g"))] + [(set (match_operand:DF 0 "float_nonimm_operand" "=a,fR,a,Q,g") + (match_operand:DF 1 "float_operand" "fFR,a,Q,a,g"))] "TARGET_FPU" "* if (which_alternative ==0 || which_alternative == 2) return \"ldd %1, %0\"; @@ -334,11 +338,17 @@ [(set_attr "length" "2,2,10,10,32")]) (define_insn "movsf" - [(set (match_operand:SF 0 "general_operand" "=g,r,g") - (match_operand:SF 1 "general_operand" "r,rmF,g"))] + [(set (match_operand:SF 0 "float_nonimm_operand" "=a,fR,a,Q,g") + (match_operand:SF 1 "float_operand" "fFR,a,Q,a,g"))] "TARGET_FPU" - "* return output_move_double (operands);" - [(set_attr "length" "16,16,16")]) + "* if (which_alternative ==0 || which_alternative == 2) + return \"{ldcfd|movof} %1, %0\"; + else if (which_alternative == 1 || which_alternative == 3) + return \"{stcdf|movfo} %1, %0\"; + else + return output_move_double (operands); " +;; just a guess.. + [(set_attr "length" "2,2,10,10,16")]) ;; maybe fiddle a bit with move_ratio, then ;; let constraints only accept a register ... @@ -386,15 +396,11 @@ ;;- truncation instructions (define_insn "truncdfsf2" - [(set (match_operand:SF 0 "general_operand" "=r,R,Q") - (float_truncate:SF (match_operand:DF 1 "register_operand" "a,a,a")))] + [(set (match_operand:SF 0 "float_nonimm_operand" "=f,R,Q") + (float_truncate:SF (match_operand:DF 1 "register_operand" "f,a,a")))] "TARGET_FPU" "* if (which_alternative ==0) { - output_asm_insn(\"{stcdf|movfo} %1, -(sp)\", operands); - output_asm_insn(\"mov (sp)+, %0\", operands); - operands[0] = gen_rtx_REG (HImode, REGNO (operands[0])+1); - output_asm_insn(\"mov (sp)+, %0\", operands); return \"\"; } else if (which_alternative == 1) @@ -402,11 +408,11 @@ else return \"{stcdf|movfo} %1, %0\"; " - [(set_attr "length" "6,2,4")]) + [(set_attr "length" "0,2,4")]) (define_expand "truncsihi2" - [(set (match_operand:HI 0 "general_operand" "=g") + [(set (match_operand:HI 0 "nonimmediate_operand" "=g") (subreg:HI (match_operand:SI 1 "general_operand" "or") 0))] @@ -417,7 +423,7 @@ ;;- zero extension instructions (define_insn "zero_extendqihi2" - [(set (match_operand:HI 0 "general_operand" "=rR,Q") + [(set (match_operand:HI 0 "nonimmediate_operand" "=rR,Q") (zero_extend:HI (match_operand:QI 1 "general_operand" "0,0")))] "" "bic $0177400, %0" @@ -439,14 +445,14 @@ ;;- sign extension instructions (define_insn "extendsfdf2" - [(set (match_operand:DF 0 "register_operand" "=a,a,a") - (float_extend:DF (match_operand:SF 1 "general_operand" "r,R,Q")))] + [(set (match_operand:DF 0 "register_operand" "=f,a,a") + (float_extend:DF (match_operand:SF 1 "float_operand" "f,R,Q")))] "TARGET_FPU" "@ - mov %1, -(sp)\;{ldcfd|movof} (sp)+,%0 + /* nothing */ {ldcfd|movof} %1, %0 {ldcfd|movof} %1, %0" - [(set_attr "length" "4,2,4")]) + [(set_attr "length" "0,2,4")]) ;; does movb sign extend in register-to-register move? (define_insn "extendqihi2" @@ -479,13 +485,13 @@ ;; unconditionally, and then match dependent on CPU type: (define_expand "extendhisi2" - [(set (match_operand:SI 0 "general_operand" "=g") + [(set (match_operand:SI 0 "nonimmediate_operand" "=g") (sign_extend:SI (match_operand:HI 1 "general_operand" "g")))] "" "") (define_insn "" ; "extendhisi2" - [(set (match_operand:SI 0 "general_operand" "=o,<,r") + [(set (match_operand:SI 0 "nonimmediate_operand" "=o,<,r") (sign_extend:SI (match_operand:HI 1 "general_operand" "g,g,g")))] "TARGET_40_PLUS" "* @@ -604,7 +610,7 @@ ;; cut float to int (define_insn "fix_truncdfsi2" - [(set (match_operand:SI 0 "general_operand" "=r,R,Q") + [(set (match_operand:SI 0 "nonimmediate_operand" "=r,R,Q") (fix:SI (fix:DF (match_operand:DF 1 "register_operand" "a,a,a"))))] "TARGET_FPU" "* if (which_alternative ==0) @@ -625,7 +631,7 @@ [(set_attr "length" "10,6,8")]) (define_insn "fix_truncdfhi2" - [(set (match_operand:HI 0 "general_operand" "=rR,Q") + [(set (match_operand:HI 0 "nonimmediate_operand" "=rR,Q") (fix:HI (fix:DF (match_operand:DF 1 "register_operand" "a,a"))))] "TARGET_FPU" "{stcdi|movfi} %1, %0" @@ -644,7 +650,7 @@ [(set_attr "length" "2,4,10")]) (define_insn "addsi3" - [(set (match_operand:SI 0 "general_operand" "=r,r,o,o,r,r,r,o,o,o") + [(set (match_operand:SI 0 "nonimmediate_operand" "=r,r,o,o,r,r,r,o,o,o") (plus:SI (match_operand:SI 1 "general_operand" "%0,0,0,0,0,0,0,0,0,0") (match_operand:SI 2 "general_operand" "r,o,r,o,I,J,K,I,J,K")))] "" @@ -694,7 +700,7 @@ [(set_attr "length" "6,10,12,16,6,2,10,10,6,16")]) (define_insn "addhi3" - [(set (match_operand:HI 0 "general_operand" "=rR,rR,Q,Q") + [(set (match_operand:HI 0 "nonimmediate_operand" "=rR,rR,Q,Q") (plus:HI (match_operand:HI 1 "general_operand" "%0,0,0,0") (match_operand:HI 2 "general_operand" "rRLM,Qi,rRLM,Qi")))] "" @@ -713,7 +719,7 @@ [(set_attr "length" "2,4,4,6")]) (define_insn "addqi3" - [(set (match_operand:QI 0 "general_operand" "=rR,rR,Q,Q") + [(set (match_operand:QI 0 "nonimmediate_operand" "=rR,rR,Q,Q") (plus:QI (match_operand:QI 1 "general_operand" "%0,0,0,0") (match_operand:QI 2 "general_operand" "rRLM,Qi,rRLM,Qi")))] "" @@ -746,7 +752,7 @@ [(set_attr "length" "2,4")]) (define_insn "subsi3" - [(set (match_operand:SI 0 "general_operand" "=r,r,o,o") + [(set (match_operand:SI 0 "nonimmediate_operand" "=r,r,o,o") (minus:SI (match_operand:SI 1 "general_operand" "0,0,0,0") (match_operand:SI 2 "general_operand" "r,o,r,o")))] "" @@ -780,7 +786,7 @@ [(set_attr "length" "6,10,12,16")]) (define_insn "subhi3" - [(set (match_operand:HI 0 "general_operand" "=rR,rR,Q,Q") + [(set (match_operand:HI 0 "nonimmediate_operand" "=rR,rR,Q,Q") (minus:HI (match_operand:HI 1 "general_operand" "0,0,0,0") (match_operand:HI 2 "general_operand" "rR,Qi,rR,Qi")))] "" @@ -793,7 +799,7 @@ [(set_attr "length" "2,4,4,6")]) (define_insn "subqi3" - [(set (match_operand:QI 0 "general_operand" "=rR,rR,Q,Q") + [(set (match_operand:QI 0 "nonimmediate_operand" "=rR,rR,Q,Q") (minus:QI (match_operand:QI 1 "general_operand" "0,0,0,0") (match_operand:QI 2 "general_operand" "rR,Qi,rR,Qi")))] "" @@ -808,73 +814,44 @@ ;;;;- and instructions ;; Bit-and on the pdp (like on the VAX) is done with a clear-bits insn. -(define_insn "andsi3" - [(set (match_operand:SI 0 "general_operand" "=r,r,o,o,r,r,r,o,o,o") - (and:SI (match_operand:SI 1 "general_operand" "%0,0,0,0,0,0,0,0,0,0") - (not:SI (match_operand:SI 2 "general_operand" "r,o,r,o,I,J,K,I,J,K"))))] +(define_expand "and<mode>3" + [(set (match_operand:PDPint 0 "nonimmediate_operand" "") + (and:PDPint (not:PDPint (match_operand:PDPint 1 "general_operand" "")) + (match_operand:PDPint 2 "general_operand" "")))] "" - "* -{ /* Here we trust that operands don't overlap - - or is lateoperands the low word?? - looks like it! */ + " +{ + rtx op1 = operands[1]; - rtx lateoperands[3]; - - lateoperands[0] = operands[0]; + /* If there is a constant argument, complement that one. + Similarly, if one of the inputs is the same as the output, + complement the other input. */ + if ((CONST_INT_P (operands[2]) && ! CONST_INT_P (op1)) || + rtx_equal_p (operands[0], operands[1])) + { + operands[1] = operands[2]; + operands[2] = op1; + op1 = operands[1]; + } - if (REG_P (operands[0])) - operands[0] = gen_rtx_REG (HImode, REGNO (operands[0]) + 1); + if (CONST_INT_P (op1)) + operands[1] = GEN_INT (~INTVAL (op1)); else - operands[0] = adjust_address (operands[0], HImode, 2); - - if (! CONSTANT_P(operands[2])) - { - lateoperands[2] = operands[2]; - - if (REG_P (operands[2])) - operands[2] = gen_rtx_REG (HImode, REGNO (operands[2]) + 1); - else - operands[2] = adjust_address (operands[2], HImode, 2); - - output_asm_insn (\"bic %2, %0\", operands); - output_asm_insn (\"bic %2, %0\", lateoperands); - return \"\"; - } - - lateoperands[2] = GEN_INT ((INTVAL (operands[2]) >> 16) & 0xffff); - operands[2] = GEN_INT (INTVAL (operands[2]) & 0xffff); - - /* these have different lengths, so we should have - different constraints! */ - if (INTVAL(operands[2])) - output_asm_insn (\"bic %2, %0\", operands); - - if (INTVAL(lateoperands[2])) - output_asm_insn (\"bic %2, %0\", lateoperands); - - return \"\"; -}" - [(set_attr "length" "4,8,8,12,4,4,8,6,6,12")]) - -(define_insn "andhi3" - [(set (match_operand:HI 0 "general_operand" "=rR,rR,Q,Q") - (and:HI (match_operand:HI 1 "general_operand" "0,0,0,0") - (not:HI (match_operand:HI 2 "general_operand" "rR,Qi,rR,Qi"))))] - "" - "bic %2, %0" - [(set_attr "length" "2,4,4,6")]) + operands[1] = expand_unop (<MODE>mode, one_cmpl_optab, op1, 0, 1); +}") -(define_insn "andqi3" - [(set (match_operand:QI 0 "general_operand" "=rR,rR,Q,Q") - (and:QI (match_operand:QI 1 "general_operand" "0,0,0,0") - (not:QI (match_operand:QI 2 "general_operand" "rR,Qi,rR,Qi"))))] +(define_insn "*bic<mode>" + [(set (match_operand:PDPint 0 "nonimmediate_operand" "=rR,rR,Q,Q") + (and:PDPint + (not: PDPint (match_operand:PDPint 1 "general_operand" "rR,Qi,rR,Qi")) + (match_operand:PDPint 2 "general_operand" "0,0,0,0")))] "" - "bicb %2, %0" + "bic<PDPint:isfx> %1, %0" [(set_attr "length" "2,4,4,6")]) ;;- Bit set (inclusive or) instructions (define_insn "iorsi3" - [(set (match_operand:SI 0 "general_operand" "=r,r,o,o,r,r,r,o,o,o") + [(set (match_operand:SI 0 "nonimmediate_operand" "=r,r,o,o,r,r,r,o,o,o") (ior:SI (match_operand:SI 1 "general_operand" "%0,0,0,0,0,0,0,0,0,0") (match_operand:SI 2 "general_operand" "r,o,r,o,I,J,K,I,J,K")))] "" @@ -922,7 +899,7 @@ [(set_attr "length" "4,8,8,12,4,4,8,6,6,12")]) (define_insn "iorhi3" - [(set (match_operand:HI 0 "general_operand" "=rR,rR,Q,Q") + [(set (match_operand:HI 0 "nonimmediate_operand" "=rR,rR,Q,Q") (ior:HI (match_operand:HI 1 "general_operand" "%0,0,0,0") (match_operand:HI 2 "general_operand" "rR,Qi,rR,Qi")))] "" @@ -930,7 +907,7 @@ [(set_attr "length" "2,4,4,6")]) (define_insn "iorqi3" - [(set (match_operand:QI 0 "general_operand" "=rR,rR,Q,Q") + [(set (match_operand:QI 0 "nonimmediate_operand" "=rR,rR,Q,Q") (ior:QI (match_operand:QI 1 "general_operand" "%0,0,0,0") (match_operand:QI 2 "general_operand" "rR,Qi,rR,Qi")))] "" @@ -957,15 +934,13 @@ output_asm_insn (\"xor %2, %0\", operands); output_asm_insn (\"xor %2, %0\", lateoperands); - - return \"\"; } - + return \"\"; }" [(set_attr "length" "4")]) (define_insn "xorhi3" - [(set (match_operand:HI 0 "general_operand" "=rR,Q") + [(set (match_operand:HI 0 "nonimmediate_operand" "=rR,Q") (xor:HI (match_operand:HI 1 "general_operand" "%0,0") (match_operand:HI 2 "register_operand" "r,r")))] "TARGET_40_PLUS" @@ -975,14 +950,14 @@ ;;- one complement instructions (define_insn "one_cmplhi2" - [(set (match_operand:HI 0 "general_operand" "=rR,Q") + [(set (match_operand:HI 0 "nonimmediate_operand" "=rR,Q") (not:HI (match_operand:HI 1 "general_operand" "0,0")))] "" "com %0" [(set_attr "length" "2,4")]) (define_insn "one_cmplqi2" - [(set (match_operand:QI 0 "general_operand" "=rR,rR") + [(set (match_operand:QI 0 "nonimmediate_operand" "=rR,rR") (not:QI (match_operand:QI 1 "general_operand" "0,g")))] "" "@ @@ -1014,7 +989,7 @@ ;; asl (define_insn "" - [(set (match_operand:HI 0 "general_operand" "=rR,Q") + [(set (match_operand:HI 0 "nonimmediate_operand" "=rR,Q") (ashift:HI (match_operand:HI 1 "general_operand" "0,0") (const_int 1)))] "" @@ -1027,7 +1002,7 @@ ;; asr (define_insn "" - [(set (match_operand:HI 0 "general_operand" "=rR,Q") + [(set (match_operand:HI 0 "nonimmediate_operand" "=rR,Q") (ashift:HI (match_operand:HI 1 "general_operand" "0,0") (const_int -1)))] "" @@ -1036,7 +1011,7 @@ ;; lsr (define_insn "" - [(set (match_operand:HI 0 "general_operand" "=rR,Q") + [(set (match_operand:HI 0 "nonimmediate_operand" "=rR,Q") (lshiftrt:HI (match_operand:HI 1 "general_operand" "0,0") (const_int 1)))] "" @@ -1070,7 +1045,7 @@ ;; shift by one cheap - so let's do that, if ;; space doesn't matter (define_insn "" - [(set (match_operand:HI 0 "general_operand" "=r") + [(set (match_operand:HI 0 "nonimmediate_operand" "=r") (ashift:HI (match_operand:HI 1 "general_operand" "0") (match_operand:HI 2 "expand_shift_operand" "O")))] "! optimize_size" @@ -1091,7 +1066,7 @@ ;; aslb (define_insn "" - [(set (match_operand:QI 0 "general_operand" "=r,o") + [(set (match_operand:QI 0 "nonimmediate_operand" "=r,o") (ashift:QI (match_operand:QI 1 "general_operand" "0,0") (match_operand:HI 2 "const_int_operand" "n,n")))] "" @@ -1113,7 +1088,7 @@ ;;; asr ;(define_insn "" -; [(set (match_operand:HI 0 "general_operand" "=rR,Q") +; [(set (match_operand:HI 0 "nonimmediate_operand" "=rR,Q") ; (ashiftrt:HI (match_operand:HI 1 "general_operand" "0,0") ; (const_int 1)))] ; "" @@ -1122,7 +1097,7 @@ ;; asrb (define_insn "" - [(set (match_operand:QI 0 "general_operand" "=r,o") + [(set (match_operand:QI 0 "nonimmediate_operand" "=r,o") (ashiftrt:QI (match_operand:QI 1 "general_operand" "0,0") (match_operand:HI 2 "const_int_operand" "n,n")))] "" @@ -1193,14 +1168,14 @@ ;; absolute (define_insn "absdf2" - [(set (match_operand:DF 0 "general_operand" "=fR,Q") + [(set (match_operand:DF 0 "nonimmediate_operand" "=fR,Q") (abs:DF (match_operand:DF 1 "general_operand" "0,0")))] "TARGET_FPU" "{absd|absf} %0" [(set_attr "length" "2,4")]) (define_insn "abshi2" - [(set (match_operand:HI 0 "general_operand" "=r,o") + [(set (match_operand:HI 0 "nonimmediate_operand" "=r,o") (abs:HI (match_operand:HI 1 "general_operand" "0,0")))] "TARGET_ABSHI_BUILTIN" "* @@ -1227,7 +1202,7 @@ ; -- just a thought - don't have time to check ; ;(define_expand "abshi2" -; [(match_operand:HI 0 "general_operand" "") +; [(match_operand:HI 0 "nonimmediate_operand" "") ; (match_operand:HI 1 "general_operand" "")] ; "" ; " @@ -1257,7 +1232,7 @@ ;; negate insns (define_insn "negdf2" - [(set (match_operand:DF 0 "general_operand" "=fR,Q") + [(set (match_operand:DF 0 "float_nonimm_operand" "=fR,Q") (neg:DF (match_operand:DF 1 "register_operand" "0,0")))] "TARGET_FPU" "{negd|negf} %0" @@ -1287,14 +1262,14 @@ [(set_attr "length" "10")]) (define_insn "neghi2" - [(set (match_operand:HI 0 "general_operand" "=rR,Q") + [(set (match_operand:HI 0 "nonimmediate_operand" "=rR,Q") (neg:HI (match_operand:HI 1 "general_operand" "0,0")))] "" "neg %0" [(set_attr "length" "2,4")]) (define_insn "negqi2" - [(set (match_operand:QI 0 "general_operand" "=rR,Q") + [(set (match_operand:QI 0 "nonimmediate_operand" "=rR,Q") (neg:QI (match_operand:QI 1 "general_operand" "0,0")))] "" "negb %0" @@ -1381,7 +1356,7 @@ (define_insn "muldf3" [(set (match_operand:DF 0 "register_operand" "=a,a,a") (mult:DF (match_operand:DF 1 "register_operand" "%0,0,0") - (match_operand:DF 2 "general_operand" "fR,Q,F")))] + (match_operand:DF 2 "float_operand" "fR,Q,F")))] "TARGET_FPU" "{muld|mulf} %2, %0" [(set_attr "length" "2,4,10")]) @@ -1395,7 +1370,7 @@ (define_insn "mulhi3" [(set (match_operand:HI 0 "register_operand" "=d,d") ; multiply regs (mult:HI (match_operand:HI 1 "register_operand" "%0,0") - (match_operand:HI 2 "general_operand" "rR,Qi")))] + (match_operand:HI 2 "float_operand" "rR,Qi")))] "TARGET_40_PLUS" "mul %2, %0" [(set_attr "length" "2,4")]) @@ -1403,7 +1378,7 @@ ;; 32 bit result (define_expand "mulhisi3" [(set (match_dup 3) - (match_operand:HI 1 "general_operand" "g,g")) + (match_operand:HI 1 "nonimmediate_operand" "g,g")) (set (match_operand:SI 0 "register_operand" "=r,r") ; even numbered! (mult:SI (truncate:HI (match_dup 0)) @@ -1441,15 +1416,15 @@ (define_expand "divhi3" [(set (subreg:HI (match_dup 1) 0) - (div:HI (match_operand:SI 1 "general_operand" "0") + (div:HI (match_operand:SI 1 "register_operand" "0") (match_operand:HI 2 "general_operand" "g"))) - (set (match_operand:HI 0 "general_operand" "=r") + (set (match_operand:HI 0 "register_operand" "=r") (subreg:HI (match_dup 1) 0))] "TARGET_40_PLUS" "") (define_insn "" - [(set (subreg:HI (match_operand:SI 0 "general_operand" "=r") 0) + [(set (subreg:HI (match_operand:SI 0 "register_operand" "=r") 0) (div:HI (match_operand:SI 1 "general_operand" "0") (match_operand:HI 2 "general_operand" "g")))] "TARGET_40_PLUS" @@ -1458,15 +1433,15 @@ (define_expand "modhi3" [(set (subreg:HI (match_dup 1) 2) - (mod:HI (match_operand:SI 1 "general_operand" "0") + (mod:HI (match_operand:SI 1 "register_operand" "0") (match_operand:HI 2 "general_operand" "g"))) - (set (match_operand:HI 0 "general_operand" "=r") + (set (match_operand:HI 0 "register_operand" "=r") (subreg:HI (match_dup 1) 2))] "TARGET_40_PLUS" "") (define_insn "" - [(set (subreg:HI (match_operand:SI 0 "general_operand" "=r") 2) + [(set (subreg:HI (match_operand:SI 0 "register_operand" "=r") 2) (mod:HI (match_operand:SI 1 "general_operand" "0") (match_operand:HI 2 "general_operand" "g")))] "TARGET_40_PLUS" @@ -1475,20 +1450,20 @@ ;(define_expand "divmodhi4" ; [(parallel [(set (subreg:HI (match_dup 1) 0) -; (div:HI (match_operand:SI 1 "general_operand" "0") +; (div:HI (match_operand:SI 1 "register_operand" "0") ; (match_operand:HI 2 "general_operand" "g"))) ; (set (subreg:HI (match_dup 1) 2) ; (mod:HI (match_dup 1) ; (match_dup 2)))]) -; (set (match_operand:HI 3 "general_operand" "=r") +; (set (match_operand:HI 3 "register_operand" "=r") ; (subreg:HI (match_dup 1) 2)) -; (set (match_operand:HI 0 "general_operand" "=r") +; (set (match_operand:HI 0 "register_operand" "=r") ; (subreg:HI (match_dup 1) 0))] ; "TARGET_40_PLUS" ; "") ; ;(define_insn "" -; [(set (subreg:HI (match_operand:SI 0 "general_operand" "=r") 0) +; [(set (subreg:HI (match_operand:SI 0 "register_operand" "=r") 0) ; (div:HI (match_operand:SI 1 "general_operand" "0") ; (match_operand:HI 2 "general_operand" "g"))) ; (set (subreg:HI (match_dup 0) 2) |