diff options
Diffstat (limited to 'gcc/config/mips/sb1.md')
| -rw-r--r-- | gcc/config/mips/sb1.md | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/gcc/config/mips/sb1.md b/gcc/config/mips/sb1.md index 2c1c0681d40..9e3cbe399f3 100644 --- a/gcc/config/mips/sb1.md +++ b/gcc/config/mips/sb1.md @@ -127,7 +127,7 @@ ;; register as destination. ;; ??? SB-1 can co-issue a load with a dependent arith insn if it executes on -;; an EX unit. Can not co-issue if the dependent insn executes on an LS unit. +;; an EX unit. Cannot co-issue if the dependent insn executes on an LS unit. ;; SB-1A can always co-issue here. ;; A load normally has a latency of zero cycles. In some cases, dependent @@ -144,7 +144,7 @@ (eq_attr "type" "load,prefetch")) "sb1_ls0 | sb1_ls1") -;; Can not co-issue fpload with fp exe when in 32-bit mode. +;; Cannot co-issue fpload with fp exe when in 32-bit mode. (define_insn_reservation "ir_sb1_fpload" 0 (and (eq_attr "cpu" "sb1,sb1a") @@ -252,7 +252,7 @@ (eq_attr "type" "const,arith,logical,move,signext")) "sb1_ls1 | sb1_ex1 | sb1_ex0") -;; On SB-1A, simple alu instructions can not execute on the LS1 unit, and we +;; On SB-1A, simple alu instructions cannot execute on the LS1 unit, and we ;; have none of the above problems. (define_insn_reservation "ir_sb1a_simple_alu" 1 |