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Diffstat (limited to 'gcc/config/mips/sb1.md')
| -rw-r--r-- | gcc/config/mips/sb1.md | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/gcc/config/mips/sb1.md b/gcc/config/mips/sb1.md index 41cebedce4f..aff645baffa 100644 --- a/gcc/config/mips/sb1.md +++ b/gcc/config/mips/sb1.md @@ -207,7 +207,7 @@ ;; unit has a latency of 5 cycles when the results goes to a LS unit (excluding ;; store data), otherwise a latency of 1 cycle. -;; ??? We can not handle latencies properly for simple alu instructions +;; ??? We cannot handle latencies properly for simple alu instructions ;; within the DFA pipeline model. Latencies can be defined only from one ;; insn reservation to another. We can't make them depend on which function ;; unit was used. This isn't a DFA flaw. There is a conflict here, as we |