diff options
Diffstat (limited to 'gcc/config/ia64')
| -rw-r--r-- | gcc/config/ia64/ia64.c | 16 | ||||
| -rw-r--r-- | gcc/config/ia64/ia64.h | 25 |
2 files changed, 14 insertions, 27 deletions
diff --git a/gcc/config/ia64/ia64.c b/gcc/config/ia64/ia64.c index e27ca031fb4..e15a8a7c8d5 100644 --- a/gcc/config/ia64/ia64.c +++ b/gcc/config/ia64/ia64.c @@ -715,7 +715,6 @@ int gr_reg_or_5bit_operand (rtx op, enum machine_mode mode) { return ((GET_CODE (op) == CONST_INT && INTVAL (op) >= 0 && INTVAL (op) < 32) - || GET_CODE (op) == CONSTANT_P_RTX || gr_register_operand (op, mode)); } @@ -725,7 +724,6 @@ int gr_reg_or_6bit_operand (rtx op, enum machine_mode mode) { return ((GET_CODE (op) == CONST_INT && CONST_OK_FOR_M (INTVAL (op))) - || GET_CODE (op) == CONSTANT_P_RTX || gr_register_operand (op, mode)); } @@ -735,7 +733,6 @@ int gr_reg_or_8bit_operand (rtx op, enum machine_mode mode) { return ((GET_CODE (op) == CONST_INT && CONST_OK_FOR_K (INTVAL (op))) - || GET_CODE (op) == CONSTANT_P_RTX || gr_register_operand (op, mode)); } @@ -745,7 +742,6 @@ int grfr_reg_or_8bit_operand (rtx op, enum machine_mode mode) { return ((GET_CODE (op) == CONST_INT && CONST_OK_FOR_K (INTVAL (op))) - || GET_CODE (op) == CONSTANT_P_RTX || grfr_register_operand (op, mode)); } @@ -756,7 +752,6 @@ int gr_reg_or_8bit_adjusted_operand (rtx op, enum machine_mode mode) { return ((GET_CODE (op) == CONST_INT && CONST_OK_FOR_L (INTVAL (op))) - || GET_CODE (op) == CONSTANT_P_RTX || gr_register_operand (op, mode)); } @@ -770,7 +765,6 @@ gr_reg_or_8bit_and_adjusted_operand (rtx op, enum machine_mode mode) { return ((GET_CODE (op) == CONST_INT && CONST_OK_FOR_K (INTVAL (op)) && CONST_OK_FOR_L (INTVAL (op))) - || GET_CODE (op) == CONSTANT_P_RTX || gr_register_operand (op, mode)); } @@ -780,7 +774,6 @@ int gr_reg_or_14bit_operand (rtx op, enum machine_mode mode) { return ((GET_CODE (op) == CONST_INT && CONST_OK_FOR_I (INTVAL (op))) - || GET_CODE (op) == CONSTANT_P_RTX || gr_register_operand (op, mode)); } @@ -790,7 +783,6 @@ int gr_reg_or_22bit_operand (rtx op, enum machine_mode mode) { return ((GET_CODE (op) == CONST_INT && CONST_OK_FOR_J (INTVAL (op))) - || GET_CODE (op) == CONSTANT_P_RTX || gr_register_operand (op, mode)); } @@ -799,8 +791,7 @@ gr_reg_or_22bit_operand (rtx op, enum machine_mode mode) int shift_count_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) { - return ((GET_CODE (op) == CONST_INT && CONST_OK_FOR_M (INTVAL (op))) - || GET_CODE (op) == CONSTANT_P_RTX); + return (GET_CODE (op) == CONST_INT && CONST_OK_FOR_M (INTVAL (op))); } /* Return 1 if OP is a 5 bit immediate operand. */ @@ -808,9 +799,8 @@ shift_count_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) int shift_32bit_count_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) { - return ((GET_CODE (op) == CONST_INT - && (INTVAL (op) >= 0 && INTVAL (op) < 32)) - || GET_CODE (op) == CONSTANT_P_RTX); + return (GET_CODE (op) == CONST_INT + && (INTVAL (op) >= 0 && INTVAL (op) < 32)); } /* Return 1 if OP is a 2, 4, 8, or 16 immediate operand. */ diff --git a/gcc/config/ia64/ia64.h b/gcc/config/ia64/ia64.h index 29f78c43a0e..b0f4dc64bce 100644 --- a/gcc/config/ia64/ia64.h +++ b/gcc/config/ia64/ia64.h @@ -2178,7 +2178,7 @@ do { \ { "destination_operand", {SUBREG, REG, MEM}}, \ { "not_postinc_memory_operand", {MEM}}, \ { "move_operand", {SUBREG, REG, MEM, CONST_INT, CONST_DOUBLE, \ - CONSTANT_P_RTX, SYMBOL_REF, CONST, LABEL_REF}}, \ + SYMBOL_REF, CONST, LABEL_REF}}, \ { "gr_register_operand", {SUBREG, REG}}, \ { "fr_register_operand", {SUBREG, REG}}, \ { "grfr_register_operand", {SUBREG, REG}}, \ @@ -2186,19 +2186,16 @@ do { \ { "fr_nonimmediate_operand", {SUBREG, REG, MEM}}, \ { "grfr_nonimmediate_operand", {SUBREG, REG, MEM}}, \ { "gr_reg_or_0_operand", {SUBREG, REG, CONST_INT}}, \ -{ "gr_reg_or_5bit_operand", {SUBREG, REG, CONST_INT, CONSTANT_P_RTX}}, \ -{ "gr_reg_or_6bit_operand", {SUBREG, REG, CONST_INT, CONSTANT_P_RTX}}, \ -{ "gr_reg_or_8bit_operand", {SUBREG, REG, CONST_INT, CONSTANT_P_RTX}}, \ -{ "grfr_reg_or_8bit_operand", {SUBREG, REG, CONST_INT, CONSTANT_P_RTX}}, \ -{ "gr_reg_or_8bit_adjusted_operand", {SUBREG, REG, CONST_INT, \ - CONSTANT_P_RTX}}, \ -{ "gr_reg_or_8bit_and_adjusted_operand", {SUBREG, REG, CONST_INT, \ - CONSTANT_P_RTX}}, \ -{ "gr_reg_or_14bit_operand", {SUBREG, REG, CONST_INT, CONSTANT_P_RTX}}, \ -{ "gr_reg_or_22bit_operand", {SUBREG, REG, CONST_INT, CONSTANT_P_RTX}}, \ -{ "shift_count_operand", {SUBREG, REG, CONST_INT, CONSTANT_P_RTX}}, \ -{ "shift_32bit_count_operand", {SUBREG, REG, CONST_INT, \ - CONSTANT_P_RTX}}, \ +{ "gr_reg_or_5bit_operand", {SUBREG, REG, CONST_INT}}, \ +{ "gr_reg_or_6bit_operand", {SUBREG, REG, CONST_INT}}, \ +{ "gr_reg_or_8bit_operand", {SUBREG, REG, CONST_INT}}, \ +{ "grfr_reg_or_8bit_operand", {SUBREG, REG, CONST_INT}}, \ +{ "gr_reg_or_8bit_adjusted_operand", {SUBREG, REG, CONST_INT}}, \ +{ "gr_reg_or_8bit_and_adjusted_operand", {SUBREG, REG, CONST_INT}}, \ +{ "gr_reg_or_14bit_operand", {SUBREG, REG, CONST_INT}}, \ +{ "gr_reg_or_22bit_operand", {SUBREG, REG, CONST_INT}}, \ +{ "shift_count_operand", {SUBREG, REG, CONST_INT}}, \ +{ "shift_32bit_count_operand", {SUBREG, REG, CONST_INT}}, \ { "shladd_operand", {CONST_INT}}, \ { "fetchadd_operand", {CONST_INT}}, \ { "fr_reg_or_fp01_operand", {SUBREG, REG, CONST_DOUBLE}}, \ |