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Diffstat (limited to 'gcc/config/ia64/ia64.md')
| -rw-r--r-- | gcc/config/ia64/ia64.md | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/gcc/config/ia64/ia64.md b/gcc/config/ia64/ia64.md index 48e8aa60e8d..5d1d47da55b 100644 --- a/gcc/config/ia64/ia64.md +++ b/gcc/config/ia64/ia64.md @@ -549,7 +549,7 @@ ;; Define register predicate prefix. ;; We can generate speculative loads only for general and fp registers - this -;; is constrained in ia64.c: ia64_speculate_insn (). +;; is constrained in ia64.cc: ia64_speculate_insn (). (define_mode_attr reg_pred_prefix [(BI "gr") (QI "gr") (HI "gr") (SI "gr") (DI "grfr") (SF "grfr") (DF "grfr") (XF "fr") (TI "fr")]) (define_mode_attr ld_class [(BI "ld") (QI "ld") (HI "ld") (SI "ld") (DI "ld,fld") (SF "fld,ld") (DF "fld,ld") (XF "fld") (TI "fldp")]) @@ -1420,7 +1420,7 @@ if (width == 32 && shift == 0) { /* Directly generating the mix4left instruction confuses - optimize_bit_field in function.c. Since this is performing + optimize_bit_field in function.cc. Since this is performing a useful optimization, we defer generation of the complicated mix4left RTL to the first splitting phase. */ rtx tmp = gen_reg_rtx (DImode); |