diff options
Diffstat (limited to 'gcc/config/i386')
173 files changed, 947 insertions, 760 deletions
diff --git a/gcc/config/i386/adxintrin.h b/gcc/config/i386/adxintrin.h index dd2a26ca9b0..36014ec2b18 100644 --- a/gcc/config/i386/adxintrin.h +++ b/gcc/config/i386/adxintrin.h @@ -1,4 +1,4 @@ -/* Copyright (C) 2012-2015 Free Software Foundation, Inc. +/* Copyright (C) 2012-2016 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/i386/ammintrin.h b/gcc/config/i386/ammintrin.h index fb9a53f43f4..0e509c31d64 100644 --- a/gcc/config/i386/ammintrin.h +++ b/gcc/config/i386/ammintrin.h @@ -1,4 +1,4 @@ -/* Copyright (C) 2007-2015 Free Software Foundation, Inc. +/* Copyright (C) 2007-2016 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/i386/athlon.md b/gcc/config/i386/athlon.md index d6913d3691a..a4b9c4ff7d1 100644 --- a/gcc/config/i386/athlon.md +++ b/gcc/config/i386/athlon.md @@ -1,4 +1,4 @@ -;; Copyright (C) 2002-2015 Free Software Foundation, Inc. +;; Copyright (C) 2002-2016 Free Software Foundation, Inc. ;; ;; This file is part of GCC. ;; diff --git a/gcc/config/i386/atom.md b/gcc/config/i386/atom.md index ad2cd3452a1..240eecf139e 100644 --- a/gcc/config/i386/atom.md +++ b/gcc/config/i386/atom.md @@ -1,5 +1,5 @@ ;; Atom Scheduling -;; Copyright (C) 2009-2015 Free Software Foundation, Inc. +;; Copyright (C) 2009-2016 Free Software Foundation, Inc. ;; ;; This file is part of GCC. ;; diff --git a/gcc/config/i386/att.h b/gcc/config/i386/att.h index f58bef93492..71edb93351b 100644 --- a/gcc/config/i386/att.h +++ b/gcc/config/i386/att.h @@ -1,5 +1,5 @@ /* Definitions for AT&T assembler syntax for the Intel 80386. - Copyright (C) 1988-2015 Free Software Foundation, Inc. + Copyright (C) 1988-2016 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/i386/avx2intrin.h b/gcc/config/i386/avx2intrin.h index b2a2f488c01..16c0ea8679f 100644 --- a/gcc/config/i386/avx2intrin.h +++ b/gcc/config/i386/avx2intrin.h @@ -1,4 +1,4 @@ -/* Copyright (C) 2011-2015 Free Software Foundation, Inc. +/* Copyright (C) 2011-2016 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/i386/avx512bwintrin.h b/gcc/config/i386/avx512bwintrin.h index 3114849fdd1..f40a7d91df3 100644 --- a/gcc/config/i386/avx512bwintrin.h +++ b/gcc/config/i386/avx512bwintrin.h @@ -1,4 +1,4 @@ -/* Copyright (C) 2014-2015 Free Software Foundation, Inc. +/* Copyright (C) 2014-2016 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/i386/avx512cdintrin.h b/gcc/config/i386/avx512cdintrin.h index 4da5250d379..93362c544d3 100644 --- a/gcc/config/i386/avx512cdintrin.h +++ b/gcc/config/i386/avx512cdintrin.h @@ -1,4 +1,4 @@ -/* Copyright (C) 2013-2015 Free Software Foundation, Inc. +/* Copyright (C) 2013-2016 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/i386/avx512dqintrin.h b/gcc/config/i386/avx512dqintrin.h index b36ef48f2a1..14a4e8869a1 100644 --- a/gcc/config/i386/avx512dqintrin.h +++ b/gcc/config/i386/avx512dqintrin.h @@ -1,4 +1,4 @@ -/* Copyright (C) 2014-2015 Free Software Foundation, Inc. +/* Copyright (C) 2014-2016 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/i386/avx512erintrin.h b/gcc/config/i386/avx512erintrin.h index b7b103ca1f4..7b76b686b56 100644 --- a/gcc/config/i386/avx512erintrin.h +++ b/gcc/config/i386/avx512erintrin.h @@ -1,4 +1,4 @@ -/* Copyright (C) 2013-2015 Free Software Foundation, Inc. +/* Copyright (C) 2013-2016 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/i386/avx512fintrin.h b/gcc/config/i386/avx512fintrin.h index d7e7020577b..e009d8c55bb 100644 --- a/gcc/config/i386/avx512fintrin.h +++ b/gcc/config/i386/avx512fintrin.h @@ -1,4 +1,4 @@ -/* Copyright (C) 2013-2015 Free Software Foundation, Inc. +/* Copyright (C) 2013-2016 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/i386/avx512ifmaintrin.h b/gcc/config/i386/avx512ifmaintrin.h index b558981b258..c2f43111e1a 100644 --- a/gcc/config/i386/avx512ifmaintrin.h +++ b/gcc/config/i386/avx512ifmaintrin.h @@ -1,4 +1,4 @@ -/* Copyright (C) 2013-2015 Free Software Foundation, Inc. +/* Copyright (C) 2013-2016 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/i386/avx512ifmavlintrin.h b/gcc/config/i386/avx512ifmavlintrin.h index 750eaff3ed6..9091f899cae 100644 --- a/gcc/config/i386/avx512ifmavlintrin.h +++ b/gcc/config/i386/avx512ifmavlintrin.h @@ -1,4 +1,4 @@ -/* Copyright (C) 2013-2015 Free Software Foundation, Inc. +/* Copyright (C) 2013-2016 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/i386/avx512pfintrin.h b/gcc/config/i386/avx512pfintrin.h index 433e182344b..06599c3082d 100644 --- a/gcc/config/i386/avx512pfintrin.h +++ b/gcc/config/i386/avx512pfintrin.h @@ -1,4 +1,4 @@ -/* Copyright (C) 2013-2015 Free Software Foundation, Inc. +/* Copyright (C) 2013-2016 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/i386/avx512vbmiintrin.h b/gcc/config/i386/avx512vbmiintrin.h index f93b13b47d2..a00cf70f527 100644 --- a/gcc/config/i386/avx512vbmiintrin.h +++ b/gcc/config/i386/avx512vbmiintrin.h @@ -1,4 +1,4 @@ -/* Copyright (C) 2013-2015 Free Software Foundation, Inc. +/* Copyright (C) 2013-2016 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/i386/avx512vbmivlintrin.h b/gcc/config/i386/avx512vbmivlintrin.h index cab4e5c07c5..4af9fb9b019 100644 --- a/gcc/config/i386/avx512vbmivlintrin.h +++ b/gcc/config/i386/avx512vbmivlintrin.h @@ -1,4 +1,4 @@ -/* Copyright (C) 2013-2015 Free Software Foundation, Inc. +/* Copyright (C) 2013-2016 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/i386/avx512vlbwintrin.h b/gcc/config/i386/avx512vlbwintrin.h index 601dcdd91a1..f260526d06f 100644 --- a/gcc/config/i386/avx512vlbwintrin.h +++ b/gcc/config/i386/avx512vlbwintrin.h @@ -1,4 +1,4 @@ -/* Copyright (C) 2014-2015 Free Software Foundation, Inc. +/* Copyright (C) 2014-2016 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/i386/avx512vldqintrin.h b/gcc/config/i386/avx512vldqintrin.h index 7ccb62b45cb..697b81c4017 100644 --- a/gcc/config/i386/avx512vldqintrin.h +++ b/gcc/config/i386/avx512vldqintrin.h @@ -1,4 +1,4 @@ -/* Copyright (C) 2014-2015 Free Software Foundation, Inc. +/* Copyright (C) 2014-2016 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/i386/avx512vlintrin.h b/gcc/config/i386/avx512vlintrin.h index b995cecc8c0..d0ffb2b4d35 100644 --- a/gcc/config/i386/avx512vlintrin.h +++ b/gcc/config/i386/avx512vlintrin.h @@ -1,4 +1,4 @@ -/* Copyright (C) 2014-2015 Free Software Foundation, Inc. +/* Copyright (C) 2014-2016 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/i386/avxintrin.h b/gcc/config/i386/avxintrin.h index f49fe9d16b7..9519400176d 100644 --- a/gcc/config/i386/avxintrin.h +++ b/gcc/config/i386/avxintrin.h @@ -1,4 +1,4 @@ -/* Copyright (C) 2008-2015 Free Software Foundation, Inc. +/* Copyright (C) 2008-2016 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/i386/avxmath.h b/gcc/config/i386/avxmath.h index 76246c7908e..e4ee1fc425e 100644 --- a/gcc/config/i386/avxmath.h +++ b/gcc/config/i386/avxmath.h @@ -1,4 +1,4 @@ -/* Copyright (C) 2010-2015 Free Software Foundation, Inc. +/* Copyright (C) 2010-2016 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/i386/bdver1.md b/gcc/config/i386/bdver1.md index 3ef23612e25..f05da31de3d 100644 --- a/gcc/config/i386/bdver1.md +++ b/gcc/config/i386/bdver1.md @@ -1,4 +1,4 @@ -;; Copyright (C) 2010-2015 Free Software Foundation, Inc. +;; Copyright (C) 2010-2016 Free Software Foundation, Inc. ;; ;; This file is part of GCC. ;; diff --git a/gcc/config/i386/bdver3.md b/gcc/config/i386/bdver3.md index eb93d41830a..d324201900d 100644 --- a/gcc/config/i386/bdver3.md +++ b/gcc/config/i386/bdver3.md @@ -1,4 +1,4 @@ -;; Copyright (C) 2012-2015 Free Software Foundation, Inc. +;; Copyright (C) 2012-2016 Free Software Foundation, Inc. ;; ;; This file is part of GCC. ;; diff --git a/gcc/config/i386/biarch64.h b/gcc/config/i386/biarch64.h index b8eccf8333c..43bb18b6803 100644 --- a/gcc/config/i386/biarch64.h +++ b/gcc/config/i386/biarch64.h @@ -1,7 +1,7 @@ /* Make configure files to produce biarch compiler defaulting to 64bit mode. This file must be included very first, while the OS specific file later to overwrite otherwise wrong defaults. - Copyright (C) 2001-2015 Free Software Foundation, Inc. + Copyright (C) 2001-2016 Free Software Foundation, Inc. Contributed by Bo Thorsen <bo@suse.de>. This file is part of GCC. diff --git a/gcc/config/i386/biarchx32.h b/gcc/config/i386/biarchx32.h index a71e819fbb9..a09a3462bee 100644 --- a/gcc/config/i386/biarchx32.h +++ b/gcc/config/i386/biarchx32.h @@ -1,7 +1,7 @@ /* Make configure files to produce biarch compiler defaulting to x32 mode. This file must be included very first, while the OS specific file later to overwrite otherwise wrong defaults. - Copyright (C) 2012-2015 Free Software Foundation, Inc. + Copyright (C) 2012-2016 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/i386/bmi2intrin.h b/gcc/config/i386/bmi2intrin.h index 9f4df7794ad..f925b516b35 100644 --- a/gcc/config/i386/bmi2intrin.h +++ b/gcc/config/i386/bmi2intrin.h @@ -1,4 +1,4 @@ -/* Copyright (C) 2011-2015 Free Software Foundation, Inc. +/* Copyright (C) 2011-2016 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/i386/bmiintrin.h b/gcc/config/i386/bmiintrin.h index a2e966cce16..a838a927be9 100644 --- a/gcc/config/i386/bmiintrin.h +++ b/gcc/config/i386/bmiintrin.h @@ -1,4 +1,4 @@ -/* Copyright (C) 2010-2015 Free Software Foundation, Inc. +/* Copyright (C) 2010-2016 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/i386/bmmintrin.h b/gcc/config/i386/bmmintrin.h index 93efce79d29..104cda34ce8 100644 --- a/gcc/config/i386/bmmintrin.h +++ b/gcc/config/i386/bmmintrin.h @@ -1,4 +1,4 @@ -/* Copyright (C) 2007-2015 Free Software Foundation, Inc. +/* Copyright (C) 2007-2016 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/i386/bsd.h b/gcc/config/i386/bsd.h index 2c2c08545b7..fb83c4fb4ec 100644 --- a/gcc/config/i386/bsd.h +++ b/gcc/config/i386/bsd.h @@ -1,7 +1,7 @@ /* Definitions for BSD assembler syntax for Intel 386 (actually AT&T syntax for insns and operands, adapted to BSD conventions for symbol names and debugging.) - Copyright (C) 1988-2015 Free Software Foundation, Inc. + Copyright (C) 1988-2016 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/i386/btver2.md b/gcc/config/i386/btver2.md index 617e5264dae..cc8edd5e988 100644 --- a/gcc/config/i386/btver2.md +++ b/gcc/config/i386/btver2.md @@ -1,4 +1,4 @@ -;; Copyright (C) 2012-2015 Free Software Foundation, Inc. +;; Copyright (C) 2012-2016 Free Software Foundation, Inc. ;; ;; This file is part of GCC. ;; diff --git a/gcc/config/i386/clflushoptintrin.h b/gcc/config/i386/clflushoptintrin.h index 16a00c9733e..c079e39c51c 100644 --- a/gcc/config/i386/clflushoptintrin.h +++ b/gcc/config/i386/clflushoptintrin.h @@ -1,4 +1,4 @@ -/* Copyright (C) 2013-2015 Free Software Foundation, Inc. +/* Copyright (C) 2013-2016 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/i386/clwbintrin.h b/gcc/config/i386/clwbintrin.h index bde6de4f870..47931ff327b 100644 --- a/gcc/config/i386/clwbintrin.h +++ b/gcc/config/i386/clwbintrin.h @@ -1,4 +1,4 @@ -/* Copyright (C) 2013-2015 Free Software Foundation, Inc. +/* Copyright (C) 2013-2016 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/i386/clzerointrin.h b/gcc/config/i386/clzerointrin.h index 696585b6d88..c353f205b6e 100644 --- a/gcc/config/i386/clzerointrin.h +++ b/gcc/config/i386/clzerointrin.h @@ -1,4 +1,4 @@ -/* Copyright (C) 2012-2015 Free Software Foundation, Inc. +/* Copyright (C) 2012-2016 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/i386/constraints.md b/gcc/config/i386/constraints.md index 2861d8dfdd2..bac9d6668a8 100644 --- a/gcc/config/i386/constraints.md +++ b/gcc/config/i386/constraints.md @@ -1,5 +1,5 @@ ;; Constraint definitions for IA-32 and x86-64. -;; Copyright (C) 2006-2015 Free Software Foundation, Inc. +;; Copyright (C) 2006-2016 Free Software Foundation, Inc. ;; ;; This file is part of GCC. ;; @@ -148,6 +148,7 @@ ;; We use the B prefix to denote any number of internal operands: ;; f FLAGS_REG ;; g GOT memory operand. +;; m Vector memory operand ;; s Sibcall memory operand, not valid for TARGET_X32 ;; w Call memory operand, not valid for TARGET_X32 ;; z Constant call address operand. @@ -160,15 +161,23 @@ "@internal GOT memory operand." (match_operand 0 "GOT_memory_operand")) +(define_constraint "Bm" + "@internal Vector memory operand." + (match_operand 0 "vector_memory_operand")) + (define_constraint "Bs" "@internal Sibcall memory operand." - (and (not (match_test "TARGET_X32")) - (match_operand 0 "sibcall_memory_operand"))) + (ior (and (not (match_test "TARGET_X32")) + (match_operand 0 "sibcall_memory_operand")) + (and (match_test "TARGET_X32 && Pmode == DImode") + (match_operand 0 "GOT_memory_operand")))) (define_constraint "Bw" "@internal Call memory operand." - (and (not (match_test "TARGET_X32")) - (match_operand 0 "memory_operand"))) + (ior (and (not (match_test "TARGET_X32")) + (match_operand 0 "memory_operand")) + (and (match_test "TARGET_X32 && Pmode == DImode") + (match_operand 0 "GOT_memory_operand")))) (define_constraint "Bz" "@internal Constant call address operand." diff --git a/gcc/config/i386/core2.md b/gcc/config/i386/core2.md index 43964085374..2235cb661cd 100644 --- a/gcc/config/i386/core2.md +++ b/gcc/config/i386/core2.md @@ -1,5 +1,5 @@ ;; Scheduling for Core 2 and derived processors. -;; Copyright (C) 2004-2015 Free Software Foundation, Inc. +;; Copyright (C) 2004-2016 Free Software Foundation, Inc. ;; ;; This file is part of GCC. ;; diff --git a/gcc/config/i386/cpuid.h b/gcc/config/i386/cpuid.h index fccdf1f8782..8760e60d382 100644 --- a/gcc/config/i386/cpuid.h +++ b/gcc/config/i386/cpuid.h @@ -1,5 +1,5 @@ /* - * Copyright (C) 2007-2015 Free Software Foundation, Inc. + * Copyright (C) 2007-2016 Free Software Foundation, Inc. * * This file is free software; you can redistribute it and/or modify it * under the terms of the GNU General Public License as published by the @@ -95,6 +95,8 @@ /* %ecx */ #define bit_PREFETCHWT1 (1 << 0) #define bit_AVX512VBMI (1 << 1) +#define bit_PKU (1 << 3) +#define bit_OSPKE (1 << 4) /* XFEATURE_ENABLED_MASK register bits (%eax == 13, %ecx == 0) */ #define bit_BNDREGS (1 << 3) diff --git a/gcc/config/i386/cross-stdarg.h b/gcc/config/i386/cross-stdarg.h index 867415037e4..7d77b0edf55 100644 --- a/gcc/config/i386/cross-stdarg.h +++ b/gcc/config/i386/cross-stdarg.h @@ -1,4 +1,4 @@ -/* Copyright (C) 2002-2015 Free Software Foundation, Inc. +/* Copyright (C) 2002-2016 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/i386/crtdll.h b/gcc/config/i386/crtdll.h index b3ffd659273..23346839c0d 100644 --- a/gcc/config/i386/crtdll.h +++ b/gcc/config/i386/crtdll.h @@ -1,7 +1,7 @@ /* Operating system specific defines to be used when targeting GCC for hosting on Windows32, using GNU tools and the Windows32 API Library. This variant uses CRTDLL.DLL instead of MSVCRTDLL.DLL. - Copyright (C) 1998-2015 Free Software Foundation, Inc. + Copyright (C) 1998-2016 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/i386/cygming.h b/gcc/config/i386/cygming.h index 71506ecbcd0..71019cbfdbc 100644 --- a/gcc/config/i386/cygming.h +++ b/gcc/config/i386/cygming.h @@ -1,6 +1,6 @@ /* Operating system specific defines to be used when targeting GCC for hosting on Windows32, using a Unix style C library and tools. - Copyright (C) 1995-2015 Free Software Foundation, Inc. + Copyright (C) 1995-2016 Free Software Foundation, Inc. This file is part of GCC. @@ -432,6 +432,11 @@ do { \ fputc ('\n', (FILE)); \ } \ while (0) + +/* Use the weak support for ONE_ONLY decls. */ +#undef MAKE_DECL_ONE_ONLY +#define MAKE_DECL_ONE_ONLY(DECL) (DECL_WEAK (DECL) = 1) + #endif /* HAVE_GAS_WEAK */ /* FIXME: SUPPORTS_WEAK && TARGET_HAVE_NAMED_SECTIONS is true, diff --git a/gcc/config/i386/cygming.opt b/gcc/config/i386/cygming.opt index d9c1259e69c..a9074bfa928 100644 --- a/gcc/config/i386/cygming.opt +++ b/gcc/config/i386/cygming.opt @@ -1,6 +1,6 @@ ; Cygwin- and MinGW-specific options. -; Copyright (C) 2005-2015 Free Software Foundation, Inc. +; Copyright (C) 2005-2016 Free Software Foundation, Inc. ; ; This file is part of GCC. ; diff --git a/gcc/config/i386/cygwin-stdint.h b/gcc/config/i386/cygwin-stdint.h index 13b2bfe584a..f5ea488a307 100644 --- a/gcc/config/i386/cygwin-stdint.h +++ b/gcc/config/i386/cygwin-stdint.h @@ -1,5 +1,5 @@ /* Definitions for <stdint.h> types on systems using Cygwin. - Copyright (C) 2009-2015 Free Software Foundation, Inc. + Copyright (C) 2009-2016 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/i386/cygwin-w64.h b/gcc/config/i386/cygwin-w64.h index 586ce051046..4faf5d96a56 100644 --- a/gcc/config/i386/cygwin-w64.h +++ b/gcc/config/i386/cygwin-w64.h @@ -1,7 +1,7 @@ /* Operating system specific defines to be used when targeting GCC for hosting on Windows 32/64 via Cygwin runtime, using GNU tools and the Windows API Library. - Copyright (C) 2013-2015 Free Software Foundation, Inc. + Copyright (C) 2013-2016 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/i386/cygwin.h b/gcc/config/i386/cygwin.h index d1b6bc51b53..182e4d62658 100644 --- a/gcc/config/i386/cygwin.h +++ b/gcc/config/i386/cygwin.h @@ -1,6 +1,6 @@ /* Operating system specific defines to be used when targeting GCC for hosting on Windows32, using a Unix style C library and tools. - Copyright (C) 1995-2015 Free Software Foundation, Inc. + Copyright (C) 1995-2016 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/i386/cygwin.opt b/gcc/config/i386/cygwin.opt index 569863b9272..fa976b37dce 100644 --- a/gcc/config/i386/cygwin.opt +++ b/gcc/config/i386/cygwin.opt @@ -1,6 +1,6 @@ ; Cygwin-specific options. -; Copyright (C) 2013-2015 Free Software Foundation, Inc. +; Copyright (C) 2013-2016 Free Software Foundation, Inc. ; ; This file is part of GCC. ; diff --git a/gcc/config/i386/darwin.h b/gcc/config/i386/darwin.h index 2006a750013..c10ceff0cc2 100644 --- a/gcc/config/i386/darwin.h +++ b/gcc/config/i386/darwin.h @@ -1,5 +1,5 @@ /* Target definitions for x86 running Darwin. - Copyright (C) 2001-2015 Free Software Foundation, Inc. + Copyright (C) 2001-2016 Free Software Foundation, Inc. Contributed by Apple Computer Inc. This file is part of GCC. @@ -226,7 +226,11 @@ do { \ compiles default to stabs+. darwin9+ defaults to dwarf-2. */ #ifndef DARWIN_PREFER_DWARF #undef PREFERRED_DEBUGGING_TYPE +#ifdef HAVE_AS_STABS_DIRECTIVE #define PREFERRED_DEBUGGING_TYPE (TARGET_64BIT ? DWARF2_DEBUG : DBX_DEBUG) +#else +#define PREFERRED_DEBUGGING_TYPE DWARF2_DEBUG +#endif #endif /* Darwin uses the standard DWARF register numbers but the default diff --git a/gcc/config/i386/darwin64.h b/gcc/config/i386/darwin64.h index 8e641b71e35..bb6bf512cbb 100644 --- a/gcc/config/i386/darwin64.h +++ b/gcc/config/i386/darwin64.h @@ -1,5 +1,5 @@ /* Target definitions for x86_64 running Darwin. - Copyright (C) 2006-2015 Free Software Foundation, Inc. + Copyright (C) 2006-2016 Free Software Foundation, Inc. Contributed by Apple Computer Inc. This file is part of GCC. diff --git a/gcc/config/i386/djgpp-stdint.h b/gcc/config/i386/djgpp-stdint.h index 84f2b5099fe..7045611761f 100644 --- a/gcc/config/i386/djgpp-stdint.h +++ b/gcc/config/i386/djgpp-stdint.h @@ -1,5 +1,5 @@ /* Definitions for <stdint.h> types on systems using DJGPP. - Copyright (C) 2009-2015 Free Software Foundation, Inc. + Copyright (C) 2009-2016 Free Software Foundation, Inc. This file is part of GCC. @@ -22,21 +22,21 @@ along with GCC; see the file COPYING3. If not see /* Exact-width integer types */ #define INT8_TYPE "signed char" -#define INT16_TYPE "signed short int" -#define INT32_TYPE "signed long int" -#define INT64_TYPE "signed long long int" +#define INT16_TYPE "short int" +#define INT32_TYPE "int" +#define INT64_TYPE "long long int" #define UINT8_TYPE "unsigned char" #define UINT16_TYPE "short unsigned int" -#define UINT32_TYPE "long unsigned int" +#define UINT32_TYPE "unsigned int" #define UINT64_TYPE "long long unsigned int" /* Minimum-width integer types */ #define INT_LEAST8_TYPE "signed char" -#define INT_LEAST16_TYPE "signed short int" -#define INT_LEAST32_TYPE "signed int" -#define INT_LEAST64_TYPE "signed long long int" +#define INT_LEAST16_TYPE "short int" +#define INT_LEAST32_TYPE "int" +#define INT_LEAST64_TYPE "long long int" #define UINT_LEAST8_TYPE "unsigned char" #define UINT_LEAST16_TYPE "short unsigned int" @@ -46,12 +46,12 @@ along with GCC; see the file COPYING3. If not see /* Fastest minimum-width integer types */ #define INT_FAST8_TYPE "signed char" -#define INT_FAST16_TYPE "signed int" -#define INT_FAST32_TYPE "signed int" -#define INT_FAST64_TYPE "long long signed int" +#define INT_FAST16_TYPE "short int" +#define INT_FAST32_TYPE "int" +#define INT_FAST64_TYPE "long long int" #define UINT_FAST8_TYPE "unsigned char" -#define UINT_FAST16_TYPE "unsigned int" +#define UINT_FAST16_TYPE "short unsigned int" #define UINT_FAST32_TYPE "unsigned int" #define UINT_FAST64_TYPE "long long unsigned int" diff --git a/gcc/config/i386/djgpp.c b/gcc/config/i386/djgpp.c new file mode 100644 index 00000000000..7414338e4a5 --- /dev/null +++ b/gcc/config/i386/djgpp.c @@ -0,0 +1,47 @@ +/* Subroutines for DJGPP. + Copyright (C) 2013-2016 Free Software Foundation, Inc. + +This file is part of GCC. + +GCC is free software; you can redistribute it and/or modify it under +the terms of the GNU General Public License as published by the Free +Software Foundation; either version 3, or (at your option) any later +version. + +GCC is distributed in the hope that it will be useful, but WITHOUT ANY +WARRANTY; without even the implied warranty of MERCHANTABILITY or +FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +for more details. + +You should have received a copy of the GNU General Public License +along with GCC; see the file COPYING3. If not see +<http://www.gnu.org/licenses/>. */ + +#include "config.h" +#include "system.h" +#include "coretypes.h" +#include "tm.h" +#include "output.h" +#include "lto-section-names.h" + +void +i386_djgpp_asm_named_section(const char *name, unsigned int flags, + tree) +{ + char flagchars[8], *f = flagchars; + + if (flags & SECTION_WRITE) + *f++ = 'w'; + if (flags & SECTION_CODE) + *f++ = 'x'; + + /* LTO sections need 1-byte alignment to avoid confusing the + zlib decompression algorithm with trailing zero pad bytes. */ + if (strncmp (name, LTO_SECTION_NAME_PREFIX, + strlen (LTO_SECTION_NAME_PREFIX)) == 0) + *f++ = '0'; + + *f++ = '\0'; + + fprintf (asm_out_file, "\t.section\t%s,\"%s\"\n", name, flagchars); +} diff --git a/gcc/config/i386/djgpp.h b/gcc/config/i386/djgpp.h index f8b90313529..c758f5f789d 100644 --- a/gcc/config/i386/djgpp.h +++ b/gcc/config/i386/djgpp.h @@ -1,5 +1,5 @@ /* Configuration for an i386 running MS-DOS with DJGPP. - Copyright (C) 1997-2015 Free Software Foundation, Inc. + Copyright (C) 1997-2016 Free Software Foundation, Inc. This file is part of GCC. @@ -20,6 +20,9 @@ along with GCC; see the file COPYING3. If not see /* Support generation of DWARF2 debugging info. */ #define DWARF2_DEBUGGING_INFO 1 +#undef PREFERRED_DEBUGGING_TYPE +#define PREFERRED_DEBUGGING_TYPE DWARF2_DEBUG + /* Don't assume anything about the header files. */ #define NO_IMPLICIT_EXTERN_C @@ -30,6 +33,10 @@ along with GCC; see the file COPYING3. If not see #undef DATA_SECTION_ASM_OP #define DATA_SECTION_ASM_OP "\t.section .data" +/* Define the name of the .ident op. */ +#undef TARGET_ASM_OUTPUT_IDENT +#define TARGET_ASM_OUTPUT_IDENT default_asm_output_ident_directive + /* Enable alias attribute support. */ #ifndef SET_ASM_OP #define SET_ASM_OP "\t.set\t" @@ -39,56 +46,25 @@ along with GCC; see the file COPYING3. If not see #undef TEXT_SECTION_ASM_OP #define TEXT_SECTION_ASM_OP "\t.section .text" -/* Define standard DJGPP installation paths. */ -/* We override default /usr or /usr/local part with /dev/env/DJDIR which */ -/* points to actual DJGPP installation directory. */ - -/* Search for as.exe and ld.exe in DJGPP's binary directory. */ -#undef MD_EXEC_PREFIX -#define MD_EXEC_PREFIX "/dev/env/DJDIR/bin/" - -/* Standard DJGPP library and startup files */ -#undef MD_STARTFILE_PREFIX -#define MD_STARTFILE_PREFIX "/dev/env/DJDIR/lib/" - -/* Correctly handle absolute filename detection in cp/xref.c */ -#define FILE_NAME_ABSOLUTE_P(NAME) \ - (((NAME)[0] == '/') || ((NAME)[0] == '\\') || \ - (((NAME)[0] >= 'A') && ((NAME)[0] <= 'z') && ((NAME)[1] == ':'))) - #define TARGET_OS_CPP_BUILTINS() \ do \ { \ + if (!flag_iso) \ + builtin_define_with_int_value ("DJGPP",2); \ + builtin_define_with_int_value ("__DJGPP",2); \ + builtin_define_with_int_value ("__DJGPP__",2); \ builtin_define_std ("MSDOS"); \ builtin_define_std ("GO32"); \ + builtin_define_std ("unix"); \ builtin_assert ("system=msdos"); \ } \ while (0) -/* Include <sys/version.h> so __DJGPP__ and __DJGPP_MINOR__ are defined. */ #undef CPP_SPEC -#define CPP_SPEC "-remap %{posix:-D_POSIX_SOURCE} \ - -imacros %s../include/sys/version.h" - -/* We need to override link_command_spec in gcc.c so support -Tdjgpp.djl. - This cannot be done in LINK_SPECS as that LINK_SPECS is processed - before library search directories are known by the linker. - This avoids problems when specs file is not available. An alternate way, - suggested by Robert Hoehne, is to use SUBTARGET_EXTRA_SPECS instead. -*/ - -#undef LINK_COMMAND_SPEC -#define LINK_COMMAND_SPEC \ -"%{!fsyntax-only: \ -%{!c:%{!M:%{!MM:%{!E:%{!S:%(linker) %l " LINK_COMPRESS_DEBUG_SPEC \ -"%X %{o*} %{e*} %{N} %{n} \ -\t%{r} %{s} %{t} %{u*} %{z} %{Z}\ -\t%{!nostdlib:%{!nostartfiles:%S}}\ -\t%{static:} %{L*} %D %o\ -\t%{!nostdlib:%{!nodefaultlibs:%G %L %G}}\ -\t%{!nostdlib:%{!nostartfiles:%E}}\ -\t-Tdjgpp.djl %{T*}}}}}}}\n\ -%{!c:%{!M:%{!MM:%{!E:%{!S:stubify %{v} %{o*:%*} %{!o*:a.out} }}}}}" +#define CPP_SPEC "-remap %{posix:-D_POSIX_SOURCE}" + +#undef POST_LINK_SPEC +#define POST_LINK_SPEC "stubify %{v} %{o*:%*} %{!o*:a.out}" /* Always just link in 'libc.a'. */ #undef LIB_SPEC @@ -98,12 +74,8 @@ along with GCC; see the file COPYING3. If not see #undef STARTFILE_SPEC #define STARTFILE_SPEC "%{pg:gcrt0.o%s}%{!pg:crt0.o%s}" -/* Make sure that gcc will not look for .h files in /usr/local/include - unless user explicitly requests it. */ -#undef LOCAL_INCLUDE_DIR - /* Switch into a generic section. */ -#define TARGET_ASM_NAMED_SECTION default_coff_asm_named_section +#define TARGET_ASM_NAMED_SECTION i386_djgpp_asm_named_section /* This is how to output an assembler line that says to advance the location counter @@ -159,23 +131,37 @@ along with GCC; see the file COPYING3. If not see #undef PTRDIFF_TYPE #define PTRDIFF_TYPE "int" -/* Used to be defined in xm-djgpp.h, but moved here for cross-compilers. */ -#define LIBSTDCXX "stdcxx" - -/* Warn that -mbnu210 is now obsolete. */ -#undef SUBTARGET_OVERRIDE_OPTIONS -#define SUBTARGET_OVERRIDE_OPTIONS \ -do \ - { \ - if (TARGET_BNU210) \ - { \ - warning (0, "-mbnu210 is ignored (option is obsolete)"); \ - } \ - } \ -while (0) +#undef DBX_REGISTER_NUMBER +#define DBX_REGISTER_NUMBER(n) svr4_dbx_register_map[n] + +/* Default to pcc-struct-return. */ +#define DEFAULT_PCC_STRUCT_RETURN 1 + +/* Ignore (with warning) -fPIC for DJGPP */ +#undef SUBTARGET_OVERRIDE_OPTIONS +#define SUBTARGET_OVERRIDE_OPTIONS \ + do { \ + if (flag_pic) \ + { \ + fnotice(stdout, "-f%s ignored (not supported for DJGPP)\n", \ + (flag_pic > 1) ? "PIC" : "pic"); \ + flag_pic = 0; \ + } \ + \ + /* Don't emit DWARF3/4 unless specifically selected. */ \ + /* DWARF3/4 currently does not work for DJGPP. */ \ + if (!global_options_set.x_dwarf_version) \ + dwarf_version = 2; \ + \ + } \ + while (0) /* Support for C++ templates. */ #undef MAKE_DECL_ONE_ONLY #define MAKE_DECL_ONE_ONLY(DECL) (DECL_WEAK (DECL) = 1) -#define IX86_MAYBE_NO_LIBGCC_TFMODE +/* Function protypes for gcc/i386/djgpp.c */ + +void +i386_djgpp_asm_named_section(const char *name, unsigned int flags, + tree decl); diff --git a/gcc/config/i386/djgpp.opt b/gcc/config/i386/djgpp.opt index d52c77dee85..b4ae04fdf12 100644 --- a/gcc/config/i386/djgpp.opt +++ b/gcc/config/i386/djgpp.opt @@ -1,6 +1,6 @@ ; DJGPP-specific options. -; Copyright (C) 2005-2015 Free Software Foundation, Inc. +; Copyright (C) 2005-2016 Free Software Foundation, Inc. ; ; This file is part of GCC. ; @@ -18,11 +18,5 @@ ; along with GCC; see the file COPYING3. If not see ; <http://www.gnu.org/licenses/>. -;; -mbnu210 is now ignored and obsolete. It was used to enable support for -;; weak symbols, and .gnu.linkonce support. -mbnu210 -Target Var(TARGET_BNU210) -Ignored (obsolete). - posix Driver diff --git a/gcc/config/i386/dragonfly.h b/gcc/config/i386/dragonfly.h index ab98429a967..8c68eff0d09 100644 --- a/gcc/config/i386/dragonfly.h +++ b/gcc/config/i386/dragonfly.h @@ -1,5 +1,5 @@ /* Definitions for Intel 386 running DragonFly with ELF format - Copyright (C) 2014-2015 Free Software Foundation, Inc. + Copyright (C) 2014-2016 Free Software Foundation, Inc. Contributed by John Marino <gnugcc@marino.st> This file is part of GCC. diff --git a/gcc/config/i386/driver-i386.c b/gcc/config/i386/driver-i386.c index 8ec1e40c2ac..b12146663e4 100644 --- a/gcc/config/i386/driver-i386.c +++ b/gcc/config/i386/driver-i386.c @@ -1,5 +1,5 @@ /* Subroutines for the gcc driver. - Copyright (C) 2006-2015 Free Software Foundation, Inc. + Copyright (C) 2006-2016 Free Software Foundation, Inc. This file is part of GCC. @@ -414,7 +414,7 @@ const char *host_detect_local_cpu (int argc, const char **argv) unsigned int has_avx512dq = 0, has_avx512bw = 0, has_avx512vl = 0; unsigned int has_avx512vbmi = 0, has_avx512ifma = 0, has_clwb = 0; unsigned int has_pcommit = 0, has_mwaitx = 0; - unsigned int has_clzero = 0; + unsigned int has_clzero = 0, has_pku = 0; bool arch; @@ -501,7 +501,8 @@ const char *host_detect_local_cpu (int argc, const char **argv) has_avx512vl = ebx & bit_AVX512IFMA; has_prefetchwt1 = ecx & bit_PREFETCHWT1; - has_avx512vl = ecx & bit_AVX512VBMI; + has_avx512vbmi = ecx & bit_AVX512VBMI; + has_pku = ecx & bit_OSPKE; } if (max_level >= 13) @@ -971,6 +972,7 @@ const char *host_detect_local_cpu (int argc, const char **argv) const char *pcommit = has_pcommit ? " -mpcommit" : " -mno-pcommit"; const char *mwaitx = has_mwaitx ? " -mmwaitx" : " -mno-mwaitx"; const char *clzero = has_clzero ? " -mclzero" : " -mno-clzero"; + const char *pku = has_pku ? " -mpku" : " -mno-pku"; options = concat (options, mmx, mmx3dnow, sse, sse2, sse3, ssse3, sse4a, cx16, sahf, movbe, aes, sha, pclmul, popcnt, abm, lwp, fma, fma4, xop, bmi, bmi2, @@ -980,7 +982,7 @@ const char *host_detect_local_cpu (int argc, const char **argv) avx512cd, avx512pf, prefetchwt1, clflushopt, xsavec, xsaves, avx512dq, avx512bw, avx512vl, avx512ifma, avx512vbmi, clwb, pcommit, mwaitx, - clzero, NULL); + clzero, pku, NULL); } done: diff --git a/gcc/config/i386/emmintrin.h b/gcc/config/i386/emmintrin.h index b19f05a1021..8652fe96d0e 100644 --- a/gcc/config/i386/emmintrin.h +++ b/gcc/config/i386/emmintrin.h @@ -1,4 +1,4 @@ -/* Copyright (C) 2003-2015 Free Software Foundation, Inc. +/* Copyright (C) 2003-2016 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/i386/f16cintrin.h b/gcc/config/i386/f16cintrin.h index d810a93914a..0d46d3b90f3 100644 --- a/gcc/config/i386/f16cintrin.h +++ b/gcc/config/i386/f16cintrin.h @@ -1,4 +1,4 @@ -/* Copyright (C) 2011-2015 Free Software Foundation, Inc. +/* Copyright (C) 2011-2016 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/i386/fma4intrin.h b/gcc/config/i386/fma4intrin.h index 06668e859a8..ecd4d1c9fd0 100644 --- a/gcc/config/i386/fma4intrin.h +++ b/gcc/config/i386/fma4intrin.h @@ -1,4 +1,4 @@ -/* Copyright (C) 2007-2015 Free Software Foundation, Inc. +/* Copyright (C) 2007-2016 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/i386/fmaintrin.h b/gcc/config/i386/fmaintrin.h index 9128b4d138b..d131d49e9a9 100644 --- a/gcc/config/i386/fmaintrin.h +++ b/gcc/config/i386/fmaintrin.h @@ -1,4 +1,4 @@ -/* Copyright (C) 2011-2015 Free Software Foundation, Inc. +/* Copyright (C) 2011-2016 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/i386/freebsd.h b/gcc/config/i386/freebsd.h index 78d5e198576..d66cf51bae9 100644 --- a/gcc/config/i386/freebsd.h +++ b/gcc/config/i386/freebsd.h @@ -1,5 +1,5 @@ /* Definitions for Intel 386 running FreeBSD with ELF format - Copyright (C) 1996-2015 Free Software Foundation, Inc. + Copyright (C) 1996-2016 Free Software Foundation, Inc. Contributed by Eric Youngdale. Modified for stabs-in-ELF by H.J. Lu. Adapted from GNU/Linux version by John Polstra. diff --git a/gcc/config/i386/freebsd64.h b/gcc/config/i386/freebsd64.h index 24cb221e5fa..8e0090018d1 100644 --- a/gcc/config/i386/freebsd64.h +++ b/gcc/config/i386/freebsd64.h @@ -1,5 +1,5 @@ /* Definitions for AMD x86-64 running FreeBSD with ELF format - Copyright (C) 2002-2015 Free Software Foundation, Inc. + Copyright (C) 2002-2016 Free Software Foundation, Inc. Contributed by David O'Brien <obrien@FreeBSD.org> This file is part of GCC. diff --git a/gcc/config/i386/fxsrintrin.h b/gcc/config/i386/fxsrintrin.h index a3932e07506..b18b898c26a 100644 --- a/gcc/config/i386/fxsrintrin.h +++ b/gcc/config/i386/fxsrintrin.h @@ -1,4 +1,4 @@ -/* Copyright (C) 2012-2015 Free Software Foundation, Inc. +/* Copyright (C) 2012-2016 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/i386/gas.h b/gcc/config/i386/gas.h index 086ce5344f3..c2ae8b088c6 100644 --- a/gcc/config/i386/gas.h +++ b/gcc/config/i386/gas.h @@ -1,5 +1,5 @@ /* Definitions for Intel 386 using GAS. - Copyright (C) 1988-2015 Free Software Foundation, Inc. + Copyright (C) 1988-2016 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/i386/geode.md b/gcc/config/i386/geode.md index 9f1411db052..1cf0036a869 100644 --- a/gcc/config/i386/geode.md +++ b/gcc/config/i386/geode.md @@ -1,5 +1,5 @@ ;; Geode Scheduling -;; Copyright (C) 2006-2015 Free Software Foundation, Inc. +;; Copyright (C) 2006-2016 Free Software Foundation, Inc. ;; ;; This file is part of GCC. ;; diff --git a/gcc/config/i386/gmm_malloc.h b/gcc/config/i386/gmm_malloc.h index 52b853ceb2c..0582e0c444e 100644 --- a/gcc/config/i386/gmm_malloc.h +++ b/gcc/config/i386/gmm_malloc.h @@ -1,4 +1,4 @@ -/* Copyright (C) 2004-2015 Free Software Foundation, Inc. +/* Copyright (C) 2004-2016 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/i386/gnu-user-common.h b/gcc/config/i386/gnu-user-common.h index bd32fe2e667..6b7b0743aa3 100644 --- a/gcc/config/i386/gnu-user-common.h +++ b/gcc/config/i386/gnu-user-common.h @@ -1,5 +1,5 @@ /* Common definitions for Intel 386 and AMD x86-64 systems using - GNU userspace. Copyright (C) 2012-2015 Free Software Foundation, Inc. + GNU userspace. Copyright (C) 2012-2016 Free Software Foundation, Inc. Contributed by Ilya Enkovich. This file is part of GCC. diff --git a/gcc/config/i386/gnu-user.h b/gcc/config/i386/gnu-user.h index 0d001e22f9e..fee33a3efdc 100644 --- a/gcc/config/i386/gnu-user.h +++ b/gcc/config/i386/gnu-user.h @@ -1,5 +1,5 @@ /* Definitions for Intel 386 systems using GNU userspace. - Copyright (C) 1994-2015 Free Software Foundation, Inc. + Copyright (C) 1994-2016 Free Software Foundation, Inc. Contributed by Eric Youngdale. Modified for stabs-in-ELF by H.J. Lu. diff --git a/gcc/config/i386/gnu-user64.h b/gcc/config/i386/gnu-user64.h index 734310f8f56..7a02a7eb4d7 100644 --- a/gcc/config/i386/gnu-user64.h +++ b/gcc/config/i386/gnu-user64.h @@ -1,5 +1,5 @@ /* Definitions for AMD x86-64 using GNU userspace. - Copyright (C) 2001-2015 Free Software Foundation, Inc. + Copyright (C) 2001-2016 Free Software Foundation, Inc. Contributed by Jan Hubicka <jh@suse.cz>, based on linux.h. This file is part of GCC. diff --git a/gcc/config/i386/gnu.h b/gcc/config/i386/gnu.h index 8892a4f4455..c726d31f496 100644 --- a/gcc/config/i386/gnu.h +++ b/gcc/config/i386/gnu.h @@ -1,7 +1,7 @@ /* Configuration for an i386 running GNU with ELF as the target machine. */ /* -Copyright (C) 1994-2015 Free Software Foundation, Inc. +Copyright (C) 1994-2016 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/i386/haswell.md b/gcc/config/i386/haswell.md index 2bb0ac9873c..1f49c237ae7 100644 --- a/gcc/config/i386/haswell.md +++ b/gcc/config/i386/haswell.md @@ -1,5 +1,5 @@ ;; Scheduling for Haswell and derived processors. -;; Copyright (C) 2004-2015 Free Software Foundation, Inc. +;; Copyright (C) 2004-2016 Free Software Foundation, Inc. ;; ;; This file is part of GCC. ;; diff --git a/gcc/config/i386/host-cygwin.c b/gcc/config/i386/host-cygwin.c index b62cdeeab12..dd59ab99c92 100644 --- a/gcc/config/i386/host-cygwin.c +++ b/gcc/config/i386/host-cygwin.c @@ -1,5 +1,5 @@ /* Cygwin host-specific hook definitions. - Copyright (C) 2004-2015 Free Software Foundation, Inc. + Copyright (C) 2004-2016 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/i386/host-i386-darwin.c b/gcc/config/i386/host-i386-darwin.c index 9c948f560b6..6283696902d 100644 --- a/gcc/config/i386/host-i386-darwin.c +++ b/gcc/config/i386/host-i386-darwin.c @@ -1,5 +1,5 @@ /* i386-darwin host-specific hook definitions. - Copyright (C) 2003-2015 Free Software Foundation, Inc. + Copyright (C) 2003-2016 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/i386/host-mingw32.c b/gcc/config/i386/host-mingw32.c index 7eb47cc51ee..f51219abfd6 100644 --- a/gcc/config/i386/host-mingw32.c +++ b/gcc/config/i386/host-mingw32.c @@ -1,5 +1,5 @@ /* mingw32 host-specific hook definitions. - Copyright (C) 2004-2015 Free Software Foundation, Inc. + Copyright (C) 2004-2016 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/i386/i386-builtin-types.awk b/gcc/config/i386/i386-builtin-types.awk index 944c7a400d7..1825e9f7b44 100644 --- a/gcc/config/i386/i386-builtin-types.awk +++ b/gcc/config/i386/i386-builtin-types.awk @@ -1,4 +1,4 @@ -# Copyright (C) 2009-2015 Free Software Foundation, Inc. +# Copyright (C) 2009-2016 Free Software Foundation, Inc. # # This program is free software; you can redistribute it and/or modify it # under the terms of the GNU General Public License as published by the diff --git a/gcc/config/i386/i386-c.c b/gcc/config/i386/i386-c.c index 0f3c3ec452c..ea0c5df059f 100644 --- a/gcc/config/i386/i386-c.c +++ b/gcc/config/i386/i386-c.c @@ -1,5 +1,5 @@ /* Subroutines used for macro/preprocessor support on the ia-32. - Copyright (C) 2008-2015 Free Software Foundation, Inc. + Copyright (C) 2008-2016 Free Software Foundation, Inc. This file is part of GCC. @@ -439,8 +439,8 @@ ix86_target_macros_internal (HOST_WIDE_INT isa_flag, def_or_undef (parse_in, "__CLWB__"); if (isa_flag & OPTION_MASK_ISA_MWAITX) def_or_undef (parse_in, "__MWAITX__"); - if (isa_flag & OPTION_MASK_ISA_CLZERO) - def_or_undef (parse_in, "__CLZERO__"); + if (isa_flag & OPTION_MASK_ISA_PKU) + def_or_undef (parse_in, "__PKU__"); if (TARGET_IAMCU) { def_or_undef (parse_in, "__iamcu"); diff --git a/gcc/config/i386/i386-interix.h b/gcc/config/i386/i386-interix.h index 97dbcd97ef5..7d4b8721ecd 100644 --- a/gcc/config/i386/i386-interix.h +++ b/gcc/config/i386/i386-interix.h @@ -1,5 +1,5 @@ /* Target definitions for GCC for Intel 80386 running Interix - Parts Copyright (C) 1991-2015 Free Software Foundation, Inc. + Parts Copyright (C) 1991-2016 Free Software Foundation, Inc. Parts: by Douglas B. Rupp (drupp@cs.washington.edu). diff --git a/gcc/config/i386/i386-modes.def b/gcc/config/i386/i386-modes.def index 714c138cc6a..d524313adc3 100644 --- a/gcc/config/i386/i386-modes.def +++ b/gcc/config/i386/i386-modes.def @@ -1,5 +1,5 @@ /* Definitions of target machine for GCC for IA-32. - Copyright (C) 2002-2015 Free Software Foundation, Inc. + Copyright (C) 2002-2016 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/i386/i386-opts.h b/gcc/config/i386/i386-opts.h index 960f1d89e76..b7f92e3bea1 100644 --- a/gcc/config/i386/i386-opts.h +++ b/gcc/config/i386/i386-opts.h @@ -1,5 +1,5 @@ /* Definitions for option handling for IA-32. - Copyright (C) 1988-2015 Free Software Foundation, Inc. + Copyright (C) 1988-2016 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/i386/i386-protos.h b/gcc/config/i386/i386-protos.h index bd084dc9714..252bb192aa7 100644 --- a/gcc/config/i386/i386-protos.h +++ b/gcc/config/i386/i386-protos.h @@ -1,5 +1,5 @@ /* Definitions of target machine for GCC for IA-32. - Copyright (C) 1988-2015 Free Software Foundation, Inc. + Copyright (C) 1988-2016 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c index cecea2496a9..92d8ee1a88f 100644 --- a/gcc/config/i386/i386.c +++ b/gcc/config/i386/i386.c @@ -1,5 +1,5 @@ /* Subroutines used for code generation on IA-32. - Copyright (C) 1988-2015 Free Software Foundation, Inc. + Copyright (C) 1988-2016 Free Software Foundation, Inc. This file is part of GCC. @@ -2815,7 +2815,11 @@ scalar_to_vector_candidate_p (rtx_insn *insn) return false; } - if (!REG_P (XEXP (src, 0)) && !MEM_P (XEXP (src, 0))) + if (!REG_P (XEXP (src, 0)) && !MEM_P (XEXP (src, 0)) + /* Check for andnot case. */ + && (GET_CODE (src) != AND + || GET_CODE (XEXP (src, 0)) != NOT + || !REG_P (XEXP (XEXP (src, 0), 0)))) return false; if (!REG_P (XEXP (src, 1)) && !MEM_P (XEXP (src, 1))) @@ -3150,13 +3154,13 @@ scalar_chain::compute_convert_gain () } if (dump_file) - fprintf (dump_file, " Instruction convertion gain: %d\n", gain); + fprintf (dump_file, " Instruction conversion gain: %d\n", gain); EXECUTE_IF_SET_IN_BITMAP (defs_conv, 0, insn_uid, bi) cost += DF_REG_DEF_COUNT (insn_uid) * ix86_cost->mmxsse_to_integer; if (dump_file) - fprintf (dump_file, " Registers convertion cost: %d\n", cost); + fprintf (dump_file, " Registers conversion cost: %d\n", cost); gain -= cost; @@ -3383,7 +3387,12 @@ scalar_chain::convert_op (rtx *op, rtx_insn *insn) { *op = copy_rtx_if_shared (*op); - if (MEM_P (*op)) + if (GET_CODE (*op) == NOT) + { + convert_op (&XEXP (*op, 0), insn); + PUT_MODE (*op, V2DImode); + } + else if (MEM_P (*op)) { rtx tmp = gen_reg_rtx (DImode); @@ -3531,7 +3540,7 @@ convert_scalars_to_vector () /* Find all instructions we want to convert into vector mode. */ if (dump_file) - fprintf (dump_file, "Searching for mode convertion candidates...\n"); + fprintf (dump_file, "Searching for mode conversion candidates...\n"); FOR_EACH_BB_FN (bb, cfun) { @@ -3755,6 +3764,7 @@ ix86_target_string (HOST_WIDE_INT isa, int flags, const char *arch, { "-mpcommit", OPTION_MASK_ISA_PCOMMIT }, { "-mmwaitx", OPTION_MASK_ISA_MWAITX }, { "-mclzero", OPTION_MASK_ISA_CLZERO }, + { "-mpku", OPTION_MASK_ISA_PKU }, }; /* Flag options. */ @@ -4310,6 +4320,7 @@ ix86_option_override_internal (bool main_args_p, #define PTA_MWAITX (HOST_WIDE_INT_1 << 57) #define PTA_CLZERO (HOST_WIDE_INT_1 << 58) #define PTA_NO_80387 (HOST_WIDE_INT_1 << 59) +#define PTA_PKU (HOST_WIDE_INT_1 << 60) #define PTA_CORE2 \ (PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3 | PTA_SSSE3 \ @@ -4331,7 +4342,7 @@ ix86_option_override_internal (bool main_args_p, (PTA_BROADWELL | PTA_CLFLUSHOPT | PTA_XSAVEC | PTA_XSAVES) #define PTA_SKYLAKE_AVX512 \ (PTA_SKYLAKE | PTA_AVX512F | PTA_AVX512CD | PTA_AVX512VL \ - | PTA_AVX512BW | PTA_AVX512DQ) + | PTA_AVX512BW | PTA_AVX512DQ | PTA_PKU) #define PTA_KNL \ (PTA_BROADWELL | PTA_AVX512PF | PTA_AVX512ER | PTA_AVX512F | PTA_AVX512CD) #define PTA_BONNELL \ @@ -4934,6 +4945,9 @@ ix86_option_override_internal (bool main_args_p, if (processor_alias_table[i].flags & PTA_MWAITX && !(opts->x_ix86_isa_flags_explicit & OPTION_MASK_ISA_MWAITX)) opts->x_ix86_isa_flags |= OPTION_MASK_ISA_MWAITX; + if (processor_alias_table[i].flags & PTA_PKU + && !(opts->x_ix86_isa_flags_explicit & OPTION_MASK_ISA_PKU)) + opts->x_ix86_isa_flags |= OPTION_MASK_ISA_PKU; if (!(opts_set->x_target_flags & MASK_80387)) { @@ -5338,6 +5352,13 @@ ix86_option_override_internal (bool main_args_p, opts->x_param_values, opts_set->x_param_values); + /* Restrict number of if-converted SET insns to 1. */ + if (TARGET_ONE_IF_CONV_INSN) + maybe_set_param_value (PARAM_MAX_RTL_IF_CONVERSION_INSNS, + 1, + opts->x_param_values, + opts_set->x_param_values); + /* Enable sw prefetching at -O3 for CPUS that prefetching is helpful. */ if (opts->x_flag_prefetch_loop_arrays < 0 && HAVE_prefetch @@ -5930,6 +5951,7 @@ ix86_valid_target_attribute_inner_p (tree args, char *p_strings[], IX86_ATTR_ISA ("pcommit", OPT_mpcommit), IX86_ATTR_ISA ("mwaitx", OPT_mmwaitx), IX86_ATTR_ISA ("clzero", OPT_mclzero), + IX86_ATTR_ISA ("pku", OPT_mpku), /* enum options */ IX86_ATTR_ENUM ("fpmath=", OPT_mfpmath_), @@ -6657,6 +6679,7 @@ ix86_function_ok_for_sibcall (tree decl, tree exp) { tree type, decl_or_type; rtx a, b; + bool bind_global = decl && !targetm.binds_local_p (decl); /* If we are generating position-independent code, we cannot sibcall optimize direct calls to global functions, as the PLT requires @@ -6665,7 +6688,7 @@ ix86_function_ok_for_sibcall (tree decl, tree exp) && !TARGET_64BIT && flag_pic && flag_plt - && decl && !targetm.binds_local_p (decl)) + && bind_global) return false; /* If we need to align the outgoing stack, then sibcalling would @@ -6723,8 +6746,10 @@ ix86_function_ok_for_sibcall (tree decl, tree exp) /* If this call is indirect, we'll need to be able to use a call-clobbered register for the address of the target function. Make sure that all such registers are not used for passing - parameters. Note that DLLIMPORT functions are indirect. */ + parameters. Note that DLLIMPORT functions and call to global + function via GOT slot are indirect. */ if (!decl + || (bind_global && flag_pic && !flag_plt) || (TARGET_DLLIMPORT_DECL_ATTRIBUTES && DECL_DLLIMPORT_P (decl))) { /* Check if regparm >= 3 since arg_reg_available is set to @@ -10894,6 +10919,10 @@ ix86_frame_pointer_required (void) if (TARGET_64BIT_MS_ABI && get_frame_size () > SEH_MAX_FRAME_SIZE) return true; + /* SSE saves require frame-pointer when stack is misaligned. */ + if (TARGET_64BIT_MS_ABI && ix86_incoming_stack_boundary < 128) + return true; + /* In ix86_option_override_internal, TARGET_OMIT_LEAF_FRAME_POINTER turns off the frame pointer by default. Turn it back on now if we've not got a leaf function. */ @@ -19350,11 +19379,11 @@ ix86_expand_vector_logical_operator (enum rtx_code code, machine_mode mode, { op1 = operands[1]; op2 = SUBREG_REG (operands[2]); - if (!nonimmediate_operand (op2, GET_MODE (dst))) + if (!vector_operand (op2, GET_MODE (dst))) op2 = force_reg (GET_MODE (dst), op2); } op1 = SUBREG_REG (op1); - if (!nonimmediate_operand (op1, GET_MODE (dst))) + if (!vector_operand (op1, GET_MODE (dst))) op1 = force_reg (GET_MODE (dst), op1); emit_insn (gen_rtx_SET (dst, gen_rtx_fmt_ee (code, GET_MODE (dst), @@ -19365,9 +19394,9 @@ ix86_expand_vector_logical_operator (enum rtx_code code, machine_mode mode, break; } } - if (!nonimmediate_operand (operands[1], mode)) + if (!vector_operand (operands[1], mode)) operands[1] = force_reg (mode, operands[1]); - if (!nonimmediate_operand (operands[2], mode)) + if (!vector_operand (operands[2], mode)) operands[2] = force_reg (mode, operands[2]); ix86_fixup_binary_operands_no_copy (code, mode, operands); emit_insn (gen_rtx_SET (operands[0], @@ -21679,6 +21708,19 @@ ix86_expand_branch (enum rtx_code code, rtx op0, rtx op1, rtx label) case DImode: if (TARGET_64BIT) goto simple; + /* For 32-bit target DI comparison may be performed on + SSE registers. To allow this we should avoid split + to SI mode which is achieved by doing xor in DI mode + and then comparing with zero (which is recognized by + STV pass). We don't compare using xor when optimizing + for size. */ + if (!optimize_insn_for_size_p () + && TARGET_STV + && (code == EQ || code == NE)) + { + op0 = force_reg (mode, gen_rtx_XOR (mode, op0, op1)); + op1 = const0_rtx; + } case TImode: /* Expand DImode branch into multiple compare+branch. */ { @@ -32283,6 +32325,10 @@ enum ix86_builtins IX86_BUILTIN_READ_FLAGS, IX86_BUILTIN_WRITE_FLAGS, + /* PKU instructions. */ + IX86_BUILTIN_RDPKRU, + IX86_BUILTIN_WRPKRU, + IX86_BUILTIN_MAX }; @@ -32788,6 +32834,10 @@ static const struct builtin_description bdesc_special_args[] = /* PCOMMIT. */ { OPTION_MASK_ISA_PCOMMIT, CODE_FOR_pcommit, "__builtin_ia32_pcommit", IX86_BUILTIN_PCOMMIT, UNKNOWN, (int) VOID_FTYPE_VOID }, + + /* RDPKRU and WRPKRU. */ + { OPTION_MASK_ISA_PKU, CODE_FOR_rdpkru, "__builtin_ia32_rdpkru", IX86_BUILTIN_RDPKRU, UNKNOWN, (int) UNSIGNED_FTYPE_VOID }, + { OPTION_MASK_ISA_PKU, CODE_FOR_wrpkru, "__builtin_ia32_wrpkru", IX86_BUILTIN_WRPKRU, UNKNOWN, (int) VOID_FTYPE_UNSIGNED } }; /* Builtins with variable number of arguments. */ @@ -35186,48 +35236,6 @@ static const struct builtin_description bdesc_tm[] = { OPTION_MASK_ISA_AVX, CODE_FOR_nothing, "__builtin__ITM_LM256", (enum ix86_builtins) BUILT_IN_TM_LOG_M256, UNKNOWN, VOID_FTYPE_PCVOID }, }; -/* TM callbacks. */ - -/* Return the builtin decl needed to load a vector of TYPE. */ - -static tree -ix86_builtin_tm_load (tree type) -{ - if (TREE_CODE (type) == VECTOR_TYPE) - { - switch (tree_to_uhwi (TYPE_SIZE (type))) - { - case 64: - return builtin_decl_explicit (BUILT_IN_TM_LOAD_M64); - case 128: - return builtin_decl_explicit (BUILT_IN_TM_LOAD_M128); - case 256: - return builtin_decl_explicit (BUILT_IN_TM_LOAD_M256); - } - } - return NULL_TREE; -} - -/* Return the builtin decl needed to store a vector of TYPE. */ - -static tree -ix86_builtin_tm_store (tree type) -{ - if (TREE_CODE (type) == VECTOR_TYPE) - { - switch (tree_to_uhwi (TYPE_SIZE (type))) - { - case 64: - return builtin_decl_explicit (BUILT_IN_TM_STORE_M64); - case 128: - return builtin_decl_explicit (BUILT_IN_TM_STORE_M128); - case 256: - return builtin_decl_explicit (BUILT_IN_TM_STORE_M256); - } - } - return NULL_TREE; -} - /* Initialize the transactional memory vector load/store builtins. */ static void @@ -39755,7 +39763,11 @@ ix86_expand_special_args_builtin (const struct builtin_description *d, memory = 0; break; case VOID_FTYPE_PV8DF_V8DF_UQI: + case VOID_FTYPE_PV4DF_V4DF_UQI: + case VOID_FTYPE_PV2DF_V2DF_UQI: case VOID_FTYPE_PV16SF_V16SF_UHI: + case VOID_FTYPE_PV8SF_V8SF_UQI: + case VOID_FTYPE_PV4SF_V4SF_UQI: case VOID_FTYPE_PV8DI_V8DI_UQI: case VOID_FTYPE_PV4DI_V4DI_UQI: case VOID_FTYPE_PV2DI_V2DI_UQI: @@ -39813,10 +39825,6 @@ ix86_expand_special_args_builtin (const struct builtin_description *d, case VOID_FTYPE_PV16QI_V16QI_UHI: case VOID_FTYPE_PV32QI_V32QI_USI: case VOID_FTYPE_PV64QI_V64QI_UDI: - case VOID_FTYPE_PV4DF_V4DF_UQI: - case VOID_FTYPE_PV2DF_V2DF_UQI: - case VOID_FTYPE_PV8SF_V8SF_UQI: - case VOID_FTYPE_PV4SF_V4SF_UQI: nargs = 2; klass = store; /* Reserve memory operand for target. */ @@ -41800,13 +41808,12 @@ rdseed_step: op0 = fixup_modeless_constant (op0, mode0); - if (GET_MODE (op0) == mode0 - || (GET_MODE (op0) == VOIDmode && op0 != constm1_rtx)) + if (GET_MODE (op0) == mode0 || GET_MODE (op0) == VOIDmode) { if (!insn_data[icode].operand[0].predicate (op0, mode0)) op0 = copy_to_mode_reg (mode0, op0); } - else if (op0 != constm1_rtx) + else { op0 = copy_to_reg (op0); op0 = simplify_gen_subreg (mode0, op0, GET_MODE (op0), 0); @@ -54313,12 +54320,6 @@ ix86_addr_space_zero_address_valid (addr_space_t as) #define TARGET_VECTORIZE_BUILTIN_VECTORIZED_FUNCTION \ ix86_builtin_vectorized_function -#undef TARGET_VECTORIZE_BUILTIN_TM_LOAD -#define TARGET_VECTORIZE_BUILTIN_TM_LOAD ix86_builtin_tm_load - -#undef TARGET_VECTORIZE_BUILTIN_TM_STORE -#define TARGET_VECTORIZE_BUILTIN_TM_STORE ix86_builtin_tm_store - #undef TARGET_VECTORIZE_BUILTIN_GATHER #define TARGET_VECTORIZE_BUILTIN_GATHER ix86_vectorize_builtin_gather diff --git a/gcc/config/i386/i386.h b/gcc/config/i386/i386.h index e69c9cc4563..9062d631165 100644 --- a/gcc/config/i386/i386.h +++ b/gcc/config/i386/i386.h @@ -1,5 +1,5 @@ /* Definitions of target machine for GCC for IA-32. - Copyright (C) 1988-2015 Free Software Foundation, Inc. + Copyright (C) 1988-2016 Free Software Foundation, Inc. This file is part of GCC. @@ -158,6 +158,9 @@ see the files COPYING3 and COPYING.RUNTIME respectively. If not, see #define TARGET_CLWB_P(x) TARGET_ISA_CLWB_P(x) #define TARGET_MWAITX TARGET_ISA_MWAITX #define TARGET_MWAITX_P(x) TARGET_ISA_MWAITX_P(x) +#define TARGET_PKU TARGET_ISA_PKU +#define TARGET_PKU_P(x) TARGET_ISA_PKU_P(x) + #define TARGET_LP64 TARGET_ABI_64 #define TARGET_LP64_P(x) TARGET_ABI_64_P(x) @@ -496,6 +499,8 @@ extern unsigned char ix86_tune_features[X86_TUNE_LAST]; ix86_tune_features[X86_TUNE_ADJUST_UNROLL] #define TARGET_AVOID_FALSE_DEP_FOR_BMI \ ix86_tune_features[X86_TUNE_AVOID_FALSE_DEP_FOR_BMI] +#define TARGET_ONE_IF_CONV_INSN \ + ix86_tune_features[X86_TUNE_ONE_IF_CONV_INSN] /* Feature tests against the various architecture variations. */ enum ix86_arch_indices { @@ -688,8 +693,11 @@ extern const char *host_detect_local_cpu (int argc, const char **argv); only SSE, rounding is correct; when using both SSE and the FPU, the rounding precision is indeterminate, since either may be chosen apparently at random. */ -#define TARGET_FLT_EVAL_METHOD \ - (TARGET_MIX_SSE_I387 ? -1 : TARGET_SSE_MATH ? 0 : 2) +#define TARGET_FLT_EVAL_METHOD \ + (TARGET_80387 \ + ? (TARGET_MIX_SSE_I387 ? -1 \ + : (TARGET_SSE_MATH ? (TARGET_SSE2 ? 0 : -1) : 2)) \ + : 0) /* Whether to allow x87 floating-point arithmetic on MODE (one of SFmode, DFmode and XFmode) in the current excess precision diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md index 49b221665fd..f16b42ab884 100644 --- a/gcc/config/i386/i386.md +++ b/gcc/config/i386/i386.md @@ -1,5 +1,5 @@ ;; GCC machine description for IA-32 and x86-64. -;; Copyright (C) 1988-2015 Free Software Foundation, Inc. +;; Copyright (C) 1988-2016 Free Software Foundation, Inc. ;; Mostly by William Schelter. ;; x86_64 support added by Jan Hubicka ;; @@ -268,6 +268,8 @@ ;; For CLZERO support UNSPECV_CLZERO + ;; For RDPKRU and WRPKRU support + UNSPECV_PKU ]) ;; Constants to represent rounding modes in the ROUND instruction @@ -7868,7 +7870,7 @@ ;; Combine likes to form bit extractions for some tests. Humor it. (define_insn "*testqi_ext_3" [(set (reg FLAGS_REG) - (compare (zero_extract:SWI48 + (compare (zero_extract:SWI248 (match_operand 0 "nonimmediate_operand" "rm") (match_operand 1 "const_int_operand" "n") (match_operand 2 "const_int_operand" "n")) @@ -8643,6 +8645,23 @@ (clobber (reg:CC FLAGS_REG))])] "split_double_mode (DImode, &operands[0], 3, &operands[0], &operands[3]);") +(define_insn_and_split "*andndi3_doubleword" + [(set (match_operand:DI 0 "register_operand" "=r,r") + (and:DI + (not:DI (match_operand:DI 1 "register_operand" "r,r")) + (match_operand:DI 2 "nonimmediate_operand" "r,m"))) + (clobber (reg:CC FLAGS_REG))] + "TARGET_BMI && !TARGET_64BIT && TARGET_STV && TARGET_SSE" + "#" + "&& reload_completed" + [(parallel [(set (match_dup 0) + (and:SI (not:SI (match_dup 1)) (match_dup 2))) + (clobber (reg:CC FLAGS_REG))]) + (parallel [(set (match_dup 3) + (and:SI (not:SI (match_dup 4)) (match_dup 5))) + (clobber (reg:CC FLAGS_REG))])] + "split_double_mode (DImode, &operands[0], 3, &operands[0], &operands[3]);") + (define_insn "*<code>hi_1" [(set (match_operand:HI 0 "nonimmediate_operand" "=r,rm,!k") (any_or:HI @@ -11865,6 +11884,22 @@ "* return ix86_output_call_insn (insn, operands[0]);" [(set_attr "type" "call")]) +;; Since sibcall never returns, we can only use call-clobbered register +;; as GOT base. +(define_insn "*sibcall_GOT_32" + [(call (mem:QI + (mem:SI (plus:SI + (match_operand:SI 0 "register_no_elim_operand" "U") + (match_operand:SI 1 "GOT32_symbol_operand")))) + (match_operand 2))] + "!TARGET_MACHO && !TARGET_64BIT && SIBLING_CALL_P (insn)" +{ + rtx fnaddr = gen_rtx_PLUS (Pmode, operands[0], operands[1]); + fnaddr = gen_const_mem (Pmode, fnaddr); + return ix86_output_call_insn (insn, fnaddr); +} + [(set_attr "type" "call")]) + (define_insn "*sibcall" [(call (mem:QI (match_operand:W 0 "sibcall_insn_operand" "UBsBz")) (match_operand 1))] @@ -12042,6 +12077,23 @@ "* return ix86_output_call_insn (insn, operands[1]);" [(set_attr "type" "callv")]) +;; Since sibcall never returns, we can only use call-clobbered register +;; as GOT base. +(define_insn "*sibcall_value_GOT_32" + [(set (match_operand 0) + (call (mem:QI + (mem:SI (plus:SI + (match_operand:SI 1 "register_no_elim_operand" "U") + (match_operand:SI 2 "GOT32_symbol_operand")))) + (match_operand 3)))] + "!TARGET_MACHO && !TARGET_64BIT && SIBLING_CALL_P (insn)" +{ + rtx fnaddr = gen_rtx_PLUS (Pmode, operands[1], operands[2]); + fnaddr = gen_const_mem (Pmode, fnaddr); + return ix86_output_call_insn (insn, fnaddr); +} + [(set_attr "type" "callv")]) + (define_insn "*sibcall_value" [(set (match_operand 0) (call (mem:QI (match_operand:W 1 "sibcall_insn_operand" "UBsBz")) @@ -19287,6 +19339,48 @@ [(set_attr "type" "imov") (set_attr "mode" "<MODE>")]) +;; RDPKRU and WRPKRU + +(define_expand "rdpkru" + [(parallel + [(set (match_operand:SI 0 "register_operand") + (unspec_volatile:SI [(match_dup 1)] UNSPECV_PKU)) + (set (match_dup 2) (const_int 0))])] + "TARGET_PKU" +{ + operands[1] = force_reg (SImode, const0_rtx); + operands[2] = gen_reg_rtx (SImode); +}) + +(define_insn "*rdpkru" + [(set (match_operand:SI 0 "register_operand" "=a") + (unspec_volatile:SI [(match_operand:SI 2 "register_operand" "c")] + UNSPECV_PKU)) + (set (match_operand:SI 1 "register_operand" "=d") + (const_int 0))] + "TARGET_PKU" + "rdpkru" + [(set_attr "type" "other")]) + +(define_expand "wrpkru" + [(unspec_volatile:SI + [(match_operand:SI 0 "register_operand") + (match_dup 1) (match_dup 2)] UNSPECV_PKU)] + "TARGET_PKU" +{ + operands[1] = force_reg (SImode, const0_rtx); + operands[2] = force_reg (SImode, const0_rtx); +}) + +(define_insn "*wrpkru" + [(unspec_volatile:SI + [(match_operand:SI 0 "register_operand" "a") + (match_operand:SI 1 "register_operand" "d") + (match_operand:SI 2 "register_operand" "c")] UNSPECV_PKU)] + "TARGET_PKU" + "wrpkru" + [(set_attr "type" "other")]) + (include "mmx.md") (include "sse.md") (include "sync.md") diff --git a/gcc/config/i386/i386.opt b/gcc/config/i386/i386.opt index 730b753ba4b..36dd4bd1572 100644 --- a/gcc/config/i386/i386.opt +++ b/gcc/config/i386/i386.opt @@ -1,6 +1,6 @@ ; Options for the IA-32 and AMD64 ports of the compiler. -; Copyright (C) 2005-2015 Free Software Foundation, Inc. +; Copyright (C) 2005-2016 Free Software Foundation, Inc. ; ; This file is part of GCC. ; @@ -876,6 +876,10 @@ mclzero Target Report Mask(ISA_CLZERO) Var(ix86_isa_flags) Save Support CLZERO built-in functions and code generation. +mpku +Target Report Mask(ISA_PKU) Var(ix86_isa_flags) Save +Support PKU built-in functions and code generation. + mstack-protector-guard= Target RejectNegative Joined Enum(stack_protector_guard) Var(ix86_stack_protector_guard) Init(SSP_TLS) Use given stack-protector guard. diff --git a/gcc/config/i386/i386elf.h b/gcc/config/i386/i386elf.h index aed5e045083..e2a6a10d600 100644 --- a/gcc/config/i386/i386elf.h +++ b/gcc/config/i386/i386elf.h @@ -1,5 +1,5 @@ /* Target definitions for GCC for Intel 80386 using ELF - Copyright (C) 1988-2015 Free Software Foundation, Inc. + Copyright (C) 1988-2016 Free Software Foundation, Inc. Derived from sysv4.h written by Ron Guilmette (rfg@netcom.com). diff --git a/gcc/config/i386/ia32intrin.h b/gcc/config/i386/ia32intrin.h index b8d1c315dd4..650c93820a1 100644 --- a/gcc/config/i386/ia32intrin.h +++ b/gcc/config/i386/ia32intrin.h @@ -1,4 +1,4 @@ -/* Copyright (C) 2009-2015 Free Software Foundation, Inc. +/* Copyright (C) 2009-2016 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/i386/iamcu.h b/gcc/config/i386/iamcu.h index c20c2db6910..e16c9d63a7c 100644 --- a/gcc/config/i386/iamcu.h +++ b/gcc/config/i386/iamcu.h @@ -1,5 +1,5 @@ /* Definitions of target machine for Intel MCU psABI. - Copyright (C) 2015 Free Software Foundation, Inc. + Copyright (C) 2015-2016 Free Software Foundation, Inc. This file is part of GCC. @@ -94,3 +94,19 @@ see the files COPYING3 and COPYING.RUNTIME respectively. If not, see goto DONE; \ } \ } while (0) + +#undef SIZE_TYPE +#define SIZE_TYPE "unsigned int" + +#undef PTRDIFF_TYPE +#define PTRDIFF_TYPE "int" + +#undef WCHAR_TYPE +#define WCHAR_TYPE "long int" + +#undef WCHAR_TYPE_SIZE +#define WCHAR_TYPE_SIZE BITS_PER_WORD + +/* Use int, instead of long int, for int32_t and uint32_t. */ +#undef STDINT_LONG32 +#define STDINT_LONG32 0 diff --git a/gcc/config/i386/immintrin.h b/gcc/config/i386/immintrin.h index a1e9c3c07da..93331113d97 100644 --- a/gcc/config/i386/immintrin.h +++ b/gcc/config/i386/immintrin.h @@ -1,4 +1,4 @@ -/* Copyright (C) 2008-2015 Free Software Foundation, Inc. +/* Copyright (C) 2008-2016 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/i386/intelmic-mkoffload.c b/gcc/config/i386/intelmic-mkoffload.c index 828b415015e..a78e48c0eb6 100644 --- a/gcc/config/i386/intelmic-mkoffload.c +++ b/gcc/config/i386/intelmic-mkoffload.c @@ -1,6 +1,6 @@ /* Offload image generation tool for Intel MIC devices. - Copyright (C) 2014-2015 Free Software Foundation, Inc. + Copyright (C) 2014-2016 Free Software Foundation, Inc. Contributed by Ilya Verbin <ilya.verbin@intel.com>. diff --git a/gcc/config/i386/intelmic-offload.h b/gcc/config/i386/intelmic-offload.h index 4fb4b65aa91..12aca578af2 100644 --- a/gcc/config/i386/intelmic-offload.h +++ b/gcc/config/i386/intelmic-offload.h @@ -1,6 +1,6 @@ /* Support for Intel MIC offloading. - Copyright (C) 2014-2015 Free Software Foundation, Inc. + Copyright (C) 2014-2016 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/i386/interix.opt b/gcc/config/i386/interix.opt index 04de55b1c2e..bd65432fe59 100644 --- a/gcc/config/i386/interix.opt +++ b/gcc/config/i386/interix.opt @@ -1,6 +1,6 @@ ; Interix-specific options. -; Copyright (C) 2005-2015 Free Software Foundation, Inc. +; Copyright (C) 2005-2016 Free Software Foundation, Inc. ; ; This file is part of GCC. ; diff --git a/gcc/config/i386/k6.md b/gcc/config/i386/k6.md index bbdc5d8c218..8118b3c9cc4 100644 --- a/gcc/config/i386/k6.md +++ b/gcc/config/i386/k6.md @@ -1,5 +1,5 @@ ;; AMD K6/K6-2 Scheduling -;; Copyright (C) 2002-2015 Free Software Foundation, Inc. +;; Copyright (C) 2002-2016 Free Software Foundation, Inc. ;; ;; This file is part of GCC. ;; diff --git a/gcc/config/i386/kfreebsd-gnu.h b/gcc/config/i386/kfreebsd-gnu.h index d7b88a0738f..97be2184106 100644 --- a/gcc/config/i386/kfreebsd-gnu.h +++ b/gcc/config/i386/kfreebsd-gnu.h @@ -1,5 +1,5 @@ /* Definitions for Intel 386 running kFreeBSD-based GNU systems with ELF format - Copyright (C) 2011-2015 Free Software Foundation, Inc. + Copyright (C) 2011-2016 Free Software Foundation, Inc. Contributed by Robert Millan. This file is part of GCC. diff --git a/gcc/config/i386/kfreebsd-gnu64.h b/gcc/config/i386/kfreebsd-gnu64.h index da30cab2304..59d21a42b4f 100644 --- a/gcc/config/i386/kfreebsd-gnu64.h +++ b/gcc/config/i386/kfreebsd-gnu64.h @@ -1,5 +1,5 @@ /* Definitions for AMD x86-64 running kFreeBSD-based GNU systems with ELF format - Copyright (C) 2011-2015 Free Software Foundation, Inc. + Copyright (C) 2011-2016 Free Software Foundation, Inc. Contributed by Robert Millan. This file is part of GCC. diff --git a/gcc/config/i386/knetbsd-gnu.h b/gcc/config/i386/knetbsd-gnu.h index 86a6833d29f..51f8a0c4609 100644 --- a/gcc/config/i386/knetbsd-gnu.h +++ b/gcc/config/i386/knetbsd-gnu.h @@ -1,5 +1,5 @@ /* Definitions for Intel 386 running kNetBSD-based GNU systems with ELF format - Copyright (C) 2004-2015 Free Software Foundation, Inc. + Copyright (C) 2004-2016 Free Software Foundation, Inc. Contributed by Robert Millan. This file is part of GCC. diff --git a/gcc/config/i386/knetbsd-gnu64.h b/gcc/config/i386/knetbsd-gnu64.h index d621bbee6a4..fb9e2c0cdf0 100644 --- a/gcc/config/i386/knetbsd-gnu64.h +++ b/gcc/config/i386/knetbsd-gnu64.h @@ -1,6 +1,5 @@ /* Definitions for AMD x86-64 running kNetBSD-based GNU systems with ELF format - Copyright (C) 2012 - Free Software Foundation, Inc. + Copyright (C) 2012-2016 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/i386/kopensolaris-gnu.h b/gcc/config/i386/kopensolaris-gnu.h index 03b8de26433..a9deb5087d0 100644 --- a/gcc/config/i386/kopensolaris-gnu.h +++ b/gcc/config/i386/kopensolaris-gnu.h @@ -1,5 +1,5 @@ /* Definitions for Intel 386 running kOpenSolaris-based GNU systems with ELF format - Copyright (C) 2009-2015 Free Software Foundation, Inc. + Copyright (C) 2009-2016 Free Software Foundation, Inc. Contributed by Robert Millan. This file is part of GCC. diff --git a/gcc/config/i386/linux-common.h b/gcc/config/i386/linux-common.h index 7617490a119..4b9910fa902 100644 --- a/gcc/config/i386/linux-common.h +++ b/gcc/config/i386/linux-common.h @@ -1,5 +1,5 @@ /* Definitions for Intel 386 running Linux-based GNU systems with ELF format. - Copyright (C) 2012-2015 Free Software Foundation, Inc. + Copyright (C) 2012-2016 Free Software Foundation, Inc. Contributed by Ilya Enkovich. This file is part of GCC. diff --git a/gcc/config/i386/linux.h b/gcc/config/i386/linux.h index 385aefd046b..d37a875ed6f 100644 --- a/gcc/config/i386/linux.h +++ b/gcc/config/i386/linux.h @@ -1,5 +1,5 @@ /* Definitions for Intel 386 running Linux-based GNU systems with ELF format. - Copyright (C) 1994-2015 Free Software Foundation, Inc. + Copyright (C) 1994-2016 Free Software Foundation, Inc. Contributed by Eric Youngdale. Modified for stabs-in-ELF by H.J. Lu. diff --git a/gcc/config/i386/linux64.h b/gcc/config/i386/linux64.h index e300480fc70..73d22e357cf 100644 --- a/gcc/config/i386/linux64.h +++ b/gcc/config/i386/linux64.h @@ -1,5 +1,5 @@ /* Definitions for AMD x86-64 running Linux-based GNU systems with ELF format. - Copyright (C) 2001-2015 Free Software Foundation, Inc. + Copyright (C) 2001-2016 Free Software Foundation, Inc. Contributed by Jan Hubicka <jh@suse.cz>, based on linux.h. This file is part of GCC. diff --git a/gcc/config/i386/lwpintrin.h b/gcc/config/i386/lwpintrin.h index 714b565b4b4..1ffac23e1d2 100644 --- a/gcc/config/i386/lwpintrin.h +++ b/gcc/config/i386/lwpintrin.h @@ -1,4 +1,4 @@ -/* Copyright (C) 2007-2015 Free Software Foundation, Inc. +/* Copyright (C) 2007-2016 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/i386/lynx.h b/gcc/config/i386/lynx.h index aa7980ef4e2..6c4fec6264e 100644 --- a/gcc/config/i386/lynx.h +++ b/gcc/config/i386/lynx.h @@ -1,5 +1,5 @@ /* Definitions for LynxOS on i386. - Copyright (C) 1993-2015 Free Software Foundation, Inc. + Copyright (C) 1993-2016 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/i386/lzcntintrin.h b/gcc/config/i386/lzcntintrin.h index 9f9f145c4bd..413267ac21c 100644 --- a/gcc/config/i386/lzcntintrin.h +++ b/gcc/config/i386/lzcntintrin.h @@ -1,4 +1,4 @@ -/* Copyright (C) 2009-2015 Free Software Foundation, Inc. +/* Copyright (C) 2009-2016 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/i386/mingw-pthread.h b/gcc/config/i386/mingw-pthread.h index 56af1244430..9c1413c8dd2 100644 --- a/gcc/config/i386/mingw-pthread.h +++ b/gcc/config/i386/mingw-pthread.h @@ -1,6 +1,6 @@ /* Defines that pthread library shall be enabled by default for target. - Copyright (C) 2011-2015 Free Software Foundation, Inc. + Copyright (C) 2011-2016 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/i386/mingw-stdint.h b/gcc/config/i386/mingw-stdint.h index 5fee1b62c2d..d53290e739d 100644 --- a/gcc/config/i386/mingw-stdint.h +++ b/gcc/config/i386/mingw-stdint.h @@ -1,5 +1,5 @@ /* Definitions for <stdint.h> types on systems using mingw. - Copyright (C) 2009-2015 Free Software Foundation, Inc. + Copyright (C) 2009-2016 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/i386/mingw-w64.h b/gcc/config/i386/mingw-w64.h index 578a7b7c699..fe11333a2d1 100644 --- a/gcc/config/i386/mingw-w64.h +++ b/gcc/config/i386/mingw-w64.h @@ -1,7 +1,7 @@ /* Operating system specific defines to be used when targeting GCC for hosting on Windows 32/64 via mingw-w64 runtime, using GNU tools and the Windows API Library. - Copyright (C) 2009-2015 Free Software Foundation, Inc. + Copyright (C) 2009-2016 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/i386/mingw-w64.opt b/gcc/config/i386/mingw-w64.opt index 40f06c3e30c..6d82c1d6be1 100644 --- a/gcc/config/i386/mingw-w64.opt +++ b/gcc/config/i386/mingw-w64.opt @@ -1,6 +1,6 @@ ; MinGW-w64-specific options. -; Copyright (C) 2009-2015 Free Software Foundation, Inc. +; Copyright (C) 2009-2016 Free Software Foundation, Inc. ; ; This file is part of GCC. ; diff --git a/gcc/config/i386/mingw.opt b/gcc/config/i386/mingw.opt index 03c7a14703f..bdb91581431 100644 --- a/gcc/config/i386/mingw.opt +++ b/gcc/config/i386/mingw.opt @@ -1,6 +1,6 @@ ; MinGW-specific options. -; Copyright (C) 2008-2015 Free Software Foundation, Inc. +; Copyright (C) 2008-2016 Free Software Foundation, Inc. ; ; This file is part of GCC. ; diff --git a/gcc/config/i386/mingw32.h b/gcc/config/i386/mingw32.h index eef90fb17aa..4ac5f688033 100644 --- a/gcc/config/i386/mingw32.h +++ b/gcc/config/i386/mingw32.h @@ -1,6 +1,6 @@ /* Operating system specific defines to be used when targeting GCC for hosting on Windows32, using GNU tools and the Windows32 API Library. - Copyright (C) 1997-2015 Free Software Foundation, Inc. + Copyright (C) 1997-2016 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/i386/mm3dnow.h b/gcc/config/i386/mm3dnow.h index 2a88997232d..f7371f76640 100644 --- a/gcc/config/i386/mm3dnow.h +++ b/gcc/config/i386/mm3dnow.h @@ -1,4 +1,4 @@ -/* Copyright (C) 2004-2015 Free Software Foundation, Inc. +/* Copyright (C) 2004-2016 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/i386/mmintrin.h b/gcc/config/i386/mmintrin.h index d0984735717..d5a1f00216d 100644 --- a/gcc/config/i386/mmintrin.h +++ b/gcc/config/i386/mmintrin.h @@ -1,4 +1,4 @@ -/* Copyright (C) 2002-2015 Free Software Foundation, Inc. +/* Copyright (C) 2002-2016 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/i386/mmx.md b/gcc/config/i386/mmx.md index 673ed7af123..a2e7231e1a9 100644 --- a/gcc/config/i386/mmx.md +++ b/gcc/config/i386/mmx.md @@ -1,5 +1,5 @@ ;; GCC machine description for MMX and 3dNOW! instructions -;; Copyright (C) 2005-2015 Free Software Foundation, Inc. +;; Copyright (C) 2005-2016 Free Software Foundation, Inc. ;; ;; This file is part of GCC. ;; diff --git a/gcc/config/i386/msformat-c.c b/gcc/config/i386/msformat-c.c index 1b05eac78b7..651f1db91b1 100644 --- a/gcc/config/i386/msformat-c.c +++ b/gcc/config/i386/msformat-c.c @@ -1,5 +1,5 @@ /* Check calls to formatted I/O functions (-Wformat). - Copyright (C) 1992-2015 Free Software Foundation, Inc. + Copyright (C) 1992-2016 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/i386/mwaitxintrin.h b/gcc/config/i386/mwaitxintrin.h index d7112dad205..270034d9249 100644 --- a/gcc/config/i386/mwaitxintrin.h +++ b/gcc/config/i386/mwaitxintrin.h @@ -1,4 +1,4 @@ -/* Copyright (C) 2012-2015 Free Software Foundation, Inc. +/* Copyright (C) 2012-2016 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/i386/netbsd-elf.h b/gcc/config/i386/netbsd-elf.h index 426441984b4..a6668200f05 100644 --- a/gcc/config/i386/netbsd-elf.h +++ b/gcc/config/i386/netbsd-elf.h @@ -1,6 +1,6 @@ /* Definitions of target machine for GCC, for i386/ELF NetBSD systems. - Copyright (C) 2001-2015 Free Software Foundation, Inc. + Copyright (C) 2001-2016 Free Software Foundation, Inc. Contributed by matthew green <mrg@eterna.com.au> This file is part of GCC. diff --git a/gcc/config/i386/netbsd64.h b/gcc/config/i386/netbsd64.h index 3d9c705316f..d1e2925ebcb 100644 --- a/gcc/config/i386/netbsd64.h +++ b/gcc/config/i386/netbsd64.h @@ -1,6 +1,6 @@ /* Definitions of target machine for GCC, for x86-64/ELF NetBSD systems. - Copyright (C) 2002-2015 Free Software Foundation, Inc. + Copyright (C) 2002-2016 Free Software Foundation, Inc. Contributed by Wasabi Systems, Inc. This file is part of GCC. diff --git a/gcc/config/i386/nmmintrin.h b/gcc/config/i386/nmmintrin.h index da9311e7606..9cb284747ac 100644 --- a/gcc/config/i386/nmmintrin.h +++ b/gcc/config/i386/nmmintrin.h @@ -1,4 +1,4 @@ -/* Copyright (C) 2007-2015 Free Software Foundation, Inc. +/* Copyright (C) 2007-2016 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/i386/nto.h b/gcc/config/i386/nto.h index 606311221f5..1866cf7141b 100644 --- a/gcc/config/i386/nto.h +++ b/gcc/config/i386/nto.h @@ -1,5 +1,5 @@ /* Definitions for Intel 386 running QNX/Neutrino. - Copyright (C) 2002-2015 Free Software Foundation, Inc. + Copyright (C) 2002-2016 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/i386/nto.opt b/gcc/config/i386/nto.opt index 25fa4ca770a..12486383316 100644 --- a/gcc/config/i386/nto.opt +++ b/gcc/config/i386/nto.opt @@ -1,6 +1,6 @@ ; QNX options. -; Copyright (C) 2011-2015 Free Software Foundation, Inc. +; Copyright (C) 2011-2016 Free Software Foundation, Inc. ; ; This file is part of GCC. ; diff --git a/gcc/config/i386/openbsd.h b/gcc/config/i386/openbsd.h index 260d3555553..325f1b93de7 100644 --- a/gcc/config/i386/openbsd.h +++ b/gcc/config/i386/openbsd.h @@ -1,5 +1,5 @@ /* Configuration for an OpenBSD i386 target. - Copyright (C) 1999-2015 Free Software Foundation, Inc. + Copyright (C) 1999-2016 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/i386/openbsdelf.h b/gcc/config/i386/openbsdelf.h index f9ce55902f6..eb8d9868489 100644 --- a/gcc/config/i386/openbsdelf.h +++ b/gcc/config/i386/openbsdelf.h @@ -1,6 +1,6 @@ /* Configuration for an OpenBSD i386 target. - Copyright (C) 2005-2015 Free Software Foundation, Inc. + Copyright (C) 2005-2016 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/i386/pcommitintrin.h b/gcc/config/i386/pcommitintrin.h index f9bc2f891f8..44e7a779909 100644 --- a/gcc/config/i386/pcommitintrin.h +++ b/gcc/config/i386/pcommitintrin.h @@ -1,4 +1,4 @@ -/* Copyright (C) 2013-2015 Free Software Foundation, Inc. +/* Copyright (C) 2013-2016 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/i386/pentium.md b/gcc/config/i386/pentium.md index 5064dd3a0a4..bb62b12a574 100644 --- a/gcc/config/i386/pentium.md +++ b/gcc/config/i386/pentium.md @@ -1,5 +1,5 @@ ;; Pentium Scheduling -;; Copyright (C) 2002-2015 Free Software Foundation, Inc. +;; Copyright (C) 2002-2016 Free Software Foundation, Inc. ;; ;; This file is part of GCC. ;; diff --git a/gcc/config/i386/pkuintrin.h b/gcc/config/i386/pkuintrin.h new file mode 100644 index 00000000000..09fdcd1d3f3 --- /dev/null +++ b/gcc/config/i386/pkuintrin.h @@ -0,0 +1,56 @@ +/* Copyright (C) 2015-2016 Free Software Foundation, Inc. + + This file is part of GCC. + + GCC is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3, or (at your option) + any later version. + + GCC is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + Under Section 7 of GPL version 3, you are granted additional + permissions described in the GCC Runtime Library Exception, version + 3.1, as published by the Free Software Foundation. + + You should have received a copy of the GNU General Public License and + a copy of the GCC Runtime Library Exception along with this program; + see the files COPYING3 and COPYING.RUNTIME respectively. If not, see + <http://www.gnu.org/licenses/>. */ + +#if !defined _X86INTRIN_H_INCLUDED +# error "Never use <pkuintrin.h> directly; include <x86intrin.h> instead." +#endif + +#ifndef _PKUINTRIN_H_INCLUDED +#define _PKUINTRIN_H_INCLUDED + +#ifndef __PKU__ +#pragma GCC push_options +#pragma GCC target("pku") +#define __DISABLE_PKU__ +#endif /* __PKU__ */ + +extern __inline unsigned int +__attribute__((__gnu_inline__, __always_inline__, __artificial__)) +_rdpkru_u32(void) +{ + return __builtin_ia32_rdpkru (); +} + +extern __inline void +__attribute__((__gnu_inline__, __always_inline__, __artificial__)) +_wrpkru(unsigned int key) +{ + return __builtin_ia32_wrpkru (key); +} + +#ifdef __DISABLE_PKU__ +#undef __DISABLE_PKU__ +#pragma GCC pop_options +#endif /* __DISABLE_PKU__ */ + +#endif /* _PKUINTRIN_H_INCLUDED */ diff --git a/gcc/config/i386/pmm_malloc.h b/gcc/config/i386/pmm_malloc.h index 901001b524a..a1f98d3d105 100644 --- a/gcc/config/i386/pmm_malloc.h +++ b/gcc/config/i386/pmm_malloc.h @@ -1,4 +1,4 @@ -/* Copyright (C) 2004-2015 Free Software Foundation, Inc. +/* Copyright (C) 2004-2016 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/i386/pmmintrin.h b/gcc/config/i386/pmmintrin.h index feb42deadfc..6fb8e5d3df2 100644 --- a/gcc/config/i386/pmmintrin.h +++ b/gcc/config/i386/pmmintrin.h @@ -1,4 +1,4 @@ -/* Copyright (C) 2003-2015 Free Software Foundation, Inc. +/* Copyright (C) 2003-2016 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/i386/popcntintrin.h b/gcc/config/i386/popcntintrin.h index d5ccf3164e1..9fd196f31a4 100644 --- a/gcc/config/i386/popcntintrin.h +++ b/gcc/config/i386/popcntintrin.h @@ -1,4 +1,4 @@ -/* Copyright (C) 2009-2015 Free Software Foundation, Inc. +/* Copyright (C) 2009-2016 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/i386/ppro.md b/gcc/config/i386/ppro.md index 979acc1e33e..f8a101b8721 100644 --- a/gcc/config/i386/ppro.md +++ b/gcc/config/i386/ppro.md @@ -1,5 +1,5 @@ ;; Scheduling for the Intel P6 family of processors -;; Copyright (C) 2004-2015 Free Software Foundation, Inc. +;; Copyright (C) 2004-2016 Free Software Foundation, Inc. ;; ;; This file is part of GCC. ;; diff --git a/gcc/config/i386/predicates.md b/gcc/config/i386/predicates.md index 8bdd5d88efb..14e80d9b48f 100644 --- a/gcc/config/i386/predicates.md +++ b/gcc/config/i386/predicates.md @@ -1,5 +1,5 @@ ;; Predicate definitions for IA-32 and x86-64. -;; Copyright (C) 2004-2015 Free Software Foundation, Inc. +;; Copyright (C) 2004-2016 Free Software Foundation, Inc. ;; ;; This file is part of GCC. ;; @@ -597,14 +597,38 @@ (match_operand 0 "memory_operand")))) ;; Return true if OP is a memory operands that can be used in sibcalls. +;; Since sibcall never returns, we can only use call-clobbered register +;; as GOT base. Allow GOT slot here only with pseudo register as GOT +;; base. Properly handle sibcall over GOT slot with *sibcall_GOT_32 +;; and *sibcall_value_GOT_32 patterns. (define_predicate "sibcall_memory_operand" - (and (match_operand 0 "memory_operand") - (match_test "CONSTANT_P (XEXP (op, 0)) - || (GET_CODE (XEXP (op, 0)) == PLUS - && REG_P (XEXP (XEXP (op, 0), 0)) - && GET_CODE (XEXP (XEXP (op, 0), 1)) == CONST - && GET_CODE (XEXP (XEXP (XEXP (op, 0), 1), 0)) == UNSPEC - && XINT (XEXP (XEXP (XEXP (op, 0), 1), 0), 1) == UNSPEC_GOT)"))) + (match_operand 0 "memory_operand") +{ + op = XEXP (op, 0); + if (CONSTANT_P (op)) + return true; + if (GET_CODE (op) == PLUS && REG_P (XEXP (op, 0))) + { + int regno = REGNO (XEXP (op, 0)); + if (!HARD_REGISTER_NUM_P (regno) || call_used_regs[regno]) + { + op = XEXP (op, 1); + if (GOT32_symbol_operand (op, VOIDmode)) + return true; + } + } + return false; +}) + +;; Return true if OP is a GOT memory operand. +(define_predicate "GOT_memory_operand" + (match_operand 0 "memory_operand") +{ + op = XEXP (op, 0); + return (GET_CODE (op) == CONST + && GET_CODE (XEXP (op, 0)) == UNSPEC + && XINT (XEXP (op, 0), 1) == UNSPEC_GOTPCREL); +}) ;; Test for a valid operand for a call instruction. ;; Allow constant call address operands in Pmode only. @@ -612,26 +636,26 @@ (ior (match_test "constant_call_address_operand (op, mode == VOIDmode ? mode : Pmode)") (match_operand 0 "call_register_no_elim_operand") - (and (not (match_test "TARGET_X32")) - (match_operand 0 "memory_operand")))) + (ior (and (not (match_test "TARGET_X32")) + (match_operand 0 "sibcall_memory_operand")) + (and (match_test "TARGET_X32 && Pmode == DImode") + (match_operand 0 "GOT_memory_operand"))))) ;; Similarly, but for tail calls, in which we cannot allow memory references. (define_special_predicate "sibcall_insn_operand" (ior (match_test "constant_call_address_operand (op, mode == VOIDmode ? mode : Pmode)") (match_operand 0 "register_no_elim_operand") - (and (not (match_test "TARGET_X32")) - (match_operand 0 "sibcall_memory_operand")))) + (ior (and (not (match_test "TARGET_X32")) + (match_operand 0 "sibcall_memory_operand")) + (and (match_test "TARGET_X32 && Pmode == DImode") + (match_operand 0 "GOT_memory_operand"))))) -;; Return true if OP is a GOT memory operand. -(define_predicate "GOT_memory_operand" - (match_operand 0 "memory_operand") -{ - op = XEXP (op, 0); - return (GET_CODE (op) == CONST - && GET_CODE (XEXP (op, 0)) == UNSPEC - && XINT (XEXP (op, 0), 1) == UNSPEC_GOTPCREL); -}) +;; Return true if OP is a 32-bit GOT symbol operand. +(define_predicate "GOT32_symbol_operand" + (match_test "GET_CODE (op) == CONST + && GET_CODE (XEXP (op, 0)) == UNSPEC + && XINT (XEXP (op, 0), 1) == UNSPEC_GOT")) ;; Match exactly zero. (define_predicate "const0_operand" @@ -927,6 +951,18 @@ (match_test "INTEGRAL_MODE_P (GET_MODE (op))") (match_test "op == CONSTM1_RTX (GET_MODE (op))"))) +; Return true when OP is operand acceptable for vector memory operand. +; Only AVX can have misaligned memory operand. +(define_predicate "vector_memory_operand" + (and (match_operand 0 "memory_operand") + (ior (match_test "TARGET_AVX") + (match_test "MEM_ALIGN (op) >= GET_MODE_ALIGNMENT (mode)")))) + +; Return true when OP is register_operand or vector_memory_operand. +(define_predicate "vector_operand" + (ior (match_operand 0 "register_operand") + (match_operand 0 "vector_memory_operand"))) + ; Return true when OP is operand acceptable for standard SSE move. (define_predicate "vector_move_operand" (ior (match_operand 0 "nonimmediate_operand") @@ -1567,9 +1603,9 @@ return val == ((low << 8) | low); }) -;; Return true if OP is nonimmediate_operand or CONST_VECTOR. +;; Return true if OP is vector_operand or CONST_VECTOR. (define_predicate "general_vector_operand" - (ior (match_operand 0 "nonimmediate_operand") + (ior (match_operand 0 "vector_operand") (match_code "const_vector"))) ;; Return true if OP is either -1 constant or stored in register. diff --git a/gcc/config/i386/prfchwintrin.h b/gcc/config/i386/prfchwintrin.h index 2f157162736..91d905d9fe3 100644 --- a/gcc/config/i386/prfchwintrin.h +++ b/gcc/config/i386/prfchwintrin.h @@ -1,4 +1,4 @@ -/* Copyright (C) 2012-2015 Free Software Foundation, Inc. +/* Copyright (C) 2012-2016 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/i386/rdos.h b/gcc/config/i386/rdos.h index ccf6b78824a..d98146d5d45 100644 --- a/gcc/config/i386/rdos.h +++ b/gcc/config/i386/rdos.h @@ -1,5 +1,5 @@ /* Definitions for RDOS on i386. - Copyright (C) 2013-2015 Free Software Foundation, Inc. + Copyright (C) 2013-2016 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/i386/rdos64.h b/gcc/config/i386/rdos64.h index efd3f60c0de..f5a8b86acfa 100644 --- a/gcc/config/i386/rdos64.h +++ b/gcc/config/i386/rdos64.h @@ -1,5 +1,5 @@ /* Definitions for RDOS on x86_64. - Copyright (C) 2013-2015 Free Software Foundation, Inc. + Copyright (C) 2013-2016 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/i386/rdseedintrin.h b/gcc/config/i386/rdseedintrin.h index b65fbc91cae..5af5eac4ad8 100644 --- a/gcc/config/i386/rdseedintrin.h +++ b/gcc/config/i386/rdseedintrin.h @@ -1,4 +1,4 @@ -/* Copyright (C) 2012-2015 Free Software Foundation, Inc. +/* Copyright (C) 2012-2016 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/i386/rtemself.h b/gcc/config/i386/rtemself.h index f5c4d854102..8b7dc5e5d17 100644 --- a/gcc/config/i386/rtemself.h +++ b/gcc/config/i386/rtemself.h @@ -1,5 +1,5 @@ /* Definitions for rtems targeting an ix86 using ELF. - Copyright (C) 1996-2015 Free Software Foundation, Inc. + Copyright (C) 1996-2016 Free Software Foundation, Inc. Contributed by Joel Sherrill (joel@OARcorp.com). This file is part of GCC. diff --git a/gcc/config/i386/rtmintrin.h b/gcc/config/i386/rtmintrin.h index 6396c9dbc48..14e29fc1556 100644 --- a/gcc/config/i386/rtmintrin.h +++ b/gcc/config/i386/rtmintrin.h @@ -1,4 +1,4 @@ -/* Copyright (C) 2012-2015 Free Software Foundation, Inc. +/* Copyright (C) 2012-2016 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/i386/shaintrin.h b/gcc/config/i386/shaintrin.h index a483b458dea..2059a662633 100644 --- a/gcc/config/i386/shaintrin.h +++ b/gcc/config/i386/shaintrin.h @@ -1,4 +1,4 @@ -/* Copyright (C) 2013-2015 Free Software Foundation, Inc. +/* Copyright (C) 2013-2016 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/i386/slm.md b/gcc/config/i386/slm.md index 9052323ebae..24ab3f8da1a 100644 --- a/gcc/config/i386/slm.md +++ b/gcc/config/i386/slm.md @@ -1,5 +1,5 @@ ;; Slivermont(SLM) Scheduling -;; Copyright (C) 2009-2015 Free Software Foundation, Inc. +;; Copyright (C) 2009-2016 Free Software Foundation, Inc. ;; ;; This file is part of GCC. ;; diff --git a/gcc/config/i386/smmintrin.h b/gcc/config/i386/smmintrin.h index b078780ce02..47e0a909689 100644 --- a/gcc/config/i386/smmintrin.h +++ b/gcc/config/i386/smmintrin.h @@ -1,4 +1,4 @@ -/* Copyright (C) 2007-2015 Free Software Foundation, Inc. +/* Copyright (C) 2007-2016 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/i386/sol2.h b/gcc/config/i386/sol2.h index ed963f89201..51d1c55de0d 100644 --- a/gcc/config/i386/sol2.h +++ b/gcc/config/i386/sol2.h @@ -1,5 +1,5 @@ /* Target definitions for GCC for Intel 80386 running Solaris 2 - Copyright (C) 1993-2015 Free Software Foundation, Inc. + Copyright (C) 1993-2016 Free Software Foundation, Inc. Contributed by Fred Fish (fnf@cygnus.com). This file is part of GCC. diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md index 6740edf7a9f..84d2b7af59b 100644 --- a/gcc/config/i386/sse.md +++ b/gcc/config/i386/sse.md @@ -1,5 +1,5 @@ ;; GCC machine description for SSE instructions -;; Copyright (C) 2005-2015 Free Software Foundation, Inc. +;; Copyright (C) 2005-2016 Free Software Foundation, Inc. ;; ;; This file is part of GCC. ;; @@ -960,30 +960,20 @@ (match_operand:<avx512fmaskmode> 3 "register_operand" "Yk,Yk")))] "TARGET_AVX512F" { - static char buf [64]; - - const char *insn_op; - const char *sse_suffix; - const char *align; if (FLOAT_MODE_P (GET_MODE_INNER (<MODE>mode))) { - insn_op = "vmov"; - sse_suffix = "<ssemodesuffix>"; + if (misaligned_operand (operands[1], <MODE>mode)) + return "vmovu<ssemodesuffix>\t{%1, %0%{%3%}%N2|%0%{%3%}%N2, %1}"; + else + return "vmova<ssemodesuffix>\t{%1, %0%{%3%}%N2|%0%{%3%}%N2, %1}"; } else { - insn_op = "vmovdq"; - sse_suffix = "<ssescalarsize>"; + if (misaligned_operand (operands[1], <MODE>mode)) + return "vmovdqu<ssescalarsize>\t{%1, %0%{%3%}%N2|%0%{%3%}%N2, %1}"; + else + return "vmovdqa<ssescalarsize>\t{%1, %0%{%3%}%N2|%0%{%3%}%N2, %1}"; } - - if (misaligned_operand (operands[1], <MODE>mode)) - align = "u"; - else - align = "a"; - - snprintf (buf, sizeof (buf), "%s%s%s\t{%%1, %%0%%{%%3%%}%%N2|%%0%%{%%3%%}%%N2, %%1}", - insn_op, align, sse_suffix); - return buf; } [(set_attr "type" "ssemov") (set_attr "prefix" "evex") @@ -1035,30 +1025,20 @@ (match_operand:<avx512fmaskmode> 2 "register_operand" "Yk")))] "TARGET_AVX512F" { - static char buf [64]; - - const char *insn_op; - const char *sse_suffix; - const char *align; if (FLOAT_MODE_P (GET_MODE_INNER (<MODE>mode))) { - insn_op = "vmov"; - sse_suffix = "<ssemodesuffix>"; + if (misaligned_operand (operands[0], <MODE>mode)) + return "vmovu<ssemodesuffix>\t{%1, %0%{%2%}|%0%{%2%}, %1}"; + else + return "vmova<ssemodesuffix>\t{%1, %0%{%2%}|%0%{%2%}, %1}"; } else { - insn_op = "vmovdq"; - sse_suffix = "<ssescalarsize>"; + if (misaligned_operand (operands[0], <MODE>mode)) + return "vmovdqu<ssescalarsize>\t{%1, %0%{%2%}|%0%{%2%}, %1}"; + else + return "vmovdqa<ssescalarsize>\t{%1, %0%{%2%}|%0%{%2%}, %1}"; } - - if (misaligned_operand (operands[0], <MODE>mode)) - align = "u"; - else - align = "a"; - - snprintf (buf, sizeof (buf), "%s%s%s\t{%%1, %%0%%{%%2%%}|%%0%%{%%2%%}, %%1}", - insn_op, align, sse_suffix); - return buf; } [(set_attr "type" "ssemov") (set_attr "prefix" "evex") @@ -1629,8 +1609,8 @@ (define_insn_and_split "*absneg<mode>2" [(set (match_operand:VF 0 "register_operand" "=x,x,v,v") (match_operator:VF 3 "absneg_operator" - [(match_operand:VF 1 "nonimmediate_operand" "0, xm, v, m")])) - (use (match_operand:VF 2 "nonimmediate_operand" "xm, 0, vm,v"))] + [(match_operand:VF 1 "vector_operand" "0, xBm,v, m")])) + (use (match_operand:VF 2 "vector_operand" "xBm,0, vm,v"))] "TARGET_SSE" "#" "&& reload_completed" @@ -1676,7 +1656,7 @@ [(set (match_operand:VF 0 "register_operand" "=x,v") (plusminus:VF (match_operand:VF 1 "<round_nimm_predicate>" "<comm>0,v") - (match_operand:VF 2 "<round_nimm_predicate>" "xm,<round_constraint>")))] + (match_operand:VF 2 "<round_nimm_predicate>" "xBm,<round_constraint>")))] "TARGET_SSE && ix86_binary_operator_ok (<CODE>, <MODE>mode, operands) && <mask_mode512bit_condition> && <round_mode512bit_condition>" "@ <plusminus_mnemonic><ssemodesuffix>\t{%2, %0|%0, %2} @@ -1691,7 +1671,7 @@ (vec_merge:VF_128 (plusminus:VF_128 (match_operand:VF_128 1 "register_operand" "0,v") - (match_operand:VF_128 2 "nonimmediate_operand" "xm,<round_constraint>")) + (match_operand:VF_128 2 "vector_operand" "xBm,<round_constraint>")) (match_dup 1) (const_int 1)))] "TARGET_SSE" @@ -1715,7 +1695,7 @@ [(set (match_operand:VF 0 "register_operand" "=x,v") (mult:VF (match_operand:VF 1 "<round_nimm_predicate>" "%0,v") - (match_operand:VF 2 "<round_nimm_predicate>" "xm,<round_constraint>")))] + (match_operand:VF 2 "<round_nimm_predicate>" "xBm,<round_constraint>")))] "TARGET_SSE && ix86_binary_operator_ok (MULT, <MODE>mode, operands) && <mask_mode512bit_condition> && <round_mode512bit_condition>" "@ mul<ssemodesuffix>\t{%2, %0|%0, %2} @@ -1731,7 +1711,7 @@ (vec_merge:VF_128 (multdiv:VF_128 (match_operand:VF_128 1 "register_operand" "0,v") - (match_operand:VF_128 2 "nonimmediate_operand" "xm,<round_constraint>")) + (match_operand:VF_128 2 "vector_operand" "xBm,<round_constraint>")) (match_dup 1) (const_int 1)))] "TARGET_SSE" @@ -1747,14 +1727,14 @@ (define_expand "div<mode>3" [(set (match_operand:VF2 0 "register_operand") (div:VF2 (match_operand:VF2 1 "register_operand") - (match_operand:VF2 2 "nonimmediate_operand")))] + (match_operand:VF2 2 "vector_operand")))] "TARGET_SSE2" "ix86_fixup_binary_operands_no_copy (DIV, <MODE>mode, operands);") (define_expand "div<mode>3" [(set (match_operand:VF1 0 "register_operand") (div:VF1 (match_operand:VF1 1 "register_operand") - (match_operand:VF1 2 "nonimmediate_operand")))] + (match_operand:VF1 2 "vector_operand")))] "TARGET_SSE" { ix86_fixup_binary_operands_no_copy (DIV, <MODE>mode, operands); @@ -1774,7 +1754,7 @@ [(set (match_operand:VF 0 "register_operand" "=x,v") (div:VF (match_operand:VF 1 "register_operand" "0,v") - (match_operand:VF 2 "<round_nimm_predicate>" "xm,<round_constraint>")))] + (match_operand:VF 2 "<round_nimm_predicate>" "xBm,<round_constraint>")))] "TARGET_SSE && <mask_mode512bit_condition> && <round_mode512bit_condition>" "@ div<ssemodesuffix>\t{%2, %0|%0, %2} @@ -1787,7 +1767,7 @@ (define_insn "<sse>_rcp<mode>2" [(set (match_operand:VF1_128_256 0 "register_operand" "=x") (unspec:VF1_128_256 - [(match_operand:VF1_128_256 1 "nonimmediate_operand" "xm")] UNSPEC_RCP))] + [(match_operand:VF1_128_256 1 "vector_operand" "xBm")] UNSPEC_RCP))] "TARGET_SSE" "%vrcpps\t{%1, %0|%0, %1}" [(set_attr "type" "sse") @@ -1842,12 +1822,12 @@ (define_expand "sqrt<mode>2" [(set (match_operand:VF2 0 "register_operand") - (sqrt:VF2 (match_operand:VF2 1 "nonimmediate_operand")))] + (sqrt:VF2 (match_operand:VF2 1 "vector_operand")))] "TARGET_SSE2") (define_expand "sqrt<mode>2" [(set (match_operand:VF1 0 "register_operand") - (sqrt:VF1 (match_operand:VF1 1 "nonimmediate_operand")))] + (sqrt:VF1 (match_operand:VF1 1 "vector_operand")))] "TARGET_SSE" { if (TARGET_SSE_MATH @@ -1862,11 +1842,14 @@ }) (define_insn "<sse>_sqrt<mode>2<mask_name><round_name>" - [(set (match_operand:VF 0 "register_operand" "=v") - (sqrt:VF (match_operand:VF 1 "<round_nimm_predicate>" "<round_constraint>")))] + [(set (match_operand:VF 0 "register_operand" "=x,v") + (sqrt:VF (match_operand:VF 1 "<round_nimm_predicate>" "xBm,<round_constraint>")))] "TARGET_SSE && <mask_mode512bit_condition> && <round_mode512bit_condition>" - "%vsqrt<ssemodesuffix>\t{<round_mask_op2>%1, %0<mask_operand2>|%0<mask_operand2>, %1<round_mask_op2>}" - [(set_attr "type" "sse") + "@ + sqrt<ssemodesuffix>\t{%1, %0|%0, %1} + vsqrt<ssemodesuffix>\t{<round_mask_op2>%1, %0<mask_operand2>|%0<mask_operand2>, %1<round_mask_op2>}" + [(set_attr "isa" "noavx,avx") + (set_attr "type" "sse") (set_attr "atom_sse_attr" "sqrt") (set_attr "btver2_sse_attr" "sqrt") (set_attr "prefix" "maybe_vex") @@ -1876,7 +1859,7 @@ [(set (match_operand:VF_128 0 "register_operand" "=x,v") (vec_merge:VF_128 (sqrt:VF_128 - (match_operand:VF_128 1 "nonimmediate_operand" "xm,<round_constraint>")) + (match_operand:VF_128 1 "vector_operand" "xBm,<round_constraint>")) (match_operand:VF_128 2 "register_operand" "0,v") (const_int 1)))] "TARGET_SSE" @@ -1893,7 +1876,7 @@ (define_expand "rsqrt<mode>2" [(set (match_operand:VF1_128_256 0 "register_operand") (unspec:VF1_128_256 - [(match_operand:VF1_128_256 1 "nonimmediate_operand")] UNSPEC_RSQRT))] + [(match_operand:VF1_128_256 1 "vector_operand")] UNSPEC_RSQRT))] "TARGET_SSE_MATH" { ix86_emit_swsqrtsf (operands[0], operands[1], <MODE>mode, true); @@ -1903,7 +1886,7 @@ (define_insn "<sse>_rsqrt<mode>2" [(set (match_operand:VF1_128_256 0 "register_operand" "=x") (unspec:VF1_128_256 - [(match_operand:VF1_128_256 1 "nonimmediate_operand" "xm")] UNSPEC_RSQRT))] + [(match_operand:VF1_128_256 1 "vector_operand" "xBm")] UNSPEC_RSQRT))] "TARGET_SSE" "%vrsqrtps\t{%1, %0|%0, %1}" [(set_attr "type" "sse") @@ -1972,7 +1955,7 @@ [(set (match_operand:VF 0 "register_operand" "=x,v") (smaxmin:VF (match_operand:VF 1 "<round_saeonly_nimm_predicate>" "%0,v") - (match_operand:VF 2 "<round_saeonly_nimm_predicate>" "xm,<round_saeonly_constraint>")))] + (match_operand:VF 2 "<round_saeonly_nimm_predicate>" "xBm,<round_saeonly_constraint>")))] "TARGET_SSE && flag_finite_math_only && ix86_binary_operator_ok (<CODE>, <MODE>mode, operands) && <mask_mode512bit_condition> && <round_saeonly_mode512bit_condition>" @@ -1989,7 +1972,7 @@ [(set (match_operand:VF 0 "register_operand" "=x,v") (smaxmin:VF (match_operand:VF 1 "register_operand" "0,v") - (match_operand:VF 2 "<round_saeonly_nimm_predicate>" "xm,<round_saeonly_constraint>")))] + (match_operand:VF 2 "<round_saeonly_nimm_predicate>" "xBm,<round_saeonly_constraint>")))] "TARGET_SSE && !flag_finite_math_only && <mask_mode512bit_condition> && <round_saeonly_mode512bit_condition>" "@ @@ -2006,7 +1989,7 @@ (vec_merge:VF_128 (smaxmin:VF_128 (match_operand:VF_128 1 "register_operand" "0,v") - (match_operand:VF_128 2 "nonimmediate_operand" "xm,<round_saeonly_constraint>")) + (match_operand:VF_128 2 "vector_operand" "xBm,<round_saeonly_constraint>")) (match_dup 1) (const_int 1)))] "TARGET_SSE" @@ -2026,10 +2009,10 @@ ;; presence of -0.0 and NaN. (define_insn "*ieee_smin<mode>3" - [(set (match_operand:VF 0 "register_operand" "=v,v") + [(set (match_operand:VF 0 "register_operand" "=x,v") (unspec:VF [(match_operand:VF 1 "register_operand" "0,v") - (match_operand:VF 2 "nonimmediate_operand" "vm,vm")] + (match_operand:VF 2 "vector_operand" "xBm,vm")] UNSPEC_IEEE_MIN))] "TARGET_SSE" "@ @@ -2041,10 +2024,10 @@ (set_attr "mode" "<MODE>")]) (define_insn "*ieee_smax<mode>3" - [(set (match_operand:VF 0 "register_operand" "=v,v") + [(set (match_operand:VF 0 "register_operand" "=x,v") (unspec:VF [(match_operand:VF 1 "register_operand" "0,v") - (match_operand:VF 2 "nonimmediate_operand" "vm,vm")] + (match_operand:VF 2 "vector_operand" "xBm,vm")] UNSPEC_IEEE_MAX))] "TARGET_SSE" "@ @@ -2074,7 +2057,7 @@ (vec_merge:V2DF (minus:V2DF (match_operand:V2DF 1 "register_operand" "0,x") - (match_operand:V2DF 2 "nonimmediate_operand" "xm,xm")) + (match_operand:V2DF 2 "vector_operand" "xBm,xm")) (plus:V2DF (match_dup 1) (match_dup 2)) (const_int 1)))] "TARGET_SSE3" @@ -2106,7 +2089,7 @@ (vec_merge:V4SF (minus:V4SF (match_operand:V4SF 1 "register_operand" "0,x") - (match_operand:V4SF 2 "nonimmediate_operand" "xm,xm")) + (match_operand:V4SF 2 "vector_operand" "xBm,xm")) (plus:V4SF (match_dup 1) (match_dup 2)) (const_int 5)))] "TARGET_SSE3" @@ -2124,10 +2107,10 @@ (match_operator:VF_128_256 6 "addsub_vm_operator" [(minus:VF_128_256 (match_operand:VF_128_256 1 "register_operand") - (match_operand:VF_128_256 2 "nonimmediate_operand")) + (match_operand:VF_128_256 2 "vector_operand")) (plus:VF_128_256 - (match_operand:VF_128_256 3 "nonimmediate_operand") - (match_operand:VF_128_256 4 "nonimmediate_operand")) + (match_operand:VF_128_256 3 "vector_operand") + (match_operand:VF_128_256 4 "vector_operand")) (match_operand 5 "const_int_operand")]))] "TARGET_SSE3 && can_create_pseudo_p () @@ -2145,11 +2128,11 @@ [(set (match_operand:VF_128_256 0 "register_operand") (match_operator:VF_128_256 6 "addsub_vm_operator" [(plus:VF_128_256 - (match_operand:VF_128_256 1 "nonimmediate_operand") - (match_operand:VF_128_256 2 "nonimmediate_operand")) + (match_operand:VF_128_256 1 "vector_operand") + (match_operand:VF_128_256 2 "vector_operand")) (minus:VF_128_256 (match_operand:VF_128_256 3 "register_operand") - (match_operand:VF_128_256 4 "nonimmediate_operand")) + (match_operand:VF_128_256 4 "vector_operand")) (match_operand 5 "const_int_operand")]))] "TARGET_SSE3 && can_create_pseudo_p () @@ -2175,10 +2158,10 @@ [(vec_concat:<ssedoublemode> (minus:VF_128_256 (match_operand:VF_128_256 1 "register_operand") - (match_operand:VF_128_256 2 "nonimmediate_operand")) + (match_operand:VF_128_256 2 "vector_operand")) (plus:VF_128_256 - (match_operand:VF_128_256 3 "nonimmediate_operand") - (match_operand:VF_128_256 4 "nonimmediate_operand"))) + (match_operand:VF_128_256 3 "vector_operand") + (match_operand:VF_128_256 4 "vector_operand"))) (match_parallel 5 "addsub_vs_parallel" [(match_operand 6 "const_int_operand")])]))] "TARGET_SSE3 @@ -2208,11 +2191,11 @@ (match_operator:VF_128_256 7 "addsub_vs_operator" [(vec_concat:<ssedoublemode> (plus:VF_128_256 - (match_operand:VF_128_256 1 "nonimmediate_operand") - (match_operand:VF_128_256 2 "nonimmediate_operand")) + (match_operand:VF_128_256 1 "vector_operand") + (match_operand:VF_128_256 2 "vector_operand")) (minus:VF_128_256 (match_operand:VF_128_256 3 "register_operand") - (match_operand:VF_128_256 4 "nonimmediate_operand"))) + (match_operand:VF_128_256 4 "vector_operand"))) (match_parallel 5 "addsub_vs_parallel" [(match_operand 6 "const_int_operand")])]))] "TARGET_SSE3 @@ -2274,7 +2257,7 @@ (vec_select:DF (match_dup 1) (parallel [(const_int 1)]))) (plus:DF (vec_select:DF - (match_operand:V2DF 2 "nonimmediate_operand") + (match_operand:V2DF 2 "vector_operand") (parallel [(const_int 0)])) (vec_select:DF (match_dup 2) (parallel [(const_int 1)])))))] "TARGET_SSE3") @@ -2291,7 +2274,7 @@ (parallel [(match_operand:SI 4 "const_0_to_1_operand")]))) (plus:DF (vec_select:DF - (match_operand:V2DF 2 "nonimmediate_operand" "xm,xm") + (match_operand:V2DF 2 "vector_operand" "xBm,xm") (parallel [(match_operand:SI 5 "const_0_to_1_operand")])) (vec_select:DF (match_dup 2) @@ -2317,7 +2300,7 @@ (vec_select:DF (match_dup 1) (parallel [(const_int 1)]))) (minus:DF (vec_select:DF - (match_operand:V2DF 2 "nonimmediate_operand" "xm,xm") + (match_operand:V2DF 2 "vector_operand" "xBm,xm") (parallel [(const_int 0)])) (vec_select:DF (match_dup 2) (parallel [(const_int 1)])))))] "TARGET_SSE3" @@ -2424,7 +2407,7 @@ (vec_concat:V2SF (plusminus:SF (vec_select:SF - (match_operand:V4SF 2 "nonimmediate_operand" "xm,xm") + (match_operand:V4SF 2 "vector_operand" "xBm,xm") (parallel [(const_int 0)])) (vec_select:SF (match_dup 2) (parallel [(const_int 1)]))) (plusminus:SF @@ -2650,7 +2633,7 @@ [(set (match_operand:VF_128_256 0 "register_operand" "=x,x") (match_operator:VF_128_256 3 "sse_comparison_operator" [(match_operand:VF_128_256 1 "register_operand" "%0,x") - (match_operand:VF_128_256 2 "nonimmediate_operand" "xm,xm")]))] + (match_operand:VF_128_256 2 "vector_operand" "xBm,xm")]))] "TARGET_SSE && GET_RTX_CLASS (GET_CODE (operands[3])) == RTX_COMM_COMPARE" "@ @@ -2666,7 +2649,7 @@ [(set (match_operand:VF_128_256 0 "register_operand" "=x,x") (match_operator:VF_128_256 3 "sse_comparison_operator" [(match_operand:VF_128_256 1 "register_operand" "0,x") - (match_operand:VF_128_256 2 "nonimmediate_operand" "xm,xm")]))] + (match_operand:VF_128_256 2 "vector_operand" "xBm,xm")]))] "TARGET_SSE" "@ cmp%D3<ssemodesuffix>\t{%2, %0|%0, %2} @@ -2682,7 +2665,7 @@ (vec_merge:VF_128 (match_operator:VF_128 3 "sse_comparison_operator" [(match_operand:VF_128 1 "register_operand" "0,x") - (match_operand:VF_128 2 "nonimmediate_operand" "xm,xm")]) + (match_operand:VF_128 2 "vector_operand" "xBm,xm")]) (match_dup 1) (const_int 1)))] "TARGET_SSE" @@ -2815,7 +2798,7 @@ (match_operand:<ssevecmode> 0 "register_operand" "v") (parallel [(const_int 0)])) (vec_select:MODEF - (match_operand:<ssevecmode> 1 "<round_saeonly_nimm_predicate>" "<round_saeonly_constraint>") + (match_operand:<ssevecmode> 1 "<round_saeonly_nimm_scalar_predicate>" "<round_saeonly_constraint>") (parallel [(const_int 0)]))))] "SSE_FLOAT_MODE_P (<MODE>mode)" "%vcomi<ssemodesuffix>\t{<round_saeonly_op2>%1, %0|%0, %<iptr>1<round_saeonly_op2>}" @@ -2835,7 +2818,7 @@ (match_operand:<ssevecmode> 0 "register_operand" "v") (parallel [(const_int 0)])) (vec_select:MODEF - (match_operand:<ssevecmode> 1 "<round_saeonly_nimm_predicate>" "<round_saeonly_constraint>") + (match_operand:<ssevecmode> 1 "<round_saeonly_nimm_scalar_predicate>" "<round_saeonly_constraint>") (parallel [(const_int 0)]))))] "SSE_FLOAT_MODE_P (<MODE>mode)" "%vucomi<ssemodesuffix>\t{<round_saeonly_op2>%1, %0|%0, %<iptr>1<round_saeonly_op2>}" @@ -2888,7 +2871,7 @@ [(set (match_operand:<sseintvecmode> 0 "register_operand") (match_operator:<sseintvecmode> 1 "" [(match_operand:VI124_128 2 "register_operand") - (match_operand:VI124_128 3 "nonimmediate_operand")]))] + (match_operand:VI124_128 3 "vector_operand")]))] "TARGET_SSE2" { bool ok = ix86_expand_int_vec_cmp (operands); @@ -2900,7 +2883,7 @@ [(set (match_operand:V2DI 0 "register_operand") (match_operator:V2DI 1 "" [(match_operand:V2DI 2 "register_operand") - (match_operand:V2DI 3 "nonimmediate_operand")]))] + (match_operand:V2DI 3 "vector_operand")]))] "TARGET_SSE4_2" { bool ok = ix86_expand_int_vec_cmp (operands); @@ -2924,7 +2907,7 @@ [(set (match_operand:<sseintvecmode> 0 "register_operand") (match_operator:<sseintvecmode> 1 "" [(match_operand:VF_128 2 "register_operand") - (match_operand:VF_128 3 "nonimmediate_operand")]))] + (match_operand:VF_128 3 "vector_operand")]))] "TARGET_SSE" { bool ok = ix86_expand_fp_vec_cmp (operands); @@ -2972,7 +2955,7 @@ [(set (match_operand:<sseintvecmode> 0 "register_operand") (match_operator:<sseintvecmode> 1 "" [(match_operand:VI124_128 2 "register_operand") - (match_operand:VI124_128 3 "nonimmediate_operand")]))] + (match_operand:VI124_128 3 "vector_operand")]))] "TARGET_SSE2" { bool ok = ix86_expand_int_vec_cmp (operands); @@ -2984,7 +2967,7 @@ [(set (match_operand:V2DI 0 "register_operand") (match_operator:V2DI 1 "" [(match_operand:V2DI 2 "register_operand") - (match_operand:V2DI 3 "nonimmediate_operand")]))] + (match_operand:V2DI 3 "vector_operand")]))] "TARGET_SSE4_2" { bool ok = ix86_expand_int_vec_cmp (operands); @@ -3030,8 +3013,8 @@ [(set (match_operand:V_128 0 "register_operand") (if_then_else:V_128 (match_operator 3 "" - [(match_operand:VF_128 4 "nonimmediate_operand") - (match_operand:VF_128 5 "nonimmediate_operand")]) + [(match_operand:VF_128 4 "vector_operand") + (match_operand:VF_128 5 "vector_operand")]) (match_operand:V_128 1 "general_operand") (match_operand:V_128 2 "general_operand")))] "TARGET_SSE @@ -3075,7 +3058,7 @@ (define_expand "vcond_mask_<mode><sseintvecmodelower>" [(set (match_operand:VI124_128 0 "register_operand") (vec_merge:VI124_128 - (match_operand:VI124_128 1 "nonimmediate_operand") + (match_operand:VI124_128 1 "vector_operand") (match_operand:VI124_128 2 "vector_move_operand") (match_operand:<sseintvecmode> 3 "register_operand")))] "TARGET_SSE2" @@ -3088,7 +3071,7 @@ (define_expand "vcond_mask_v2div2di" [(set (match_operand:V2DI 0 "register_operand") (vec_merge:V2DI - (match_operand:V2DI 1 "nonimmediate_operand") + (match_operand:V2DI 1 "vector_operand") (match_operand:V2DI 2 "vector_move_operand") (match_operand:V2DI 3 "register_operand")))] "TARGET_SSE4_2" @@ -3114,7 +3097,7 @@ (define_expand "vcond_mask_<mode><sseintvecmodelower>" [(set (match_operand:VF_128 0 "register_operand") (vec_merge:VF_128 - (match_operand:VF_128 1 "nonimmediate_operand") + (match_operand:VF_128 1 "vector_operand") (match_operand:VF_128 2 "vector_move_operand") (match_operand:<sseintvecmode> 3 "register_operand")))] "TARGET_SSE" @@ -3135,7 +3118,7 @@ (and:VF_128_256 (not:VF_128_256 (match_operand:VF_128_256 1 "register_operand" "0,v")) - (match_operand:VF_128_256 2 "nonimmediate_operand" "xm,vm")))] + (match_operand:VF_128_256 2 "vector_operand" "xBm,vm")))] "TARGET_SSE && <mask_avx512vl_condition>" { static char buf[128]; @@ -3223,8 +3206,8 @@ (define_expand "<code><mode>3<mask_name>" [(set (match_operand:VF_128_256 0 "register_operand") (any_logic:VF_128_256 - (match_operand:VF_128_256 1 "nonimmediate_operand") - (match_operand:VF_128_256 2 "nonimmediate_operand")))] + (match_operand:VF_128_256 1 "vector_operand") + (match_operand:VF_128_256 2 "vector_operand")))] "TARGET_SSE && <mask_avx512vl_condition>" "ix86_fixup_binary_operands_no_copy (<CODE>, <MODE>mode, operands);") @@ -3239,8 +3222,8 @@ (define_insn "*<code><mode>3<mask_name>" [(set (match_operand:VF_128_256 0 "register_operand" "=x,v") (any_logic:VF_128_256 - (match_operand:VF_128_256 1 "nonimmediate_operand" "%0,v") - (match_operand:VF_128_256 2 "nonimmediate_operand" "xm,vm")))] + (match_operand:VF_128_256 1 "vector_operand" "%0,v") + (match_operand:VF_128_256 2 "vector_operand" "xBm,vm")))] "TARGET_SSE && <mask_avx512vl_condition> && ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)" { @@ -3328,10 +3311,10 @@ [(set (match_dup 4) (and:VF (not:VF (match_dup 3)) - (match_operand:VF 1 "nonimmediate_operand"))) + (match_operand:VF 1 "vector_operand"))) (set (match_dup 5) (and:VF (match_dup 3) - (match_operand:VF 2 "nonimmediate_operand"))) + (match_operand:VF 2 "vector_operand"))) (set (match_operand:VF 0 "register_operand") (ior:VF (match_dup 4) (match_dup 5)))] "TARGET_SSE" @@ -3393,7 +3376,7 @@ [(set (match_operand:TF 0 "register_operand" "=x,x") (and:TF (not:TF (match_operand:TF 1 "register_operand" "0,x")) - (match_operand:TF 2 "nonimmediate_operand" "xm,xm")))] + (match_operand:TF 2 "vector_operand" "xBm,xm")))] "TARGET_SSE" { static char buf[32]; @@ -3480,16 +3463,16 @@ (define_expand "<code>tf3" [(set (match_operand:TF 0 "register_operand") (any_logic:TF - (match_operand:TF 1 "nonimmediate_operand") - (match_operand:TF 2 "nonimmediate_operand")))] + (match_operand:TF 1 "vector_operand") + (match_operand:TF 2 "vector_operand")))] "TARGET_SSE" "ix86_fixup_binary_operands_no_copy (<CODE>, TFmode, operands);") (define_insn "*<code>tf3" [(set (match_operand:TF 0 "register_operand" "=x,x") (any_logic:TF - (match_operand:TF 1 "nonimmediate_operand" "%0,x") - (match_operand:TF 2 "nonimmediate_operand" "xm,xm")))] + (match_operand:TF 1 "vector_operand" "%0,x") + (match_operand:TF 2 "vector_operand" "xBm,xm")))] "TARGET_SSE && ix86_binary_operator_ok (<CODE>, TFmode, operands)" { @@ -4269,7 +4252,7 @@ [(set (match_operand:V4SF 0 "register_operand" "=x,x,v") (vec_merge:V4SF (vec_duplicate:V4SF - (float:SF (match_operand:SI 2 "<round_nimm_predicate>" "r,m,<round_constraint3>"))) + (float:SF (match_operand:SI 2 "<round_nimm_scalar_predicate>" "r,m,<round_constraint3>"))) (match_operand:V4SF 1 "register_operand" "0,0,v") (const_int 1)))] "TARGET_SSE" @@ -4291,7 +4274,7 @@ [(set (match_operand:V4SF 0 "register_operand" "=x,x,v") (vec_merge:V4SF (vec_duplicate:V4SF - (float:SF (match_operand:DI 2 "<round_nimm_predicate>" "r,m,<round_constraint3>"))) + (float:SF (match_operand:DI 2 "<round_nimm_scalar_predicate>" "r,m,<round_constraint3>"))) (match_operand:V4SF 1 "register_operand" "0,0,v") (const_int 1)))] "TARGET_SSE && TARGET_64BIT" @@ -4314,7 +4297,7 @@ [(set (match_operand:SI 0 "register_operand" "=r,r") (unspec:SI [(vec_select:SF - (match_operand:V4SF 1 "<round_nimm_predicate>" "v,<round_constraint2>") + (match_operand:V4SF 1 "<round_nimm_scalar_predicate>" "v,<round_constraint2>") (parallel [(const_int 0)]))] UNSPEC_FIX_NOTRUNC))] "TARGET_SSE" @@ -4344,7 +4327,7 @@ [(set (match_operand:DI 0 "register_operand" "=r,r") (unspec:DI [(vec_select:SF - (match_operand:V4SF 1 "<round_nimm_predicate>" "v,<round_constraint2>") + (match_operand:V4SF 1 "<round_nimm_scalar_predicate>" "v,<round_constraint2>") (parallel [(const_int 0)]))] UNSPEC_FIX_NOTRUNC))] "TARGET_SSE && TARGET_64BIT" @@ -4374,7 +4357,7 @@ [(set (match_operand:SI 0 "register_operand" "=r,r") (fix:SI (vec_select:SF - (match_operand:V4SF 1 "<round_saeonly_nimm_predicate>" "v,<round_saeonly_constraint2>") + (match_operand:V4SF 1 "<round_saeonly_nimm_scalar_predicate>" "v,<round_saeonly_constraint2>") (parallel [(const_int 0)]))))] "TARGET_SSE" "%vcvttss2si\t{<round_saeonly_op2>%1, %0|%0, %k1<round_saeonly_op2>}" @@ -4390,7 +4373,7 @@ [(set (match_operand:DI 0 "register_operand" "=r,r") (fix:DI (vec_select:SF - (match_operand:V4SF 1 "<round_saeonly_nimm_predicate>" "v,<round_saeonly_constraint>") + (match_operand:V4SF 1 "<round_saeonly_nimm_scalar_predicate>" "v,<round_saeonly_constraint>") (parallel [(const_int 0)]))))] "TARGET_SSE && TARGET_64BIT" "%vcvttss2si{q}\t{<round_saeonly_op2>%1, %0|%0, %k1<round_saeonly_op2>}" @@ -4431,12 +4414,15 @@ (set_attr "mode" "<ssescalarmode>")]) (define_insn "float<sseintvecmodelower><mode>2<mask_name><round_name>" - [(set (match_operand:VF1 0 "register_operand" "=v") + [(set (match_operand:VF1 0 "register_operand" "=x,v") (float:VF1 - (match_operand:<sseintvecmode> 1 "<round_nimm_predicate>" "<round_constraint>")))] + (match_operand:<sseintvecmode> 1 "<round_nimm_predicate>" "xBm,<round_constraint>")))] "TARGET_SSE2 && <mask_mode512bit_condition> && <round_mode512bit_condition>" - "%vcvtdq2ps\t{<round_mask_op2>%1, %0<mask_operand2>|%0<mask_operand2>, %1<round_mask_op2>}" - [(set_attr "type" "ssecvt") + "@ + cvtdq2ps\t{%1, %0|%0, %1} + vcvtdq2ps\t{<round_mask_op2>%1, %0<mask_operand2>|%0<mask_operand2>, %1<round_mask_op2>}" + [(set_attr "isa" "noavx,avx") + (set_attr "type" "ssecvt") (set_attr "prefix" "maybe_vex") (set_attr "mode" "<sseinsnmode>")]) @@ -4479,7 +4465,7 @@ (define_insn "<sse2_avx_avx512f>_fix_notrunc<sf2simodelower><mode><mask_name>" [(set (match_operand:VI4_AVX 0 "register_operand" "=v") (unspec:VI4_AVX - [(match_operand:<ssePSmode> 1 "nonimmediate_operand" "vm")] + [(match_operand:<ssePSmode> 1 "vector_operand" "vBm")] UNSPEC_FIX_NOTRUNC))] "TARGET_SSE2 && <mask_mode512bit_condition>" "%vcvtps2dq\t{%1, %0<mask_operand2>|%0<mask_operand2>, %1}" @@ -4581,7 +4567,7 @@ (define_insn "fix_truncv4sfv4si2<mask_name>" [(set (match_operand:V4SI 0 "register_operand" "=v") - (fix:V4SI (match_operand:V4SF 1 "nonimmediate_operand" "vm")))] + (fix:V4SI (match_operand:V4SF 1 "vector_operand" "vBm")))] "TARGET_SSE2 && <mask_avx512vl_condition>" "%vcvttps2dq\t{%1, %0<mask_operand2>|%0<mask_operand2>, %1}" [(set_attr "type" "ssecvt") @@ -4684,7 +4670,7 @@ [(set (match_operand:V2DF 0 "register_operand" "=x,x,v") (vec_merge:V2DF (vec_duplicate:V2DF - (float:DF (match_operand:DI 2 "<round_nimm_predicate>" "r,m,<round_constraint3>"))) + (float:DF (match_operand:DI 2 "<round_nimm_scalar_predicate>" "r,m,<round_constraint3>"))) (match_operand:V2DF 1 "register_operand" "0,0,v") (const_int 1)))] "TARGET_SSE2 && TARGET_64BIT" @@ -4732,7 +4718,7 @@ [(set (match_operand:SI 0 "register_operand" "=r") (unsigned_fix:SI (vec_select:SF - (match_operand:V4SF 1 "<round_saeonly_nimm_predicate>" "<round_saeonly_constraint>") + (match_operand:V4SF 1 "<round_saeonly_nimm_scalar_predicate>" "<round_saeonly_constraint>") (parallel [(const_int 0)]))))] "TARGET_AVX512F" "vcvttss2usi\t{<round_saeonly_op2>%1, %0|%0, %1<round_saeonly_op2>}" @@ -4744,7 +4730,7 @@ [(set (match_operand:DI 0 "register_operand" "=r") (unsigned_fix:DI (vec_select:SF - (match_operand:V4SF 1 "<round_saeonly_nimm_predicate>" "<round_saeonly_constraint>") + (match_operand:V4SF 1 "<round_saeonly_nimm_scalar_predicate>" "<round_saeonly_constraint>") (parallel [(const_int 0)]))))] "TARGET_AVX512F && TARGET_64BIT" "vcvttss2usi\t{<round_saeonly_op2>%1, %0|%0, %1<round_saeonly_op2>}" @@ -4782,7 +4768,7 @@ [(set (match_operand:SI 0 "register_operand" "=r") (unsigned_fix:SI (vec_select:DF - (match_operand:V2DF 1 "<round_saeonly_nimm_predicate>" "<round_saeonly_constraint>") + (match_operand:V2DF 1 "<round_saeonly_nimm_scalar_predicate>" "<round_saeonly_constraint>") (parallel [(const_int 0)]))))] "TARGET_AVX512F" "vcvttsd2usi\t{<round_saeonly_op2>%1, %0|%0, %1<round_saeonly_op2>}" @@ -4794,7 +4780,7 @@ [(set (match_operand:DI 0 "register_operand" "=r") (unsigned_fix:DI (vec_select:DF - (match_operand:V2DF 1 "<round_saeonly_nimm_predicate>" "<round_saeonly_constraint>") + (match_operand:V2DF 1 "<round_saeonly_nimm_scalar_predicate>" "<round_saeonly_constraint>") (parallel [(const_int 0)]))))] "TARGET_AVX512F && TARGET_64BIT" "vcvttsd2usi\t{<round_saeonly_op2>%1, %0|%0, %1<round_saeonly_op2>}" @@ -4806,7 +4792,7 @@ [(set (match_operand:SI 0 "register_operand" "=r,r") (unspec:SI [(vec_select:DF - (match_operand:V2DF 1 "<round_nimm_predicate>" "v,<round_constraint2>") + (match_operand:V2DF 1 "<round_nimm_scalar_predicate>" "v,<round_constraint2>") (parallel [(const_int 0)]))] UNSPEC_FIX_NOTRUNC))] "TARGET_SSE2" @@ -4837,7 +4823,7 @@ [(set (match_operand:DI 0 "register_operand" "=r,r") (unspec:DI [(vec_select:DF - (match_operand:V2DF 1 "<round_nimm_predicate>" "v,<round_constraint2>") + (match_operand:V2DF 1 "<round_nimm_scalar_predicate>" "v,<round_constraint2>") (parallel [(const_int 0)]))] UNSPEC_FIX_NOTRUNC))] "TARGET_SSE2 && TARGET_64BIT" @@ -4867,7 +4853,7 @@ [(set (match_operand:SI 0 "register_operand" "=r,r") (fix:SI (vec_select:DF - (match_operand:V2DF 1 "<round_saeonly_nimm_predicate>" "v,<round_saeonly_constraint2>") + (match_operand:V2DF 1 "<round_saeonly_nimm_scalar_predicate>" "v,<round_saeonly_constraint2>") (parallel [(const_int 0)]))))] "TARGET_SSE2" "%vcvttsd2si\t{<round_saeonly_op2>%1, %0|%0, %q1<round_saeonly_op2>}" @@ -4884,7 +4870,7 @@ [(set (match_operand:DI 0 "register_operand" "=r,r") (fix:DI (vec_select:DF - (match_operand:V2DF 1 "<round_saeonly_nimm_predicate>" "v,<round_saeonly_constraint2>") + (match_operand:V2DF 1 "<round_saeonly_nimm_scalar_predicate>" "v,<round_saeonly_constraint2>") (parallel [(const_int 0)]))))] "TARGET_SSE2 && TARGET_64BIT" "%vcvttsd2si{q}\t{<round_saeonly_op2>%1, %0|%0, %q1<round_saeonly_op2>}" @@ -5081,7 +5067,7 @@ (define_insn "sse2_cvtpd2dq<mask_name>" [(set (match_operand:V4SI 0 "register_operand" "=v") (vec_concat:V4SI - (unspec:V2SI [(match_operand:V2DF 1 "nonimmediate_operand" "vm")] + (unspec:V2SI [(match_operand:V2DF 1 "vector_operand" "vBm")] UNSPEC_FIX_NOTRUNC) (const_vector:V2SI [(const_int 0) (const_int 0)])))] "TARGET_SSE2 && <mask_avx512vl_condition>" @@ -5242,7 +5228,7 @@ (define_insn "sse2_cvttpd2dq<mask_name>" [(set (match_operand:V4SI 0 "register_operand" "=v") (vec_concat:V4SI - (fix:V2SI (match_operand:V2DF 1 "nonimmediate_operand" "vm")) + (fix:V2SI (match_operand:V2DF 1 "vector_operand" "vBm")) (const_vector:V2SI [(const_int 0) (const_int 0)])))] "TARGET_SSE2 && <mask_avx512vl_condition>" { @@ -5285,7 +5271,7 @@ (vec_merge:V2DF (float_extend:V2DF (vec_select:V2SF - (match_operand:V4SF 2 "<round_saeonly_nimm_predicate>" "x,m,<round_saeonly_constraint>") + (match_operand:V4SF 2 "<round_saeonly_nimm_scalar_predicate>" "x,m,<round_saeonly_constraint>") (parallel [(const_int 0) (const_int 1)]))) (match_operand:V2DF 1 "register_operand" "0,0,v") (const_int 1)))] @@ -5328,7 +5314,7 @@ [(set (match_operand:V4SF 0 "register_operand") (vec_concat:V4SF (float_truncate:V2SF - (match_operand:V2DF 1 "nonimmediate_operand")) + (match_operand:V2DF 1 "vector_operand")) (match_dup 2)))] "TARGET_SSE2" "operands[2] = CONST0_RTX (V2SFmode);") @@ -5338,7 +5324,7 @@ (vec_merge:V4SF (vec_concat:V4SF (float_truncate:V2SF - (match_operand:V2DF 1 "nonimmediate_operand")) + (match_operand:V2DF 1 "vector_operand")) (match_dup 4)) (match_operand:V4SF 2 "register_operand") (match_operand:QI 3 "register_operand")))] @@ -5349,7 +5335,7 @@ [(set (match_operand:V4SF 0 "register_operand" "=v") (vec_concat:V4SF (float_truncate:V2SF - (match_operand:V2DF 1 "nonimmediate_operand" "vm")) + (match_operand:V2DF 1 "vector_operand" "vBm")) (match_operand:V2SF 2 "const0_operand")))] "TARGET_SSE2 && <mask_avx512vl_condition>" { @@ -5478,7 +5464,7 @@ [(set (match_operand:V2DF 0 "register_operand" "=v") (float_extend:V2DF (vec_select:V2SF - (match_operand:V4SF 1 "nonimmediate_operand" "vm") + (match_operand:V4SF 1 "vector_operand" "vBm") (parallel [(const_int 0) (const_int 1)]))))] "TARGET_SSE2 && <mask_avx512vl_condition>" "%vcvtps2pd\t{%1, %0<mask_operand2>|%0<mask_operand2>, %q1}" @@ -5495,7 +5481,7 @@ (vec_select:V4SF (vec_concat:V8SF (match_dup 2) - (match_operand:V4SF 1 "nonimmediate_operand")) + (match_operand:V4SF 1 "vector_operand")) (parallel [(const_int 6) (const_int 7) (const_int 2) (const_int 3)]))) (set (match_operand:V2DF 0 "register_operand") @@ -5536,7 +5522,7 @@ [(set (match_operand:V2DF 0 "register_operand") (float_extend:V2DF (vec_select:V2SF - (match_operand:V4SF 1 "nonimmediate_operand") + (match_operand:V4SF 1 "vector_operand") (parallel [(const_int 0) (const_int 1)]))))] "TARGET_SSE2") @@ -5608,7 +5594,7 @@ (define_expand "vec_unpacks_float_hi_v4si" [(set (match_dup 2) (vec_select:V4SI - (match_operand:V4SI 1 "nonimmediate_operand") + (match_operand:V4SI 1 "vector_operand") (parallel [(const_int 2) (const_int 3) (const_int 2) (const_int 3)]))) (set (match_operand:V2DF 0 "register_operand") @@ -5623,14 +5609,14 @@ [(set (match_operand:V2DF 0 "register_operand") (float:V2DF (vec_select:V2SI - (match_operand:V4SI 1 "nonimmediate_operand") + (match_operand:V4SI 1 "vector_operand") (parallel [(const_int 0) (const_int 1)]))))] "TARGET_SSE2") (define_expand "vec_unpacks_float_hi_v8si" [(set (match_dup 2) (vec_select:V4SI - (match_operand:V8SI 1 "nonimmediate_operand") + (match_operand:V8SI 1 "vector_operand") (parallel [(const_int 4) (const_int 5) (const_int 6) (const_int 7)]))) (set (match_operand:V4DF 0 "register_operand") @@ -5676,7 +5662,7 @@ (define_expand "vec_unpacku_float_hi_v4si" [(set (match_dup 5) (vec_select:V4SI - (match_operand:V4SI 1 "nonimmediate_operand") + (match_operand:V4SI 1 "vector_operand") (parallel [(const_int 2) (const_int 3) (const_int 2) (const_int 3)]))) (set (match_dup 6) @@ -5713,7 +5699,7 @@ [(set (match_dup 5) (float:V2DF (vec_select:V2SI - (match_operand:V4SI 1 "nonimmediate_operand") + (match_operand:V4SI 1 "vector_operand") (parallel [(const_int 0) (const_int 1)])))) (set (match_dup 6) (lt:V2DF (match_dup 5) (match_dup 3))) @@ -5855,8 +5841,8 @@ (define_expand "vec_pack_trunc_v2df" [(match_operand:V4SF 0 "register_operand") - (match_operand:V2DF 1 "nonimmediate_operand") - (match_operand:V2DF 2 "nonimmediate_operand")] + (match_operand:V2DF 1 "vector_operand") + (match_operand:V2DF 2 "vector_operand")] "TARGET_SSE2" { rtx tmp0, tmp1; @@ -5917,8 +5903,8 @@ (define_expand "vec_pack_sfix_trunc_v2df" [(match_operand:V4SI 0 "register_operand") - (match_operand:V2DF 1 "nonimmediate_operand") - (match_operand:V2DF 2 "nonimmediate_operand")] + (match_operand:V2DF 1 "vector_operand") + (match_operand:V2DF 2 "vector_operand")] "TARGET_SSE2" { rtx tmp0, tmp1, tmp2; @@ -6014,8 +6000,8 @@ (define_expand "vec_pack_sfix_v2df" [(match_operand:V4SI 0 "register_operand") - (match_operand:V2DF 1 "nonimmediate_operand") - (match_operand:V2DF 2 "nonimmediate_operand")] + (match_operand:V2DF 1 "vector_operand") + (match_operand:V2DF 2 "vector_operand")] "TARGET_SSE2" { rtx tmp0, tmp1, tmp2; @@ -6218,7 +6204,7 @@ (vec_select:V4SF (vec_concat:V8SF (match_operand:V4SF 1 "register_operand" "0,v") - (match_operand:V4SF 2 "nonimmediate_operand" "xm,vm")) + (match_operand:V4SF 2 "vector_operand" "xBm,vm")) (parallel [(const_int 2) (const_int 6) (const_int 3) (const_int 7)])))] "TARGET_SSE && <mask_avx512vl_condition>" @@ -6323,7 +6309,7 @@ (vec_select:V4SF (vec_concat:V8SF (match_operand:V4SF 1 "register_operand" "0,x") - (match_operand:V4SF 2 "nonimmediate_operand" "xm,xm")) + (match_operand:V4SF 2 "vector_operand" "xBm,xm")) (parallel [(const_int 0) (const_int 4) (const_int 1) (const_int 5)])))] "TARGET_SSE" @@ -6357,7 +6343,7 @@ [(set (match_operand:V4SF 0 "register_operand" "=v") (vec_select:V4SF (vec_concat:V8SF - (match_operand:V4SF 1 "nonimmediate_operand" "vm") + (match_operand:V4SF 1 "vector_operand" "vBm") (match_dup 1)) (parallel [(const_int 1) (const_int 1) @@ -6410,7 +6396,7 @@ [(set (match_operand:V4SF 0 "register_operand" "=v") (vec_select:V4SF (vec_concat:V8SF - (match_operand:V4SF 1 "nonimmediate_operand" "vm") + (match_operand:V4SF 1 "vector_operand" "vBm") (match_dup 1)) (parallel [(const_int 0) (const_int 0) @@ -6505,7 +6491,7 @@ (define_expand "sse_shufps<mask_expand4_name>" [(match_operand:V4SF 0 "register_operand") (match_operand:V4SF 1 "register_operand") - (match_operand:V4SF 2 "nonimmediate_operand") + (match_operand:V4SF 2 "vector_operand") (match_operand:SI 3 "const_int_operand")] "TARGET_SSE" { @@ -6555,7 +6541,7 @@ (vec_select:VI4F_128 (vec_concat:<ssedoublevecmode> (match_operand:VI4F_128 1 "register_operand" "0,x") - (match_operand:VI4F_128 2 "nonimmediate_operand" "xm,xm")) + (match_operand:VI4F_128 2 "vector_operand" "xBm,xm")) (parallel [(match_operand 3 "const_0_to_3_operand") (match_operand 4 "const_0_to_3_operand") (match_operand 5 "const_4_to_7_operand") @@ -6651,6 +6637,7 @@ %vmovaps\t{%1, %0|%0, %1} %vmovlps\t{%1, %d0|%d0, %q1}" [(set_attr "type" "ssemov") + (set_attr "ssememalign" "64") (set_attr "prefix" "maybe_vex") (set_attr "mode" "V2SF,V4SF,V2SF")]) @@ -6776,7 +6763,7 @@ (set_attr "mode" "V4SF,V4SF,V4SF,V4SF,V4SF,V4SF,SF,DI,DI")]) ;; ??? In theory we can match memory for the MMX alternative, but allowing -;; nonimmediate_operand for operand 2 and *not* allowing memory for the SSE +;; vector_operand for operand 2 and *not* allowing memory for the SSE ;; alternatives pretty much forces the MMX alternative to be chosen. (define_insn "*vec_concatv2sf_sse" [(set (match_operand:V2SF 0 "register_operand" "=x,x,*y,*y") @@ -8501,7 +8488,7 @@ (define_expand "sse2_shufpd<mask_expand4_name>" [(match_operand:V2DF 0 "register_operand") (match_operand:V2DF 1 "register_operand") - (match_operand:V2DF 2 "nonimmediate_operand") + (match_operand:V2DF 2 "vector_operand") (match_operand:SI 3 "const_int_operand")] "TARGET_SSE2" { @@ -8576,7 +8563,7 @@ (vec_select:V2DI (vec_concat:V4DI (match_operand:V2DI 1 "register_operand" "0,v") - (match_operand:V2DI 2 "nonimmediate_operand" "xm,vm")) + (match_operand:V2DI 2 "vector_operand" "xBm,vm")) (parallel [(const_int 1) (const_int 3)])))] "TARGET_SSE2 && <mask_avx512vl_condition>" @@ -8626,7 +8613,7 @@ (vec_select:V2DI (vec_concat:V4DI (match_operand:V2DI 1 "register_operand" "0,v") - (match_operand:V2DI 2 "nonimmediate_operand" "xm,vm")) + (match_operand:V2DI 2 "vector_operand" "xBm,vm")) (parallel [(const_int 0) (const_int 2)])))] "TARGET_SSE2 && <mask_avx512vl_condition>" @@ -8644,7 +8631,7 @@ (vec_select:VI8F_128 (vec_concat:<ssedoublevecmode> (match_operand:VI8F_128 1 "register_operand" "0,x") - (match_operand:VI8F_128 2 "nonimmediate_operand" "xm,xm")) + (match_operand:VI8F_128 2 "vector_operand" "xBm,xm")) (parallel [(match_operand 3 "const_0_to_1_operand") (match_operand 4 "const_2_to_3_operand")])))] "TARGET_SSE2" @@ -9615,15 +9602,15 @@ [(set (match_operand:VI_AVX2 0 "register_operand") (minus:VI_AVX2 (match_dup 2) - (match_operand:VI_AVX2 1 "nonimmediate_operand")))] + (match_operand:VI_AVX2 1 "vector_operand")))] "TARGET_SSE2" "operands[2] = force_reg (<MODE>mode, CONST0_RTX (<MODE>mode));") (define_expand "<plusminus_insn><mode>3" [(set (match_operand:VI_AVX2 0 "register_operand") (plusminus:VI_AVX2 - (match_operand:VI_AVX2 1 "nonimmediate_operand") - (match_operand:VI_AVX2 2 "nonimmediate_operand")))] + (match_operand:VI_AVX2 1 "vector_operand") + (match_operand:VI_AVX2 2 "vector_operand")))] "TARGET_SSE2" "ix86_fixup_binary_operands_no_copy (<CODE>, <MODE>mode, operands);") @@ -9652,8 +9639,8 @@ (define_insn "*<plusminus_insn><mode>3" [(set (match_operand:VI_AVX2 0 "register_operand" "=x,v") (plusminus:VI_AVX2 - (match_operand:VI_AVX2 1 "nonimmediate_operand" "<comm>0,v") - (match_operand:VI_AVX2 2 "nonimmediate_operand" "xm,vm")))] + (match_operand:VI_AVX2 1 "vector_operand" "<comm>0,v") + (match_operand:VI_AVX2 2 "vector_operand" "xBm,vm")))] "TARGET_SSE2 && ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)" "@ @@ -9697,16 +9684,16 @@ (define_expand "<sse2_avx2>_<plusminus_insn><mode>3<mask_name>" [(set (match_operand:VI12_AVX2 0 "register_operand") (sat_plusminus:VI12_AVX2 - (match_operand:VI12_AVX2 1 "nonimmediate_operand") - (match_operand:VI12_AVX2 2 "nonimmediate_operand")))] + (match_operand:VI12_AVX2 1 "vector_operand") + (match_operand:VI12_AVX2 2 "vector_operand")))] "TARGET_SSE2 && <mask_mode512bit_condition> && <mask_avx512bw_condition>" "ix86_fixup_binary_operands_no_copy (<CODE>, <MODE>mode, operands);") (define_insn "*<sse2_avx2>_<plusminus_insn><mode>3<mask_name>" [(set (match_operand:VI12_AVX2 0 "register_operand" "=x,v") (sat_plusminus:VI12_AVX2 - (match_operand:VI12_AVX2 1 "nonimmediate_operand" "<comm>0,v") - (match_operand:VI12_AVX2 2 "nonimmediate_operand" "xm,vm")))] + (match_operand:VI12_AVX2 1 "vector_operand" "<comm>0,v") + (match_operand:VI12_AVX2 2 "vector_operand" "xBm,vm")))] "TARGET_SSE2 && <mask_mode512bit_condition> && <mask_avx512bw_condition> && ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)" "@ @@ -9730,15 +9717,15 @@ (define_expand "mul<mode>3<mask_name>" [(set (match_operand:VI2_AVX2 0 "register_operand") - (mult:VI2_AVX2 (match_operand:VI2_AVX2 1 "nonimmediate_operand") - (match_operand:VI2_AVX2 2 "nonimmediate_operand")))] + (mult:VI2_AVX2 (match_operand:VI2_AVX2 1 "vector_operand") + (match_operand:VI2_AVX2 2 "vector_operand")))] "TARGET_SSE2 && <mask_mode512bit_condition> && <mask_avx512bw_condition>" "ix86_fixup_binary_operands_no_copy (MULT, <MODE>mode, operands);") (define_insn "*mul<mode>3<mask_name>" [(set (match_operand:VI2_AVX2 0 "register_operand" "=x,v") - (mult:VI2_AVX2 (match_operand:VI2_AVX2 1 "nonimmediate_operand" "%0,v") - (match_operand:VI2_AVX2 2 "nonimmediate_operand" "xm,vm")))] + (mult:VI2_AVX2 (match_operand:VI2_AVX2 1 "vector_operand" "%0,v") + (match_operand:VI2_AVX2 2 "vector_operand" "xBm,vm")))] "TARGET_SSE2 && ix86_binary_operator_ok (MULT, <MODE>mode, operands) && <mask_mode512bit_condition> && <mask_avx512bw_condition>" @@ -9757,9 +9744,9 @@ (lshiftrt:<ssedoublemode> (mult:<ssedoublemode> (any_extend:<ssedoublemode> - (match_operand:VI2_AVX2 1 "nonimmediate_operand")) + (match_operand:VI2_AVX2 1 "vector_operand")) (any_extend:<ssedoublemode> - (match_operand:VI2_AVX2 2 "nonimmediate_operand"))) + (match_operand:VI2_AVX2 2 "vector_operand"))) (const_int 16))))] "TARGET_SSE2 && <mask_mode512bit_condition> && <mask_avx512bw_condition>" @@ -9771,9 +9758,9 @@ (lshiftrt:<ssedoublemode> (mult:<ssedoublemode> (any_extend:<ssedoublemode> - (match_operand:VI2_AVX2 1 "nonimmediate_operand" "%0,v")) + (match_operand:VI2_AVX2 1 "vector_operand" "%0,v")) (any_extend:<ssedoublemode> - (match_operand:VI2_AVX2 2 "nonimmediate_operand" "xm,vm"))) + (match_operand:VI2_AVX2 2 "vector_operand" "xBm,vm"))) (const_int 16))))] "TARGET_SSE2 && ix86_binary_operator_ok (MULT, <MODE>mode, operands) @@ -9873,11 +9860,11 @@ (mult:V2DI (zero_extend:V2DI (vec_select:V2SI - (match_operand:V4SI 1 "nonimmediate_operand") + (match_operand:V4SI 1 "vector_operand") (parallel [(const_int 0) (const_int 2)]))) (zero_extend:V2DI (vec_select:V2SI - (match_operand:V4SI 2 "nonimmediate_operand") + (match_operand:V4SI 2 "vector_operand") (parallel [(const_int 0) (const_int 2)])))))] "TARGET_SSE2 && <mask_avx512vl_condition>" "ix86_fixup_binary_operands_no_copy (MULT, V4SImode, operands);") @@ -9887,11 +9874,11 @@ (mult:V2DI (zero_extend:V2DI (vec_select:V2SI - (match_operand:V4SI 1 "nonimmediate_operand" "%0,v") + (match_operand:V4SI 1 "vector_operand" "%0,v") (parallel [(const_int 0) (const_int 2)]))) (zero_extend:V2DI (vec_select:V2SI - (match_operand:V4SI 2 "nonimmediate_operand" "xm,vm") + (match_operand:V4SI 2 "vector_operand" "xBm,vm") (parallel [(const_int 0) (const_int 2)])))))] "TARGET_SSE2 && <mask_avx512vl_condition> && ix86_binary_operator_ok (MULT, V4SImode, operands)" @@ -9991,11 +9978,11 @@ (mult:V2DI (sign_extend:V2DI (vec_select:V2SI - (match_operand:V4SI 1 "nonimmediate_operand") + (match_operand:V4SI 1 "vector_operand") (parallel [(const_int 0) (const_int 2)]))) (sign_extend:V2DI (vec_select:V2SI - (match_operand:V4SI 2 "nonimmediate_operand") + (match_operand:V4SI 2 "vector_operand") (parallel [(const_int 0) (const_int 2)])))))] "TARGET_SSE4_1 && <mask_avx512vl_condition>" "ix86_fixup_binary_operands_no_copy (MULT, V4SImode, operands);") @@ -10005,11 +9992,11 @@ (mult:V2DI (sign_extend:V2DI (vec_select:V2SI - (match_operand:V4SI 1 "nonimmediate_operand" "%0,0,v") + (match_operand:V4SI 1 "vector_operand" "%0,0,v") (parallel [(const_int 0) (const_int 2)]))) (sign_extend:V2DI (vec_select:V2SI - (match_operand:V4SI 2 "nonimmediate_operand" "Yrm,*xm,vm") + (match_operand:V4SI 2 "vector_operand" "YrBm,*xBm,vm") (parallel [(const_int 0) (const_int 2)])))))] "TARGET_SSE4_1 && <mask_avx512vl_condition> && ix86_binary_operator_ok (MULT, V4SImode, operands)" @@ -10113,12 +10100,12 @@ (mult:V4SI (sign_extend:V4SI (vec_select:V4HI - (match_operand:V8HI 1 "nonimmediate_operand") + (match_operand:V8HI 1 "vector_operand") (parallel [(const_int 0) (const_int 2) (const_int 4) (const_int 6)]))) (sign_extend:V4SI (vec_select:V4HI - (match_operand:V8HI 2 "nonimmediate_operand") + (match_operand:V8HI 2 "vector_operand") (parallel [(const_int 0) (const_int 2) (const_int 4) (const_int 6)])))) (mult:V4SI @@ -10139,12 +10126,12 @@ (mult:V4SI (sign_extend:V4SI (vec_select:V4HI - (match_operand:V8HI 1 "nonimmediate_operand" "%0,x") + (match_operand:V8HI 1 "vector_operand" "%0,x") (parallel [(const_int 0) (const_int 2) (const_int 4) (const_int 6)]))) (sign_extend:V4SI (vec_select:V4HI - (match_operand:V8HI 2 "nonimmediate_operand" "xm,xm") + (match_operand:V8HI 2 "vector_operand" "xBm,xm") (parallel [(const_int 0) (const_int 2) (const_int 4) (const_int 6)])))) (mult:V4SI @@ -10187,9 +10174,9 @@ { if (TARGET_SSE4_1) { - if (!nonimmediate_operand (operands[1], <MODE>mode)) + if (!vector_operand (operands[1], <MODE>mode)) operands[1] = force_reg (<MODE>mode, operands[1]); - if (!nonimmediate_operand (operands[2], <MODE>mode)) + if (!vector_operand (operands[2], <MODE>mode)) operands[2] = force_reg (<MODE>mode, operands[2]); ix86_fixup_binary_operands_no_copy (MULT, <MODE>mode, operands); } @@ -10203,8 +10190,8 @@ (define_insn "*<sse4_1_avx2>_mul<mode>3<mask_name>" [(set (match_operand:VI4_AVX512F 0 "register_operand" "=Yr,*x,v") (mult:VI4_AVX512F - (match_operand:VI4_AVX512F 1 "nonimmediate_operand" "%0,0,v") - (match_operand:VI4_AVX512F 2 "nonimmediate_operand" "Yrm,*xm,vm")))] + (match_operand:VI4_AVX512F 1 "vector_operand" "%0,0,v") + (match_operand:VI4_AVX512F 2 "vector_operand" "YrBm,*xBm,vm")))] "TARGET_SSE4_1 && ix86_binary_operator_ok (MULT, <MODE>mode, operands) && <mask_mode512bit_condition>" "@ pmulld\t{%2, %0|%0, %2} @@ -10256,8 +10243,8 @@ ;; named patterns, but signed V4SI needs special help for plain SSE2. (define_expand "vec_widen_smult_even_v4si" [(match_operand:V2DI 0 "register_operand") - (match_operand:V4SI 1 "nonimmediate_operand") - (match_operand:V4SI 2 "nonimmediate_operand")] + (match_operand:V4SI 1 "vector_operand") + (match_operand:V4SI 2 "vector_operand")] "TARGET_SSE2" { ix86_expand_mul_widen_evenodd (operands[0], operands[1], operands[2], @@ -10313,8 +10300,8 @@ (define_expand "usadv16qi" [(match_operand:V4SI 0 "register_operand") (match_operand:V16QI 1 "register_operand") - (match_operand:V16QI 2 "nonimmediate_operand") - (match_operand:V4SI 3 "nonimmediate_operand")] + (match_operand:V16QI 2 "vector_operand") + (match_operand:V4SI 3 "vector_operand")] "TARGET_SSE2" { rtx t1 = gen_reg_rtx (V2DImode); @@ -10654,8 +10641,8 @@ (define_expand "<code><mode>3" [(set (match_operand:VI124_128 0 "register_operand") (smaxmin:VI124_128 - (match_operand:VI124_128 1 "nonimmediate_operand") - (match_operand:VI124_128 2 "nonimmediate_operand")))] + (match_operand:VI124_128 1 "vector_operand") + (match_operand:VI124_128 2 "vector_operand")))] "TARGET_SSE2" { if (TARGET_SSE4_1 || <MODE>mode == V8HImode) @@ -10693,8 +10680,8 @@ (define_insn "*sse4_1_<code><mode>3<mask_name>" [(set (match_operand:VI14_128 0 "register_operand" "=Yr,*x,v") (smaxmin:VI14_128 - (match_operand:VI14_128 1 "nonimmediate_operand" "%0,0,v") - (match_operand:VI14_128 2 "nonimmediate_operand" "Yrm,*xm,vm")))] + (match_operand:VI14_128 1 "vector_operand" "%0,0,v") + (match_operand:VI14_128 2 "vector_operand" "YrBm,*xBm,vm")))] "TARGET_SSE4_1 && <mask_mode512bit_condition> && ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)" @@ -10711,8 +10698,8 @@ (define_insn "*<code>v8hi3" [(set (match_operand:V8HI 0 "register_operand" "=x,x") (smaxmin:V8HI - (match_operand:V8HI 1 "nonimmediate_operand" "%0,x") - (match_operand:V8HI 2 "nonimmediate_operand" "xm,xm")))] + (match_operand:V8HI 1 "vector_operand" "%0,x") + (match_operand:V8HI 2 "vector_operand" "xBm,xm")))] "TARGET_SSE2 && ix86_binary_operator_ok (<CODE>, V8HImode, operands)" "@ p<maxmin_int>w\t{%2, %0|%0, %2} @@ -10727,8 +10714,8 @@ (define_expand "<code><mode>3" [(set (match_operand:VI124_128 0 "register_operand") (umaxmin:VI124_128 - (match_operand:VI124_128 1 "nonimmediate_operand") - (match_operand:VI124_128 2 "nonimmediate_operand")))] + (match_operand:VI124_128 1 "vector_operand") + (match_operand:VI124_128 2 "vector_operand")))] "TARGET_SSE2" { if (TARGET_SSE4_1 || <MODE>mode == V16QImode) @@ -10777,8 +10764,8 @@ (define_insn "*sse4_1_<code><mode>3<mask_name>" [(set (match_operand:VI24_128 0 "register_operand" "=Yr,*x,v") (umaxmin:VI24_128 - (match_operand:VI24_128 1 "nonimmediate_operand" "%0,0,v") - (match_operand:VI24_128 2 "nonimmediate_operand" "Yrm,*xm,vm")))] + (match_operand:VI24_128 1 "vector_operand" "%0,0,v") + (match_operand:VI24_128 2 "vector_operand" "YrBm,*xBm,vm")))] "TARGET_SSE4_1 && <mask_mode512bit_condition> && ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)" @@ -10795,8 +10782,8 @@ (define_insn "*<code>v16qi3" [(set (match_operand:V16QI 0 "register_operand" "=x,x") (umaxmin:V16QI - (match_operand:V16QI 1 "nonimmediate_operand" "%0,x") - (match_operand:V16QI 2 "nonimmediate_operand" "xm,xm")))] + (match_operand:V16QI 1 "vector_operand" "%0,x") + (match_operand:V16QI 2 "vector_operand" "xBm,xm")))] "TARGET_SSE2 && ix86_binary_operator_ok (<CODE>, V16QImode, operands)" "@ p<maxmin_int>b\t{%2, %0|%0, %2} @@ -10881,8 +10868,8 @@ (define_insn "*sse4_1_eqv2di3" [(set (match_operand:V2DI 0 "register_operand" "=Yr,*x,x") (eq:V2DI - (match_operand:V2DI 1 "nonimmediate_operand" "%0,0,x") - (match_operand:V2DI 2 "nonimmediate_operand" "Yrm,*xm,xm")))] + (match_operand:V2DI 1 "vector_operand" "%0,0,x") + (match_operand:V2DI 2 "vector_operand" "YrBm,*xBm,xm")))] "TARGET_SSE4_1 && ix86_binary_operator_ok (EQ, V2DImode, operands)" "@ pcmpeqq\t{%2, %0|%0, %2} @@ -10897,8 +10884,8 @@ (define_insn "*sse2_eq<mode>3" [(set (match_operand:VI124_128 0 "register_operand" "=x,x") (eq:VI124_128 - (match_operand:VI124_128 1 "nonimmediate_operand" "%0,x") - (match_operand:VI124_128 2 "nonimmediate_operand" "xm,xm")))] + (match_operand:VI124_128 1 "vector_operand" "%0,x") + (match_operand:VI124_128 2 "vector_operand" "xBm,xm")))] "TARGET_SSE2 && !TARGET_XOP && ix86_binary_operator_ok (EQ, <MODE>mode, operands)" "@ @@ -10913,16 +10900,16 @@ (define_expand "sse2_eq<mode>3" [(set (match_operand:VI124_128 0 "register_operand") (eq:VI124_128 - (match_operand:VI124_128 1 "nonimmediate_operand") - (match_operand:VI124_128 2 "nonimmediate_operand")))] + (match_operand:VI124_128 1 "vector_operand") + (match_operand:VI124_128 2 "vector_operand")))] "TARGET_SSE2 && !TARGET_XOP " "ix86_fixup_binary_operands_no_copy (EQ, <MODE>mode, operands);") (define_expand "sse4_1_eqv2di3" [(set (match_operand:V2DI 0 "register_operand") (eq:V2DI - (match_operand:V2DI 1 "nonimmediate_operand") - (match_operand:V2DI 2 "nonimmediate_operand")))] + (match_operand:V2DI 1 "vector_operand") + (match_operand:V2DI 2 "vector_operand")))] "TARGET_SSE4_1" "ix86_fixup_binary_operands_no_copy (EQ, V2DImode, operands);") @@ -10930,7 +10917,7 @@ [(set (match_operand:V2DI 0 "register_operand" "=Yr,*x,x") (gt:V2DI (match_operand:V2DI 1 "register_operand" "0,0,x") - (match_operand:V2DI 2 "nonimmediate_operand" "Yrm,*xm,xm")))] + (match_operand:V2DI 2 "vector_operand" "YrBm,*xBm,xm")))] "TARGET_SSE4_2" "@ pcmpgtq\t{%2, %0|%0, %2} @@ -10982,7 +10969,7 @@ [(set (match_operand:VI124_128 0 "register_operand" "=x,x") (gt:VI124_128 (match_operand:VI124_128 1 "register_operand" "0,x") - (match_operand:VI124_128 2 "nonimmediate_operand" "xm,xm")))] + (match_operand:VI124_128 2 "vector_operand" "xBm,xm")))] "TARGET_SSE2 && !TARGET_XOP" "@ pcmpgt<ssemodesuffix>\t{%2, %0|%0, %2} @@ -11031,7 +11018,7 @@ [(set (match_operand:V_128 0 "register_operand") (if_then_else:V_128 (match_operator 3 "" - [(match_operand:VI124_128 4 "nonimmediate_operand") + [(match_operand:VI124_128 4 "vector_operand") (match_operand:VI124_128 5 "general_operand")]) (match_operand:V_128 1) (match_operand:V_128 2)))] @@ -11048,7 +11035,7 @@ [(set (match_operand:VI8F_128 0 "register_operand") (if_then_else:VI8F_128 (match_operator 3 "" - [(match_operand:V2DI 4 "nonimmediate_operand") + [(match_operand:V2DI 4 "vector_operand") (match_operand:V2DI 5 "general_operand")]) (match_operand:VI8F_128 1) (match_operand:VI8F_128 2)))] @@ -11097,8 +11084,8 @@ [(set (match_operand:V_128 0 "register_operand") (if_then_else:V_128 (match_operator 3 "" - [(match_operand:VI124_128 4 "nonimmediate_operand") - (match_operand:VI124_128 5 "nonimmediate_operand")]) + [(match_operand:VI124_128 4 "vector_operand") + (match_operand:VI124_128 5 "vector_operand")]) (match_operand:V_128 1 "general_operand") (match_operand:V_128 2 "general_operand")))] "TARGET_SSE2 @@ -11114,8 +11101,8 @@ [(set (match_operand:VI8F_128 0 "register_operand") (if_then_else:VI8F_128 (match_operator 3 "" - [(match_operand:V2DI 4 "nonimmediate_operand") - (match_operand:V2DI 5 "nonimmediate_operand")]) + [(match_operand:V2DI 4 "vector_operand") + (match_operand:V2DI 5 "vector_operand")]) (match_operand:VI8F_128 1 "general_operand") (match_operand:VI8F_128 2 "general_operand")))] "TARGET_SSE4_2" @@ -11177,7 +11164,7 @@ (define_expand "one_cmpl<mode>2" [(set (match_operand:VI 0 "register_operand") - (xor:VI (match_operand:VI 1 "nonimmediate_operand") + (xor:VI (match_operand:VI 1 "vector_operand") (match_dup 2)))] "TARGET_SSE" { @@ -11194,7 +11181,7 @@ [(set (match_operand:VI_AVX2 0 "register_operand") (and:VI_AVX2 (not:VI_AVX2 (match_operand:VI_AVX2 1 "register_operand")) - (match_operand:VI_AVX2 2 "nonimmediate_operand")))] + (match_operand:VI_AVX2 2 "vector_operand")))] "TARGET_SSE2") (define_expand "<sse2_avx2>_andnot<mode>3_mask" @@ -11223,7 +11210,7 @@ [(set (match_operand:VI 0 "register_operand" "=x,v") (and:VI (not:VI (match_operand:VI 1 "register_operand" "0,v")) - (match_operand:VI 2 "nonimmediate_operand" "xm,vm")))] + (match_operand:VI 2 "vector_operand" "xBm,vm")))] "TARGET_SSE" { static char buf[64]; @@ -11360,8 +11347,8 @@ (define_insn "<mask_codefor><code><mode>3<mask_name>" [(set (match_operand:VI48_AVX_AVX512F 0 "register_operand" "=x,v") (any_logic:VI48_AVX_AVX512F - (match_operand:VI48_AVX_AVX512F 1 "nonimmediate_operand" "%0,v") - (match_operand:VI48_AVX_AVX512F 2 "nonimmediate_operand" "xm,vm")))] + (match_operand:VI48_AVX_AVX512F 1 "vector_operand" "%0,v") + (match_operand:VI48_AVX_AVX512F 2 "vector_operand" "xBm,vm")))] "TARGET_SSE && <mask_mode512bit_condition> && ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)" { @@ -11456,8 +11443,8 @@ (define_insn "*<code><mode>3" [(set (match_operand:VI12_AVX_AVX512F 0 "register_operand" "=x,v") (any_logic: VI12_AVX_AVX512F - (match_operand:VI12_AVX_AVX512F 1 "nonimmediate_operand" "%0,v") - (match_operand:VI12_AVX_AVX512F 2 "nonimmediate_operand" "xm,vm")))] + (match_operand:VI12_AVX_AVX512F 1 "vector_operand" "%0,v") + (match_operand:VI12_AVX_AVX512F 2 "vector_operand" "xBm,vm")))] "TARGET_SSE && ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)" { static char buf[64]; @@ -11637,7 +11624,7 @@ (ss_truncate:<ssehalfvecmode> (match_operand:<sseunpackmode> 1 "register_operand" "0,v")) (ss_truncate:<ssehalfvecmode> - (match_operand:<sseunpackmode> 2 "nonimmediate_operand" "xm,vm"))))] + (match_operand:<sseunpackmode> 2 "vector_operand" "xBm,vm"))))] "TARGET_SSE2 && <mask_mode512bit_condition> && <mask_avx512bw_condition>" "@ packsswb\t{%2, %0|%0, %2} @@ -11654,7 +11641,7 @@ (ss_truncate:<ssehalfvecmode> (match_operand:<sseunpackmode> 1 "register_operand" "0,v")) (ss_truncate:<ssehalfvecmode> - (match_operand:<sseunpackmode> 2 "nonimmediate_operand" "xm,vm"))))] + (match_operand:<sseunpackmode> 2 "vector_operand" "xBm,vm"))))] "TARGET_SSE2 && <mask_mode512bit_condition> && <mask_avx512bw_condition>" "@ packssdw\t{%2, %0|%0, %2} @@ -11671,7 +11658,7 @@ (us_truncate:<ssehalfvecmode> (match_operand:<sseunpackmode> 1 "register_operand" "0,v")) (us_truncate:<ssehalfvecmode> - (match_operand:<sseunpackmode> 2 "nonimmediate_operand" "xm,vm"))))] + (match_operand:<sseunpackmode> 2 "vector_operand" "xBm,vm"))))] "TARGET_SSE2 && <mask_mode512bit_condition> && <mask_avx512bw_condition>" "@ packuswb\t{%2, %0|%0, %2} @@ -11759,7 +11746,7 @@ (vec_select:V16QI (vec_concat:V32QI (match_operand:V16QI 1 "register_operand" "0,v") - (match_operand:V16QI 2 "nonimmediate_operand" "xm,vm")) + (match_operand:V16QI 2 "vector_operand" "xBm,vm")) (parallel [(const_int 8) (const_int 24) (const_int 9) (const_int 25) (const_int 10) (const_int 26) @@ -11855,7 +11842,7 @@ (vec_select:V16QI (vec_concat:V32QI (match_operand:V16QI 1 "register_operand" "0,v") - (match_operand:V16QI 2 "nonimmediate_operand" "xm,vm")) + (match_operand:V16QI 2 "vector_operand" "xBm,vm")) (parallel [(const_int 0) (const_int 16) (const_int 1) (const_int 17) (const_int 2) (const_int 18) @@ -11927,7 +11914,7 @@ (vec_select:V8HI (vec_concat:V16HI (match_operand:V8HI 1 "register_operand" "0,v") - (match_operand:V8HI 2 "nonimmediate_operand" "xm,vm")) + (match_operand:V8HI 2 "vector_operand" "xBm,vm")) (parallel [(const_int 4) (const_int 12) (const_int 5) (const_int 13) (const_int 6) (const_int 14) @@ -11995,7 +11982,7 @@ (vec_select:V8HI (vec_concat:V16HI (match_operand:V8HI 1 "register_operand" "0,v") - (match_operand:V8HI 2 "nonimmediate_operand" "xm,vm")) + (match_operand:V8HI 2 "vector_operand" "xBm,vm")) (parallel [(const_int 0) (const_int 8) (const_int 1) (const_int 9) (const_int 2) (const_int 10) @@ -12052,7 +12039,7 @@ (vec_select:V4SI (vec_concat:V8SI (match_operand:V4SI 1 "register_operand" "0,v") - (match_operand:V4SI 2 "nonimmediate_operand" "xm,vm")) + (match_operand:V4SI 2 "vector_operand" "xBm,vm")) (parallel [(const_int 2) (const_int 6) (const_int 3) (const_int 7)])))] "TARGET_SSE2 && <mask_avx512vl_condition>" @@ -12106,7 +12093,7 @@ (vec_select:V4SI (vec_concat:V8SI (match_operand:V4SI 1 "register_operand" "0,v") - (match_operand:V4SI 2 "nonimmediate_operand" "xm,vm")) + (match_operand:V4SI 2 "vector_operand" "xBm,vm")) (parallel [(const_int 0) (const_int 4) (const_int 1) (const_int 5)])))] "TARGET_SSE2 && <mask_avx512vl_condition>" @@ -12773,7 +12760,7 @@ (define_expand "sse2_pshufd" [(match_operand:V4SI 0 "register_operand") - (match_operand:V4SI 1 "nonimmediate_operand") + (match_operand:V4SI 1 "vector_operand") (match_operand:SI 2 "const_int_operand")] "TARGET_SSE2" { @@ -12789,7 +12776,7 @@ (define_insn "sse2_pshufd_1<mask_name>" [(set (match_operand:V4SI 0 "register_operand" "=v") (vec_select:V4SI - (match_operand:V4SI 1 "nonimmediate_operand" "vm") + (match_operand:V4SI 1 "vector_operand" "vBm") (parallel [(match_operand 2 "const_0_to_3_operand") (match_operand 3 "const_0_to_3_operand") (match_operand 4 "const_0_to_3_operand") @@ -12925,7 +12912,7 @@ (define_expand "sse2_pshuflw" [(match_operand:V8HI 0 "register_operand") - (match_operand:V8HI 1 "nonimmediate_operand") + (match_operand:V8HI 1 "vector_operand") (match_operand:SI 2 "const_int_operand")] "TARGET_SSE2" { @@ -12941,7 +12928,7 @@ (define_insn "sse2_pshuflw_1<mask_name>" [(set (match_operand:V8HI 0 "register_operand" "=v") (vec_select:V8HI - (match_operand:V8HI 1 "nonimmediate_operand" "vm") + (match_operand:V8HI 1 "vector_operand" "vBm") (parallel [(match_operand 2 "const_0_to_3_operand") (match_operand 3 "const_0_to_3_operand") (match_operand 4 "const_0_to_3_operand") @@ -13082,7 +13069,7 @@ (define_expand "sse2_pshufhw" [(match_operand:V8HI 0 "register_operand") - (match_operand:V8HI 1 "nonimmediate_operand") + (match_operand:V8HI 1 "vector_operand") (match_operand:SI 2 "const_int_operand")] "TARGET_SSE2" { @@ -13098,7 +13085,7 @@ (define_insn "sse2_pshufhw_1<mask_name>" [(set (match_operand:V8HI 0 "register_operand" "=v") (vec_select:V8HI - (match_operand:V8HI 1 "nonimmediate_operand" "vm") + (match_operand:V8HI 1 "vector_operand" "vBm") (parallel [(const_int 0) (const_int 1) (const_int 2) @@ -13576,9 +13563,9 @@ (plus:<ssedoublemode> (plus:<ssedoublemode> (zero_extend:<ssedoublemode> - (match_operand:VI12_AVX2 1 "nonimmediate_operand")) + (match_operand:VI12_AVX2 1 "vector_operand")) (zero_extend:<ssedoublemode> - (match_operand:VI12_AVX2 2 "nonimmediate_operand"))) + (match_operand:VI12_AVX2 2 "vector_operand"))) (match_dup <mask_expand_op3>)) (const_int 1))))] "TARGET_SSE2 && <mask_mode512bit_condition> && <mask_avx512bw_condition>" @@ -13603,9 +13590,9 @@ (plus:<ssedoublemode> (plus:<ssedoublemode> (zero_extend:<ssedoublemode> - (match_operand:VI12_AVX2 1 "nonimmediate_operand" "%0,v")) + (match_operand:VI12_AVX2 1 "vector_operand" "%0,v")) (zero_extend:<ssedoublemode> - (match_operand:VI12_AVX2 2 "nonimmediate_operand" "xm,vm"))) + (match_operand:VI12_AVX2 2 "vector_operand" "xBm,vm"))) (match_operand:VI12_AVX2 <mask_expand_op3> "const1_operand")) (const_int 1))))] "TARGET_SSE2 && <mask_mode512bit_condition> && <mask_avx512bw_condition> @@ -13625,7 +13612,7 @@ [(set (match_operand:VI8_AVX2_AVX512BW 0 "register_operand" "=x,v") (unspec:VI8_AVX2_AVX512BW [(match_operand:<ssebytemode> 1 "register_operand" "0,v") - (match_operand:<ssebytemode> 2 "nonimmediate_operand" "xm,vm")] + (match_operand:<ssebytemode> 2 "vector_operand" "xBm,vm")] UNSPEC_PSADBW))] "TARGET_SSE2" "@ @@ -13891,7 +13878,7 @@ (vec_concat:V2HI (ssse3_plusminus:HI (vec_select:HI - (match_operand:V8HI 2 "nonimmediate_operand" "xm,xm") + (match_operand:V8HI 2 "vector_operand" "xBm,xm") (parallel [(const_int 0)])) (vec_select:HI (match_dup 2) (parallel [(const_int 1)]))) (ssse3_plusminus:HI @@ -14004,7 +13991,7 @@ (vec_concat:V2SI (plusminus:SI (vec_select:SI - (match_operand:V4SI 2 "nonimmediate_operand" "xm,xm") + (match_operand:V4SI 2 "vector_operand" "xBm,xm") (parallel [(const_int 0)])) (vec_select:SI (match_dup 2) (parallel [(const_int 1)]))) (plusminus:SI @@ -14159,7 +14146,7 @@ (const_int 12) (const_int 14)]))) (sign_extend:V8HI (vec_select:V8QI - (match_operand:V16QI 2 "nonimmediate_operand" "xm,xm") + (match_operand:V16QI 2 "vector_operand" "xBm,xm") (parallel [(const_int 0) (const_int 2) (const_int 4) (const_int 6) (const_int 8) (const_int 10) @@ -14274,9 +14261,9 @@ (lshiftrt:<ssedoublemode> (mult:<ssedoublemode> (sign_extend:<ssedoublemode> - (match_operand:VI2_AVX2 1 "nonimmediate_operand" "%0,v")) + (match_operand:VI2_AVX2 1 "vector_operand" "%0,v")) (sign_extend:<ssedoublemode> - (match_operand:VI2_AVX2 2 "nonimmediate_operand" "xm,vm"))) + (match_operand:VI2_AVX2 2 "vector_operand" "xBm,vm"))) (const_int 14)) (match_operand:VI2_AVX2 3 "const1_operand")) (const_int 1))))] @@ -14317,7 +14304,7 @@ [(set (match_operand:VI1_AVX512 0 "register_operand" "=x,v") (unspec:VI1_AVX512 [(match_operand:VI1_AVX512 1 "register_operand" "0,v") - (match_operand:VI1_AVX512 2 "nonimmediate_operand" "xm,vm")] + (match_operand:VI1_AVX512 2 "vector_operand" "xBm,vm")] UNSPEC_PSHUFB))] "TARGET_SSSE3 && <mask_mode512bit_condition> && <mask_avx512bw_condition>" "@ @@ -14347,7 +14334,7 @@ [(set (match_operand:VI124_AVX2 0 "register_operand" "=x,x") (unspec:VI124_AVX2 [(match_operand:VI124_AVX2 1 "register_operand" "0,x") - (match_operand:VI124_AVX2 2 "nonimmediate_operand" "xm,xm")] + (match_operand:VI124_AVX2 2 "vector_operand" "xBm,xm")] UNSPEC_PSIGN))] "TARGET_SSSE3" "@ @@ -14399,7 +14386,7 @@ [(set (match_operand:SSESCALARMODE 0 "register_operand" "=x,v") (unspec:SSESCALARMODE [(match_operand:SSESCALARMODE 1 "register_operand" "0,v") - (match_operand:SSESCALARMODE 2 "nonimmediate_operand" "xm,vm") + (match_operand:SSESCALARMODE 2 "vector_operand" "xBm,vm") (match_operand:SI 3 "const_0_to_255_mul_8_operand" "n,n")] UNSPEC_PALIGNR))] "TARGET_SSSE3" @@ -14454,7 +14441,7 @@ (define_insn "*abs<mode>2" [(set (match_operand:VI1248_AVX512VL_AVX512BW 0 "register_operand" "=v") (abs:VI1248_AVX512VL_AVX512BW - (match_operand:VI1248_AVX512VL_AVX512BW 1 "nonimmediate_operand" "vm")))] + (match_operand:VI1248_AVX512VL_AVX512BW 1 "vector_operand" "vBm")))] "TARGET_SSSE3" "%vpabs<ssemodesuffix>\t{%1, %0|%0, %1}" [(set_attr "type" "sselog1") @@ -14492,7 +14479,7 @@ (define_expand "abs<mode>2" [(set (match_operand:VI1248_AVX512VL_AVX512BW 0 "register_operand") (abs:VI1248_AVX512VL_AVX512BW - (match_operand:VI1248_AVX512VL_AVX512BW 1 "nonimmediate_operand")))] + (match_operand:VI1248_AVX512VL_AVX512BW 1 "vector_operand")))] "TARGET_SSE2" { if (!TARGET_SSSE3) @@ -14606,7 +14593,7 @@ (define_insn "<sse4_1>_blend<ssemodesuffix><avxsizesuffix>" [(set (match_operand:VF_128_256 0 "register_operand" "=Yr,*x,x") (vec_merge:VF_128_256 - (match_operand:VF_128_256 2 "nonimmediate_operand" "Yrm,*xm,xm") + (match_operand:VF_128_256 2 "vector_operand" "YrBm,*xBm,xm") (match_operand:VF_128_256 1 "register_operand" "0,0,x") (match_operand:SI 3 "const_0_to_<blendbits>_operand")))] "TARGET_SSE4_1" @@ -14626,7 +14613,7 @@ [(set (match_operand:VF_128_256 0 "register_operand" "=Yr,*x,x") (unspec:VF_128_256 [(match_operand:VF_128_256 1 "register_operand" "0,0,x") - (match_operand:VF_128_256 2 "nonimmediate_operand" "Yrm,*xm,xm") + (match_operand:VF_128_256 2 "vector_operand" "YrBm,*xBm,xm") (match_operand:VF_128_256 3 "register_operand" "Yz,Yz,x")] UNSPEC_BLENDV))] "TARGET_SSE4_1" @@ -14646,8 +14633,8 @@ (define_insn "<sse4_1>_dp<ssemodesuffix><avxsizesuffix>" [(set (match_operand:VF_128_256 0 "register_operand" "=Yr,*x,x") (unspec:VF_128_256 - [(match_operand:VF_128_256 1 "nonimmediate_operand" "%0,0,x") - (match_operand:VF_128_256 2 "nonimmediate_operand" "Yrm,*xm,xm") + [(match_operand:VF_128_256 1 "vector_operand" "%0,0,x") + (match_operand:VF_128_256 2 "vector_operand" "YrBm,*xBm,xm") (match_operand:SI 3 "const_0_to_255_operand" "n,n,n")] UNSPEC_DP))] "TARGET_SSE4_1" @@ -14684,7 +14671,7 @@ [(set (match_operand:VI1_AVX2 0 "register_operand" "=Yr,*x,x") (unspec:VI1_AVX2 [(match_operand:VI1_AVX2 1 "register_operand" "0,0,x") - (match_operand:VI1_AVX2 2 "nonimmediate_operand" "Yrm,*xm,xm") + (match_operand:VI1_AVX2 2 "vector_operand" "YrBm,*xBm,xm") (match_operand:SI 3 "const_0_to_255_operand" "n,n,n")] UNSPEC_MPSADBW))] "TARGET_SSE4_1" @@ -14707,7 +14694,7 @@ (us_truncate:<ssehalfvecmode> (match_operand:<sseunpackmode> 1 "register_operand" "0,0,v")) (us_truncate:<ssehalfvecmode> - (match_operand:<sseunpackmode> 2 "nonimmediate_operand" "Yrm,*xm,vm"))))] + (match_operand:<sseunpackmode> 2 "vector_operand" "YrBm,*xBm,vm"))))] "TARGET_SSE4_1 && <mask_mode512bit_condition> && <mask_avx512bw_condition>" "@ packusdw\t{%2, %0|%0, %2} @@ -14723,7 +14710,7 @@ [(set (match_operand:VI1_AVX2 0 "register_operand" "=Yr,*x,x") (unspec:VI1_AVX2 [(match_operand:VI1_AVX2 1 "register_operand" "0,0,x") - (match_operand:VI1_AVX2 2 "nonimmediate_operand" "Yrm,*xm,xm") + (match_operand:VI1_AVX2 2 "vector_operand" "YrBm,*xBm,xm") (match_operand:VI1_AVX2 3 "register_operand" "Yz,Yz,x")] UNSPEC_BLENDV))] "TARGET_SSE4_1" @@ -14742,7 +14729,7 @@ (define_insn "sse4_1_pblendw" [(set (match_operand:V8HI 0 "register_operand" "=Yr,*x,x") (vec_merge:V8HI - (match_operand:V8HI 2 "nonimmediate_operand" "Yrm,*xm,xm") + (match_operand:V8HI 2 "vector_operand" "YrBm,*xBm,xm") (match_operand:V8HI 1 "register_operand" "0,0,x") (match_operand:SI 3 "const_0_to_255_operand" "n,n,n")))] "TARGET_SSE4_1" @@ -14803,7 +14790,7 @@ (define_insn "sse4_1_phminposuw" [(set (match_operand:V8HI 0 "register_operand" "=Yr,*x") - (unspec:V8HI [(match_operand:V8HI 1 "nonimmediate_operand" "Yrm,*xm")] + (unspec:V8HI [(match_operand:V8HI 1 "vector_operand" "YrBm,*xBm")] UNSPEC_PHMINPOSUW))] "TARGET_SSE4_1" "%vphminposuw\t{%1, %0|%0, %1}" @@ -15063,7 +15050,7 @@ (define_insn "<sse4_1>_ptest<mode>" [(set (reg:CC FLAGS_REG) (unspec:CC [(match_operand:V_AVX 0 "register_operand" "Yr, *x, x") - (match_operand:V_AVX 1 "nonimmediate_operand" "Yrm, *xm, xm")] + (match_operand:V_AVX 1 "vector_operand" "YrBm, *xBm, xm")] UNSPEC_PTEST))] "TARGET_SSE4_1" "%vptest\t{%1, %0|%0, %1}" @@ -15081,7 +15068,7 @@ (define_insn "<sse4_1>_round<ssemodesuffix><avxsizesuffix>" [(set (match_operand:VF_128_256 0 "register_operand" "=Yr,*x") (unspec:VF_128_256 - [(match_operand:VF_128_256 1 "nonimmediate_operand" "Yrm,*xm") + [(match_operand:VF_128_256 1 "vector_operand" "YrBm,*xBm") (match_operand:SI 2 "const_0_to_15_operand" "n,n")] UNSPEC_ROUND))] "TARGET_ROUND" @@ -15099,7 +15086,7 @@ (define_expand "<sse4_1>_round<ssemodesuffix>_sfix<avxsizesuffix>" [(match_operand:<sseintvecmode> 0 "register_operand") - (match_operand:VF1_128_256 1 "nonimmediate_operand") + (match_operand:VF1_128_256 1 "vector_operand") (match_operand:SI 2 "const_0_to_15_operand")] "TARGET_ROUND" { @@ -15125,8 +15112,8 @@ (define_expand "<sse4_1>_round<ssemodesuffix>_vec_pack_sfix<avxsizesuffix>" [(match_operand:<ssepackfltmode> 0 "register_operand") - (match_operand:VF2 1 "nonimmediate_operand") - (match_operand:VF2 2 "nonimmediate_operand") + (match_operand:VF2 1 "vector_operand") + (match_operand:VF2 2 "vector_operand") (match_operand:SI 3 "const_0_to_15_operand")] "TARGET_ROUND" { @@ -15667,7 +15654,7 @@ (define_expand "avx512pf_gatherpf<mode>sf" [(unspec - [(match_operand:<avx512fmaskmode> 0 "register_or_constm1_operand") + [(match_operand:<avx512fmaskmode> 0 "register_operand") (mem:<GATHER_SCATTER_SF_MEM_MODE> (match_par_dup 5 [(match_operand 2 "vsib_address_operand") @@ -15709,37 +15696,10 @@ (set_attr "prefix" "evex") (set_attr "mode" "XI")]) -(define_insn "*avx512pf_gatherpf<mode>sf" - [(unspec - [(const_int -1) - (match_operator:<GATHER_SCATTER_SF_MEM_MODE> 4 "vsib_mem_operator" - [(unspec:P - [(match_operand:P 1 "vsib_address_operand" "Tv") - (match_operand:VI48_512 0 "register_operand" "v") - (match_operand:SI 2 "const1248_operand" "n")] - UNSPEC_VSIBADDR)]) - (match_operand:SI 3 "const_2_to_3_operand" "n")] - UNSPEC_GATHER_PREFETCH)] - "TARGET_AVX512PF" -{ - switch (INTVAL (operands[3])) - { - case 3: - return "vgatherpf0<ssemodesuffix>ps\t{%4|%4}"; - case 2: - return "vgatherpf1<ssemodesuffix>ps\t{%4|%4}"; - default: - gcc_unreachable (); - } -} - [(set_attr "type" "sse") - (set_attr "prefix" "evex") - (set_attr "mode" "XI")]) - ;; Packed double variants (define_expand "avx512pf_gatherpf<mode>df" [(unspec - [(match_operand:<avx512fmaskmode> 0 "register_or_constm1_operand") + [(match_operand:<avx512fmaskmode> 0 "register_operand") (mem:V8DF (match_par_dup 5 [(match_operand 2 "vsib_address_operand") @@ -15781,37 +15741,10 @@ (set_attr "prefix" "evex") (set_attr "mode" "XI")]) -(define_insn "*avx512pf_gatherpf<mode>df" - [(unspec - [(const_int -1) - (match_operator:V8DF 4 "vsib_mem_operator" - [(unspec:P - [(match_operand:P 1 "vsib_address_operand" "Tv") - (match_operand:VI4_256_8_512 0 "register_operand" "v") - (match_operand:SI 2 "const1248_operand" "n")] - UNSPEC_VSIBADDR)]) - (match_operand:SI 3 "const_2_to_3_operand" "n")] - UNSPEC_GATHER_PREFETCH)] - "TARGET_AVX512PF" -{ - switch (INTVAL (operands[3])) - { - case 3: - return "vgatherpf0<ssemodesuffix>pd\t{%4|%4}"; - case 2: - return "vgatherpf1<ssemodesuffix>pd\t{%4|%4}"; - default: - gcc_unreachable (); - } -} - [(set_attr "type" "sse") - (set_attr "prefix" "evex") - (set_attr "mode" "XI")]) - ;; Packed float variants (define_expand "avx512pf_scatterpf<mode>sf" [(unspec - [(match_operand:<avx512fmaskmode> 0 "register_or_constm1_operand") + [(match_operand:<avx512fmaskmode> 0 "register_operand") (mem:<GATHER_SCATTER_SF_MEM_MODE> (match_par_dup 5 [(match_operand 2 "vsib_address_operand") @@ -15855,39 +15788,10 @@ (set_attr "prefix" "evex") (set_attr "mode" "XI")]) -(define_insn "*avx512pf_scatterpf<mode>sf" - [(unspec - [(const_int -1) - (match_operator:<GATHER_SCATTER_SF_MEM_MODE> 4 "vsib_mem_operator" - [(unspec:P - [(match_operand:P 1 "vsib_address_operand" "Tv") - (match_operand:VI48_512 0 "register_operand" "v") - (match_operand:SI 2 "const1248_operand" "n")] - UNSPEC_VSIBADDR)]) - (match_operand:SI 3 "const2367_operand" "n")] - UNSPEC_SCATTER_PREFETCH)] - "TARGET_AVX512PF" -{ - switch (INTVAL (operands[3])) - { - case 3: - case 7: - return "vscatterpf0<ssemodesuffix>ps\t{%4|%4}"; - case 2: - case 6: - return "vscatterpf1<ssemodesuffix>ps\t{%4|%4}"; - default: - gcc_unreachable (); - } -} - [(set_attr "type" "sse") - (set_attr "prefix" "evex") - (set_attr "mode" "XI")]) - ;; Packed double variants (define_expand "avx512pf_scatterpf<mode>df" [(unspec - [(match_operand:<avx512fmaskmode> 0 "register_or_constm1_operand") + [(match_operand:<avx512fmaskmode> 0 "register_operand") (mem:V8DF (match_par_dup 5 [(match_operand 2 "vsib_address_operand") @@ -15931,35 +15835,6 @@ (set_attr "prefix" "evex") (set_attr "mode" "XI")]) -(define_insn "*avx512pf_scatterpf<mode>df" - [(unspec - [(const_int -1) - (match_operator:V8DF 4 "vsib_mem_operator" - [(unspec:P - [(match_operand:P 1 "vsib_address_operand" "Tv") - (match_operand:VI4_256_8_512 0 "register_operand" "v") - (match_operand:SI 2 "const1248_operand" "n")] - UNSPEC_VSIBADDR)]) - (match_operand:SI 3 "const2367_operand" "n")] - UNSPEC_SCATTER_PREFETCH)] - "TARGET_AVX512PF" -{ - switch (INTVAL (operands[3])) - { - case 3: - case 7: - return "vscatterpf0<ssemodesuffix>pd\t{%4|%4}"; - case 2: - case 6: - return "vscatterpf1<ssemodesuffix>pd\t{%4|%4}"; - default: - gcc_unreachable (); - } -} - [(set_attr "type" "sse") - (set_attr "prefix" "evex") - (set_attr "mode" "XI")]) - (define_insn "avx512er_exp2<mode><mask_name><round_saeonly_name>" [(set (match_operand:VF_512 0 "register_operand" "=v") (unspec:VF_512 @@ -16926,7 +16801,7 @@ (define_insn "aesenc" [(set (match_operand:V2DI 0 "register_operand" "=x,x") (unspec:V2DI [(match_operand:V2DI 1 "register_operand" "0,x") - (match_operand:V2DI 2 "nonimmediate_operand" "xm,xm")] + (match_operand:V2DI 2 "vector_operand" "xBm,xm")] UNSPEC_AESENC))] "TARGET_AES" "@ @@ -16942,7 +16817,7 @@ (define_insn "aesenclast" [(set (match_operand:V2DI 0 "register_operand" "=x,x") (unspec:V2DI [(match_operand:V2DI 1 "register_operand" "0,x") - (match_operand:V2DI 2 "nonimmediate_operand" "xm,xm")] + (match_operand:V2DI 2 "vector_operand" "xBm,xm")] UNSPEC_AESENCLAST))] "TARGET_AES" "@ @@ -16958,7 +16833,7 @@ (define_insn "aesdec" [(set (match_operand:V2DI 0 "register_operand" "=x,x") (unspec:V2DI [(match_operand:V2DI 1 "register_operand" "0,x") - (match_operand:V2DI 2 "nonimmediate_operand" "xm,xm")] + (match_operand:V2DI 2 "vector_operand" "xBm,xm")] UNSPEC_AESDEC))] "TARGET_AES" "@ @@ -16974,7 +16849,7 @@ (define_insn "aesdeclast" [(set (match_operand:V2DI 0 "register_operand" "=x,x") (unspec:V2DI [(match_operand:V2DI 1 "register_operand" "0,x") - (match_operand:V2DI 2 "nonimmediate_operand" "xm,xm")] + (match_operand:V2DI 2 "vector_operand" "xBm,xm")] UNSPEC_AESDECLAST))] "TARGET_AES" "@ @@ -16989,7 +16864,7 @@ (define_insn "aesimc" [(set (match_operand:V2DI 0 "register_operand" "=x") - (unspec:V2DI [(match_operand:V2DI 1 "nonimmediate_operand" "xm")] + (unspec:V2DI [(match_operand:V2DI 1 "vector_operand" "xBm")] UNSPEC_AESIMC))] "TARGET_AES" "%vaesimc\t{%1, %0|%0, %1}" @@ -17000,7 +16875,7 @@ (define_insn "aeskeygenassist" [(set (match_operand:V2DI 0 "register_operand" "=x") - (unspec:V2DI [(match_operand:V2DI 1 "nonimmediate_operand" "xm") + (unspec:V2DI [(match_operand:V2DI 1 "vector_operand" "xBm") (match_operand:SI 2 "const_0_to_255_operand" "n")] UNSPEC_AESKEYGENASSIST))] "TARGET_AES" @@ -17014,7 +16889,7 @@ (define_insn "pclmulqdq" [(set (match_operand:V2DI 0 "register_operand" "=x,x") (unspec:V2DI [(match_operand:V2DI 1 "register_operand" "0,x") - (match_operand:V2DI 2 "nonimmediate_operand" "xm,xm") + (match_operand:V2DI 2 "vector_operand" "xBm,xm") (match_operand:SI 3 "const_0_to_255_operand" "n,n")] UNSPEC_PCLMUL))] "TARGET_PCLMUL" @@ -19152,7 +19027,7 @@ [(set (match_operand:V4SI 0 "register_operand" "=x") (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "0") - (match_operand:V4SI 2 "nonimmediate_operand" "xm")] + (match_operand:V4SI 2 "vector_operand" "xBm")] UNSPEC_SHA1MSG1))] "TARGET_SHA" "sha1msg1\t{%2, %0|%0, %2}" @@ -19163,7 +19038,7 @@ [(set (match_operand:V4SI 0 "register_operand" "=x") (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "0") - (match_operand:V4SI 2 "nonimmediate_operand" "xm")] + (match_operand:V4SI 2 "vector_operand" "xBm")] UNSPEC_SHA1MSG2))] "TARGET_SHA" "sha1msg2\t{%2, %0|%0, %2}" @@ -19174,7 +19049,7 @@ [(set (match_operand:V4SI 0 "register_operand" "=x") (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "0") - (match_operand:V4SI 2 "nonimmediate_operand" "xm")] + (match_operand:V4SI 2 "vector_operand" "xBm")] UNSPEC_SHA1NEXTE))] "TARGET_SHA" "sha1nexte\t{%2, %0|%0, %2}" @@ -19185,7 +19060,7 @@ [(set (match_operand:V4SI 0 "register_operand" "=x") (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "0") - (match_operand:V4SI 2 "nonimmediate_operand" "xm") + (match_operand:V4SI 2 "vector_operand" "xBm") (match_operand:SI 3 "const_0_to_3_operand" "n")] UNSPEC_SHA1RNDS4))] "TARGET_SHA" @@ -19198,7 +19073,7 @@ [(set (match_operand:V4SI 0 "register_operand" "=x") (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "0") - (match_operand:V4SI 2 "nonimmediate_operand" "xm")] + (match_operand:V4SI 2 "vector_operand" "xBm")] UNSPEC_SHA256MSG1))] "TARGET_SHA" "sha256msg1\t{%2, %0|%0, %2}" @@ -19209,7 +19084,7 @@ [(set (match_operand:V4SI 0 "register_operand" "=x") (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "0") - (match_operand:V4SI 2 "nonimmediate_operand" "xm")] + (match_operand:V4SI 2 "vector_operand" "xBm")] UNSPEC_SHA256MSG2))] "TARGET_SHA" "sha256msg2\t{%2, %0|%0, %2}" @@ -19220,7 +19095,7 @@ [(set (match_operand:V4SI 0 "register_operand" "=x") (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "0") - (match_operand:V4SI 2 "nonimmediate_operand" "xm") + (match_operand:V4SI 2 "vector_operand" "xBm") (match_operand:V4SI 3 "register_operand" "Yz")] UNSPEC_SHA256RNDS2))] "TARGET_SHA" diff --git a/gcc/config/i386/ssemath.h b/gcc/config/i386/ssemath.h index 802e6017ff2..eeebeef5d7b 100644 --- a/gcc/config/i386/ssemath.h +++ b/gcc/config/i386/ssemath.h @@ -1,4 +1,4 @@ -/* Copyright (C) 2010-2015 Free Software Foundation, Inc. +/* Copyright (C) 2010-2016 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/i386/stringop.def b/gcc/config/i386/stringop.def index 0d6a5fab672..b4abbd7ef52 100644 --- a/gcc/config/i386/stringop.def +++ b/gcc/config/i386/stringop.def @@ -1,5 +1,5 @@ /* Definitions for stringop strategy for IA-32. - Copyright (C) 2013-2015 Free Software Foundation, Inc. + Copyright (C) 2013-2016 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/i386/stringop.opt b/gcc/config/i386/stringop.opt index 6b6d1e0ff24..ad64f371436 100644 --- a/gcc/config/i386/stringop.opt +++ b/gcc/config/i386/stringop.opt @@ -1,5 +1,5 @@ /* Definitions for stringop option handling for IA-32. - Copyright (C) 2013-2015 Free Software Foundation, Inc. + Copyright (C) 2013-2016 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/i386/subst.md b/gcc/config/i386/subst.md index 1c5a541245f..e2f67c4a00c 100644 --- a/gcc/config/i386/subst.md +++ b/gcc/config/i386/subst.md @@ -1,5 +1,5 @@ ;; GCC machine description for AVX512F instructions -;; Copyright (C) 2013-2015 Free Software Foundation, Inc. +;; Copyright (C) 2013-2016 Free Software Foundation, Inc. ;; ;; This file is part of GCC. ;; @@ -123,7 +123,8 @@ (define_subst_attr "round_constraint" "round" "vm" "v") (define_subst_attr "round_constraint2" "round" "m" "v") (define_subst_attr "round_constraint3" "round" "rm" "r") -(define_subst_attr "round_nimm_predicate" "round" "nonimmediate_operand" "register_operand") +(define_subst_attr "round_nimm_predicate" "round" "vector_operand" "register_operand") +(define_subst_attr "round_nimm_scalar_predicate" "round" "nonimmediate_operand" "register_operand") (define_subst_attr "round_prefix" "round" "vex" "evex") (define_subst_attr "round_mode512bit_condition" "round" "1" "(<MODE>mode == V16SFmode || <MODE>mode == V8DFmode @@ -162,7 +163,8 @@ (define_subst_attr "round_saeonly_sd_mask_op5" "round_saeonly" "" "<round_saeonly_sd_mask_operand5>") (define_subst_attr "round_saeonly_constraint" "round_saeonly" "vm" "v") (define_subst_attr "round_saeonly_constraint2" "round_saeonly" "m" "v") -(define_subst_attr "round_saeonly_nimm_predicate" "round_saeonly" "nonimmediate_operand" "register_operand") +(define_subst_attr "round_saeonly_nimm_predicate" "round_saeonly" "vector_operand" "register_operand") +(define_subst_attr "round_saeonly_nimm_scalar_predicate" "round_saeonly" "nonimmediate_operand" "register_operand") (define_subst_attr "round_saeonly_mode512bit_condition" "round_saeonly" "1" "(<MODE>mode == V16SFmode || <MODE>mode == V8DFmode || <MODE>mode == V8DImode diff --git a/gcc/config/i386/sync.md b/gcc/config/i386/sync.md index 59573d40a99..85a2b9ad630 100644 --- a/gcc/config/i386/sync.md +++ b/gcc/config/i386/sync.md @@ -1,5 +1,5 @@ ;; GCC machine description for i386 synchronization instructions. -;; Copyright (C) 2005-2015 Free Software Foundation, Inc. +;; Copyright (C) 2005-2016 Free Software Foundation, Inc. ;; ;; This file is part of GCC. ;; diff --git a/gcc/config/i386/sysv4.h b/gcc/config/i386/sysv4.h index 9f945074056..35e91027bf5 100644 --- a/gcc/config/i386/sysv4.h +++ b/gcc/config/i386/sysv4.h @@ -1,5 +1,5 @@ /* Target definitions for GCC for Intel 80386 running System V.4 - Copyright (C) 1991-2015 Free Software Foundation, Inc. + Copyright (C) 1991-2016 Free Software Foundation, Inc. Written by Ron Guilmette (rfg@netcom.com). diff --git a/gcc/config/i386/t-cygming b/gcc/config/i386/t-cygming index 7775e79e820..db724fdc12e 100644 --- a/gcc/config/i386/t-cygming +++ b/gcc/config/i386/t-cygming @@ -1,4 +1,4 @@ -# Copyright (C) 2003-2015 Free Software Foundation, Inc. +# Copyright (C) 2003-2016 Free Software Foundation, Inc. # # This file is part of GCC. # diff --git a/gcc/config/i386/t-djgpp b/gcc/config/i386/t-djgpp new file mode 100644 index 00000000000..dd3b32ac351 --- /dev/null +++ b/gcc/config/i386/t-djgpp @@ -0,0 +1,8 @@ + +EXTRA_OBJS += djgpp.o + +djgpp.o: $(srcdir)/config/i386/djgpp.c $(CONFIG_H) $(SYSTEM_H) coretypes.h \ + $(TM_H) $(RTL_H) $(REGS_H) hard-reg-set.h output.h $(TREE_H) flags.h \ + $(TM_P_H) $(HASH_TABLE_H) $(GGC_H) $(LTO_STREAMER_H) + $(COMPILER) -c $(ALL_COMPILERFLAGS) $(ALL_CPPFLAGS) $(INCLUDES) \ + $(srcdir)/config/i386/djgpp.c diff --git a/gcc/config/i386/t-i386 b/gcc/config/i386/t-i386 index 5bb1be0427b..a90097cf8ce 100644 --- a/gcc/config/i386/t-i386 +++ b/gcc/config/i386/t-i386 @@ -1,4 +1,4 @@ -# Copyright (C) 2008-2015 Free Software Foundation, Inc. +# Copyright (C) 2008-2016 Free Software Foundation, Inc. # # This file is part of GCC. # diff --git a/gcc/config/i386/t-interix b/gcc/config/i386/t-interix index dd59b85088d..39edbe5ccb6 100644 --- a/gcc/config/i386/t-interix +++ b/gcc/config/i386/t-interix @@ -1,4 +1,4 @@ -# Copyright (C) 2011-2015 Free Software Foundation, Inc. +# Copyright (C) 2011-2016 Free Software Foundation, Inc. # # This file is part of GCC. # diff --git a/gcc/config/i386/t-linux64 b/gcc/config/i386/t-linux64 index f6dbb78ffcf..c0cc8a37246 100644 --- a/gcc/config/i386/t-linux64 +++ b/gcc/config/i386/t-linux64 @@ -1,4 +1,4 @@ -# Copyright (C) 2002-2015 Free Software Foundation, Inc. +# Copyright (C) 2002-2016 Free Software Foundation, Inc. # # This file is part of GCC. # diff --git a/gcc/config/i386/t-rtems b/gcc/config/i386/t-rtems index ed84021531a..4a68cd50b01 100644 --- a/gcc/config/i386/t-rtems +++ b/gcc/config/i386/t-rtems @@ -1,4 +1,4 @@ -# Copyright (C) 1999-2015 Free Software Foundation, Inc. +# Copyright (C) 1999-2016 Free Software Foundation, Inc. # # This file is part of GCC. # diff --git a/gcc/config/i386/t-sol2 b/gcc/config/i386/t-sol2 index a00d52e9e42..4bd1dee9ddb 100644 --- a/gcc/config/i386/t-sol2 +++ b/gcc/config/i386/t-sol2 @@ -1,4 +1,4 @@ -# Copyright (C) 2004-2015 Free Software Foundation, Inc. +# Copyright (C) 2004-2016 Free Software Foundation, Inc. # # This file is part of GCC. # diff --git a/gcc/config/i386/tbmintrin.h b/gcc/config/i386/tbmintrin.h index cc265bbba5f..d4b3588d15c 100644 --- a/gcc/config/i386/tbmintrin.h +++ b/gcc/config/i386/tbmintrin.h @@ -1,4 +1,4 @@ -/* Copyright (C) 2010-2015 Free Software Foundation, Inc. +/* Copyright (C) 2010-2016 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/i386/tmmintrin.h b/gcc/config/i386/tmmintrin.h index ac2e343eddf..6ec867d464b 100644 --- a/gcc/config/i386/tmmintrin.h +++ b/gcc/config/i386/tmmintrin.h @@ -1,4 +1,4 @@ -/* Copyright (C) 2006-2015 Free Software Foundation, Inc. +/* Copyright (C) 2006-2016 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/i386/unix.h b/gcc/config/i386/unix.h index 3ccd031882c..e73ffb3de7e 100644 --- a/gcc/config/i386/unix.h +++ b/gcc/config/i386/unix.h @@ -1,5 +1,5 @@ /* Definitions for Unix assembler syntax for the Intel 80386. - Copyright (C) 1988-2015 Free Software Foundation, Inc. + Copyright (C) 1988-2016 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/i386/vxworks.h b/gcc/config/i386/vxworks.h index 6abdf837a73..b5960b1c658 100644 --- a/gcc/config/i386/vxworks.h +++ b/gcc/config/i386/vxworks.h @@ -1,5 +1,5 @@ /* IA32 VxWorks target definitions for GNU compiler. - Copyright (C) 2003-2015 Free Software Foundation, Inc. + Copyright (C) 2003-2016 Free Software Foundation, Inc. Updated by CodeSourcery, LLC. This file is part of GCC. diff --git a/gcc/config/i386/vxworksae.h b/gcc/config/i386/vxworksae.h index c2ce8c8c576..4455298febb 100644 --- a/gcc/config/i386/vxworksae.h +++ b/gcc/config/i386/vxworksae.h @@ -1,5 +1,5 @@ /* IA32 VxWorks AE target definitions for GNU compiler. - Copyright (C) 2005-2015 Free Software Foundation, Inc. + Copyright (C) 2005-2016 Free Software Foundation, Inc. Contributed by CodeSourcery, LLC. This file is part of GCC. diff --git a/gcc/config/i386/winnt-cxx.c b/gcc/config/i386/winnt-cxx.c index 8cb1347061e..f156ba87271 100644 --- a/gcc/config/i386/winnt-cxx.c +++ b/gcc/config/i386/winnt-cxx.c @@ -1,6 +1,6 @@ /* Target support for C++ classes on Windows. Contributed by Danny Smith (dannysmith@users.sourceforge.net) - Copyright (C) 2005-2015 Free Software Foundation, Inc. + Copyright (C) 2005-2016 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/i386/winnt-stubs.c b/gcc/config/i386/winnt-stubs.c index 95aa9f20e77..39955b799ac 100644 --- a/gcc/config/i386/winnt-stubs.c +++ b/gcc/config/i386/winnt-stubs.c @@ -1,6 +1,6 @@ /* Dummy subroutines for language-specific support on Windows. Contributed by Danny Smith (dannysmith@users.sourceforge.net) - Copyright (C) 2005-2015 Free Software Foundation, Inc. + Copyright (C) 2005-2016 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/i386/winnt.c b/gcc/config/i386/winnt.c index ec670cf4bfe..53abf475bce 100644 --- a/gcc/config/i386/winnt.c +++ b/gcc/config/i386/winnt.c @@ -1,6 +1,6 @@ /* Subroutines for insn-output.c for Windows NT. Contributed by Douglas Rupp (drupp@cs.washington.edu) - Copyright (C) 1995-2015 Free Software Foundation, Inc. + Copyright (C) 1995-2016 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/i386/wmmintrin.h b/gcc/config/i386/wmmintrin.h index 37eac1fb1c8..be79f4332a7 100644 --- a/gcc/config/i386/wmmintrin.h +++ b/gcc/config/i386/wmmintrin.h @@ -1,4 +1,4 @@ -/* Copyright (C) 2008-2015 Free Software Foundation, Inc. +/* Copyright (C) 2008-2016 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/i386/x-mingw32 b/gcc/config/i386/x-mingw32 index f0884b8dfda..1d28a702a9d 100644 --- a/gcc/config/i386/x-mingw32 +++ b/gcc/config/i386/x-mingw32 @@ -1,4 +1,4 @@ -# Copyright (C) 2003-2015 Free Software Foundation, Inc. +# Copyright (C) 2003-2016 Free Software Foundation, Inc. # # This file is part of GCC. # diff --git a/gcc/config/i386/x86-64.h b/gcc/config/i386/x86-64.h index a1e145ff29d..204f128d5b0 100644 --- a/gcc/config/i386/x86-64.h +++ b/gcc/config/i386/x86-64.h @@ -1,5 +1,5 @@ /* OS independent definitions for AMD x86-64. - Copyright (C) 2001-2015 Free Software Foundation, Inc. + Copyright (C) 2001-2016 Free Software Foundation, Inc. Contributed by Bo Thorsen <bo@suse.de>. This file is part of GCC. diff --git a/gcc/config/i386/x86-tune.def b/gcc/config/i386/x86-tune.def index b2d39219124..9d25e51d407 100644 --- a/gcc/config/i386/x86-tune.def +++ b/gcc/config/i386/x86-tune.def @@ -1,5 +1,5 @@ /* Definitions of x86 tunable features. - Copyright (C) 2013-2015 Free Software Foundation, Inc. + Copyright (C) 2013-2016 Free Software Foundation, Inc. This file is part of GCC. @@ -550,3 +550,8 @@ DEF_TUNE (X86_TUNE_PROMOTE_QI_REGS, "promote_qi_regs", 0) unrolling small loop less important. For, such architectures we adjust the unroll factor so that the unrolled loop fits the loop buffer. */ DEF_TUNE (X86_TUNE_ADJUST_UNROLL, "adjust_unroll_factor", m_BDVER3 | m_BDVER4) + +/* X86_TUNE_ONE_IF_CONV_INSNS: Restrict a number of set insns to be + if-converted to one. */ +DEF_TUNE (X86_TUNE_ONE_IF_CONV_INSN, "one_if_conv_insn", + m_SILVERMONT | m_KNL | m_INTEL | m_CORE_ALL | m_GENERIC) diff --git a/gcc/config/i386/x86intrin.h b/gcc/config/i386/x86intrin.h index 9b292b35434..e666c4ed635 100644 --- a/gcc/config/i386/x86intrin.h +++ b/gcc/config/i386/x86intrin.h @@ -1,4 +1,4 @@ -/* Copyright (C) 2008-2015 Free Software Foundation, Inc. +/* Copyright (C) 2008-2016 Free Software Foundation, Inc. This file is part of GCC. @@ -95,6 +95,8 @@ #include <clzerointrin.h> +#include <pkuintrin.h> + #endif /* __iamcu__ */ #endif /* _X86INTRIN_H_INCLUDED */ diff --git a/gcc/config/i386/xm-cygwin.h b/gcc/config/i386/xm-cygwin.h index e40d11defa2..92bd1087f93 100644 --- a/gcc/config/i386/xm-cygwin.h +++ b/gcc/config/i386/xm-cygwin.h @@ -1,6 +1,6 @@ /* Configuration for GCC for hosting on Windows NT. using a unix style C library. - Copyright (C) 1995-2015 Free Software Foundation, Inc. + Copyright (C) 1995-2016 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/i386/xm-djgpp.h b/gcc/config/i386/xm-djgpp.h index 626be2fcff0..94e6ff614a7 100644 --- a/gcc/config/i386/xm-djgpp.h +++ b/gcc/config/i386/xm-djgpp.h @@ -1,5 +1,5 @@ /* Configuration for GCC for Intel 80386 running DJGPP. - Copyright (C) 1988-2015 Free Software Foundation, Inc. + Copyright (C) 1988-2016 Free Software Foundation, Inc. This file is part of GCC. @@ -22,6 +22,31 @@ along with GCC; see the file COPYING3. If not see #define HOST_EXECUTABLE_SUFFIX ".exe" +/* Define standard DJGPP installation paths. */ +/* We override default /usr or /usr/local part with /dev/env/DJDIR which */ +/* points to actual DJGPP installation directory. */ + +/* Native system include directory */ +#undef NATIVE_SYSTEM_HEADER_DIR +#define NATIVE_SYSTEM_HEADER_DIR "/dev/env/DJDIR/include/" + +/* Search for as.exe and ld.exe in DJGPP's binary directory. */ +#undef MD_EXEC_PREFIX +#define MD_EXEC_PREFIX "/dev/env/DJDIR/bin/" + +/* Standard DJGPP library and startup files */ +#undef STANDARD_STARTFILE_PREFIX_1 +#define STANDARD_STARTFILE_PREFIX_1 "/dev/env/DJDIR/lib/" + +/* Define STANDARD_STARTFILE_PREFIX_2 equal to STANDARD_STARTFILE_PREFIX_1 + to avoid gcc.c redefining it to /usr/lib */ +#undef STANDARD_STARTFILE_PREFIX_2 +#define STANDARD_STARTFILE_PREFIX_1 "/dev/env/DJDIR/lib/" + +/* Make sure that gcc will not look for .h files in /usr/local/include + unless user explicitly requests it. */ +#undef LOCAL_INCLUDE_DIR + /* System dependent initialization for collect2 to tell system() to act like Unix. */ #define COLLECT2_HOST_INITIALIZATION \ @@ -57,12 +82,12 @@ along with GCC; see the file COPYING3. If not see to try and figure out what's wrong. */ \ char *djgpp = getenv ("DJGPP"); \ if (djgpp == NULL) \ - fatal ("environment variable DJGPP not defined"); \ + fatal_error (UNKNOWN_LOCATION, "environment variable DJGPP not defined"); \ else if (access (djgpp, R_OK) == 0) \ - fatal ("environment variable DJGPP points to missing file '%s'", \ + fatal_error (UNKNOWN_LOCATION, "environment variable DJGPP points to missing file '%s'", \ djgpp); \ else \ - fatal ("environment variable DJGPP points to corrupt file '%s'", \ + fatal_error (UNKNOWN_LOCATION, "environment variable DJGPP points to corrupt file '%s'", \ djgpp); \ } \ } while (0) @@ -80,4 +105,11 @@ along with GCC; see the file COPYING3. If not see _fixpath ((PATH), fixed_path); \ strcat (fixed_path, "/"); \ (PATH) = xstrdup (fixed_path); \ - } + } + +#undef MAX_OFILE_ALIGNMENT +#define MAX_OFILE_ALIGNMENT 128 + +/* DJGPP versions up to current (2.05) have ftw.h but only ftw() not nftw(). + Disable use of ftw.h */ +#undef HAVE_FTW_H diff --git a/gcc/config/i386/xm-mingw32.h b/gcc/config/i386/xm-mingw32.h index 501cebdb963..5561e00343e 100644 --- a/gcc/config/i386/xm-mingw32.h +++ b/gcc/config/i386/xm-mingw32.h @@ -1,6 +1,6 @@ /* Configuration for GCC for hosting on Windows32. using GNU tools and the Windows32 API Library. - Copyright (C) 1997-2015 Free Software Foundation, Inc. + Copyright (C) 1997-2016 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/i386/xmmintrin.h b/gcc/config/i386/xmmintrin.h index 9cd3fa7d079..ffe5771b1c5 100644 --- a/gcc/config/i386/xmmintrin.h +++ b/gcc/config/i386/xmmintrin.h @@ -1,4 +1,4 @@ -/* Copyright (C) 2002-2015 Free Software Foundation, Inc. +/* Copyright (C) 2002-2016 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/i386/xopintrin.h b/gcc/config/i386/xopintrin.h index 6573767e7b1..609cba04a6f 100644 --- a/gcc/config/i386/xopintrin.h +++ b/gcc/config/i386/xopintrin.h @@ -1,4 +1,4 @@ -/* Copyright (C) 2007-2015 Free Software Foundation, Inc. +/* Copyright (C) 2007-2016 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/i386/xsavecintrin.h b/gcc/config/i386/xsavecintrin.h index f32dbe9e823..4757415bc3c 100644 --- a/gcc/config/i386/xsavecintrin.h +++ b/gcc/config/i386/xsavecintrin.h @@ -1,4 +1,4 @@ -/* Copyright (C) 2014-2015 Free Software Foundation, Inc. +/* Copyright (C) 2014-2016 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/i386/xsaveintrin.h b/gcc/config/i386/xsaveintrin.h index 614fcf6ef5b..53616b72281 100644 --- a/gcc/config/i386/xsaveintrin.h +++ b/gcc/config/i386/xsaveintrin.h @@ -1,4 +1,4 @@ -/* Copyright (C) 2012-2015 Free Software Foundation, Inc. +/* Copyright (C) 2012-2016 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/i386/xsaveoptintrin.h b/gcc/config/i386/xsaveoptintrin.h index 7f71c014505..2569824bb81 100644 --- a/gcc/config/i386/xsaveoptintrin.h +++ b/gcc/config/i386/xsaveoptintrin.h @@ -1,4 +1,4 @@ -/* Copyright (C) 2012-2015 Free Software Foundation, Inc. +/* Copyright (C) 2012-2016 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/i386/xsavesintrin.h b/gcc/config/i386/xsavesintrin.h index 48efc4c59e7..cc29e47dfec 100644 --- a/gcc/config/i386/xsavesintrin.h +++ b/gcc/config/i386/xsavesintrin.h @@ -1,4 +1,4 @@ -/* Copyright (C) 2014-2015 Free Software Foundation, Inc. +/* Copyright (C) 2014-2016 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/i386/xtestintrin.h b/gcc/config/i386/xtestintrin.h index 026e60b6aae..b5a84d49158 100644 --- a/gcc/config/i386/xtestintrin.h +++ b/gcc/config/i386/xtestintrin.h @@ -1,4 +1,4 @@ -/* Copyright (C) 2012-2015 Free Software Foundation, Inc. +/* Copyright (C) 2012-2016 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/i386/znver1.md b/gcc/config/i386/znver1.md index d8c429c08c8..b7fcf6c7a1e 100644 --- a/gcc/config/i386/znver1.md +++ b/gcc/config/i386/znver1.md @@ -1,4 +1,4 @@ -;; Copyright (C) 2012-2015 Free Software Foundation, Inc. +;; Copyright (C) 2012-2016 Free Software Foundation, Inc. ;; ;; This file is part of GCC. ;; |