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-rw-r--r--gcc/config/i386/sse.md126
1 files changed, 80 insertions, 46 deletions
diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md
index 4dfb2f8d3b3..32d241a27b1 100644
--- a/gcc/config/i386/sse.md
+++ b/gcc/config/i386/sse.md
@@ -158,6 +158,8 @@
;; For GFNI support
UNSPEC_GF2P8AFFINEINV
+ UNSPEC_GF2P8AFFINE
+ UNSPEC_GF2P8MUL
])
(define_c_enum "unspecv" [
@@ -1602,7 +1604,8 @@
(plusminus:VF
(match_operand:VF 1 "<round_nimm_predicate>" "<comm>0,v")
(match_operand:VF 2 "<round_nimm_predicate>" "xBm,<round_constraint>")))]
- "TARGET_SSE && ix86_binary_operator_ok (<CODE>, <MODE>mode, operands) && <mask_mode512bit_condition> && <round_mode512bit_condition>"
+ "TARGET_SSE && ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)
+ && <mask_mode512bit_condition> && <round_mode512bit_condition>"
"@
<plusminus_mnemonic><ssemodesuffix>\t{%2, %0|%0, %2}
v<plusminus_mnemonic><ssemodesuffix>\t{<round_mask_op3>%2, %1, %0<mask_operand3>|%0<mask_operand3>, %1, %2<round_mask_op3>}"
@@ -1641,7 +1644,9 @@
(mult:VF
(match_operand:VF 1 "<round_nimm_predicate>" "%0,v")
(match_operand:VF 2 "<round_nimm_predicate>" "xBm,<round_constraint>")))]
- "TARGET_SSE && ix86_binary_operator_ok (MULT, <MODE>mode, operands) && <mask_mode512bit_condition> && <round_mode512bit_condition>"
+ "TARGET_SSE
+ && !(MEM_P (operands[1]) && MEM_P (operands[2]))
+ && <mask_mode512bit_condition> && <round_mode512bit_condition>"
"@
mul<ssemodesuffix>\t{%2, %0|%0, %2}
vmul<ssemodesuffix>\t{<round_mask_op3>%2, %1, %0<mask_operand3>|%0<mask_operand3>, %1, %2<round_mask_op3>}"
@@ -1953,7 +1958,8 @@
(smaxmin:VF
(match_operand:VF 1 "<round_saeonly_nimm_predicate>" "%0,v")
(match_operand:VF 2 "<round_saeonly_nimm_predicate>" "xBm,<round_saeonly_constraint>")))]
- "TARGET_SSE && ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)
+ "TARGET_SSE
+ && !(MEM_P (operands[1]) && MEM_P (operands[2]))
&& <mask_mode512bit_condition> && <round_saeonly_mode512bit_condition>"
"@
<maxmin_float><ssemodesuffix>\t{%2, %0|%0, %2}
@@ -3197,7 +3203,7 @@
(match_operand:VF_128_256 1 "vector_operand" "%0,x,v,v")
(match_operand:VF_128_256 2 "vector_operand" "xBm,xm,vm,vm")))]
"TARGET_SSE && <mask_avx512vl_condition>
- && ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)"
+ && !(MEM_P (operands[1]) && MEM_P (operands[2]))"
{
static char buf[128];
const char *ops;
@@ -3261,7 +3267,7 @@
(any_logic:VF_512
(match_operand:VF_512 1 "nonimmediate_operand" "%v")
(match_operand:VF_512 2 "nonimmediate_operand" "vm")))]
- "TARGET_AVX512F && ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)"
+ "TARGET_AVX512F && !(MEM_P (operands[1]) && MEM_P (operands[2]))"
{
static char buf[128];
const char *ops;
@@ -3515,8 +3521,7 @@
(any_logic:TF
(match_operand:TF 1 "vector_operand" "%0,x,v,v")
(match_operand:TF 2 "vector_operand" "xBm,xm,vm,v")))]
- "TARGET_SSE
- && ix86_binary_operator_ok (<CODE>, TFmode, operands)"
+ "TARGET_SSE && !(MEM_P (operands[1]) && MEM_P (operands[2]))"
{
static char buf[128];
const char *ops;
@@ -9988,8 +9993,7 @@
(plusminus:VI_AVX2
(match_operand:VI_AVX2 1 "vector_operand" "<comm>0,v")
(match_operand:VI_AVX2 2 "vector_operand" "xBm,vm")))]
- "TARGET_SSE2
- && ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)"
+ "TARGET_SSE2 && ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)"
"@
p<plusminus_mnemonic><ssemodesuffix>\t{%2, %0|%0, %2}
vp<plusminus_mnemonic><ssemodesuffix>\t{%2, %1, %0<mask_operand3>|%0<mask_operand3>, %1, %2}"
@@ -10007,8 +10011,7 @@
(match_operand:VI48_AVX512VL 2 "nonimmediate_operand" "vm"))
(match_operand:VI48_AVX512VL 3 "vector_move_operand" "0C")
(match_operand:<avx512fmaskmode> 4 "register_operand" "Yk")))]
- "TARGET_AVX512F
- && ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)"
+ "TARGET_AVX512F && ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)"
"vp<plusminus_mnemonic><ssemodesuffix>\t{%2, %1, %0%{%4%}%N3|%0%{%4%}%N3, %1, %2}"
[(set_attr "type" "sseiadd")
(set_attr "prefix" "evex")
@@ -10073,8 +10076,7 @@
[(set (match_operand:VI2_AVX2 0 "register_operand" "=x,v")
(mult:VI2_AVX2 (match_operand:VI2_AVX2 1 "vector_operand" "%0,v")
(match_operand:VI2_AVX2 2 "vector_operand" "xBm,vm")))]
- "TARGET_SSE2
- && ix86_binary_operator_ok (MULT, <MODE>mode, operands)
+ "TARGET_SSE2 && !(MEM_P (operands[1]) && MEM_P (operands[2]))
&& <mask_mode512bit_condition> && <mask_avx512bw_condition>"
"@
pmullw\t{%2, %0|%0, %2}
@@ -10109,8 +10111,7 @@
(any_extend:<ssedoublemode>
(match_operand:VI2_AVX2 2 "vector_operand" "xBm,vm")))
(const_int 16))))]
- "TARGET_SSE2
- && ix86_binary_operator_ok (MULT, <MODE>mode, operands)
+ "TARGET_SSE2 && !(MEM_P (operands[1]) && MEM_P (operands[2]))
&& <mask_mode512bit_condition> && <mask_avx512bw_condition>"
"@
pmulh<u>w\t{%2, %0|%0, %2}
@@ -10158,7 +10159,7 @@
(const_int 4) (const_int 6)
(const_int 8) (const_int 10)
(const_int 12) (const_int 14)])))))]
- "TARGET_AVX512F && ix86_binary_operator_ok (MULT, V16SImode, operands)"
+ "TARGET_AVX512F && !(MEM_P (operands[1]) && MEM_P (operands[2]))"
"vpmuludq\t{%2, %1, %0<mask_operand3>|%0<mask_operand3>, %1, %2}"
[(set_attr "type" "sseimul")
(set_attr "prefix_extra" "1")
@@ -10195,7 +10196,7 @@
(parallel [(const_int 0) (const_int 2)
(const_int 4) (const_int 6)])))))]
"TARGET_AVX2 && <mask_avx512vl_condition>
- && ix86_binary_operator_ok (MULT, V8SImode, operands)"
+ && !(MEM_P (operands[1]) && MEM_P (operands[2]))"
"vpmuludq\t{%2, %1, %0<mask_operand3>|%0<mask_operand3>, %1, %2}"
[(set_attr "type" "sseimul")
(set_attr "prefix" "maybe_evex")
@@ -10227,7 +10228,7 @@
(match_operand:V4SI 2 "vector_operand" "xBm,vm")
(parallel [(const_int 0) (const_int 2)])))))]
"TARGET_SSE2 && <mask_avx512vl_condition>
- && ix86_binary_operator_ok (MULT, V4SImode, operands)"
+ && !(MEM_P (operands[1]) && MEM_P (operands[2]))"
"@
pmuludq\t{%2, %0|%0, %2}
vpmuludq\t{%2, %1, %0<mask_operand3>|%0<mask_operand3>, %1, %2}"
@@ -10274,7 +10275,7 @@
(const_int 4) (const_int 6)
(const_int 8) (const_int 10)
(const_int 12) (const_int 14)])))))]
- "TARGET_AVX512F && ix86_binary_operator_ok (MULT, V16SImode, operands)"
+ "TARGET_AVX512F && !(MEM_P (operands[1]) && MEM_P (operands[2]))"
"vpmuldq\t{%2, %1, %0<mask_operand3>|%0<mask_operand3>, %1, %2}"
[(set_attr "type" "sseimul")
(set_attr "prefix_extra" "1")
@@ -10310,8 +10311,7 @@
(match_operand:V8SI 2 "nonimmediate_operand" "vm")
(parallel [(const_int 0) (const_int 2)
(const_int 4) (const_int 6)])))))]
- "TARGET_AVX2
- && ix86_binary_operator_ok (MULT, V8SImode, operands)"
+ "TARGET_AVX2 && !(MEM_P (operands[1]) && MEM_P (operands[2]))"
"vpmuldq\t{%2, %1, %0<mask_operand3>|%0<mask_operand3>, %1, %2}"
[(set_attr "type" "sseimul")
(set_attr "prefix_extra" "1")
@@ -10344,7 +10344,7 @@
(match_operand:V4SI 2 "vector_operand" "YrBm,*xBm,vm")
(parallel [(const_int 0) (const_int 2)])))))]
"TARGET_SSE4_1 && <mask_avx512vl_condition>
- && ix86_binary_operator_ok (MULT, V4SImode, operands)"
+ && !(MEM_P (operands[1]) && MEM_P (operands[2]))"
"@
pmuldq\t{%2, %0|%0, %2}
pmuldq\t{%2, %0|%0, %2}
@@ -10433,7 +10433,7 @@
(const_int 5) (const_int 7)
(const_int 9) (const_int 11)
(const_int 13) (const_int 15)]))))))]
- "TARGET_AVX2 && ix86_binary_operator_ok (MULT, V16HImode, operands)"
+ "TARGET_AVX2 && !(MEM_P (operands[1]) && MEM_P (operands[2]))"
"vpmaddwd\t{%2, %1, %0|%0, %1, %2}"
[(set_attr "type" "sseiadd")
(set_attr "isa" "*,avx512bw")
@@ -10489,7 +10489,7 @@
(vec_select:V4HI (match_dup 2)
(parallel [(const_int 1) (const_int 3)
(const_int 5) (const_int 7)]))))))]
- "TARGET_SSE2 && ix86_binary_operator_ok (MULT, V8HImode, operands)"
+ "TARGET_SSE2 && !(MEM_P (operands[1]) && MEM_P (operands[2]))"
"@
pmaddwd\t{%2, %0|%0, %2}
vpmaddwd\t{%2, %1, %0|%0, %1, %2}
@@ -10539,7 +10539,8 @@
(mult:VI4_AVX512F
(match_operand:VI4_AVX512F 1 "vector_operand" "%0,0,v")
(match_operand:VI4_AVX512F 2 "vector_operand" "YrBm,*xBm,vm")))]
- "TARGET_SSE4_1 && ix86_binary_operator_ok (MULT, <MODE>mode, operands) && <mask_mode512bit_condition>"
+ "TARGET_SSE4_1 && !(MEM_P (operands[1]) && MEM_P (operands[2]))
+ && <mask_mode512bit_condition>"
"@
pmulld\t{%2, %0|%0, %2}
pmulld\t{%2, %0|%0, %2}
@@ -10857,7 +10858,7 @@
(maxmin:VI124_256
(match_operand:VI124_256 1 "nonimmediate_operand" "%v")
(match_operand:VI124_256 2 "nonimmediate_operand" "vm")))]
- "TARGET_AVX2 && ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)"
+ "TARGET_AVX2 && !(MEM_P (operands[1]) && MEM_P (operands[2]))"
"vp<maxmin_int><ssemodesuffix>\t{%2, %1, %0|%0, %1, %2}"
[(set_attr "type" "sseiadd")
(set_attr "prefix_extra" "1")
@@ -10880,7 +10881,7 @@
(maxmin:VI48_AVX512VL
(match_operand:VI48_AVX512VL 1 "nonimmediate_operand" "%v")
(match_operand:VI48_AVX512VL 2 "nonimmediate_operand" "vm")))]
- "TARGET_AVX512F && ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)"
+ "TARGET_AVX512F && !(MEM_P (operands[1]) && MEM_P (operands[2]))"
"vp<maxmin_int><ssemodesuffix>\t{%2, %1, %0<mask_operand3>|%0<mask_operand3>, %1, %2}"
[(set_attr "type" "sseiadd")
(set_attr "prefix_extra" "1")
@@ -10986,7 +10987,7 @@
(match_operand:VI14_128 2 "vector_operand" "YrBm,*xBm,vm")))]
"TARGET_SSE4_1
&& <mask_mode512bit_condition>
- && ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)"
+ && !(MEM_P (operands[1]) && MEM_P (operands[2]))"
"@
p<maxmin_int><ssemodesuffix>\t{%2, %0|%0, %2}
p<maxmin_int><ssemodesuffix>\t{%2, %0|%0, %2}
@@ -11002,7 +11003,7 @@
(smaxmin:V8HI
(match_operand:V8HI 1 "vector_operand" "%0,x,v")
(match_operand:V8HI 2 "vector_operand" "xBm,xm,vm")))]
- "TARGET_SSE2 && ix86_binary_operator_ok (<CODE>, V8HImode, operands)"
+ "TARGET_SSE2 && !(MEM_P (operands[1]) && MEM_P (operands[2]))"
"@
p<maxmin_int>w\t{%2, %0|%0, %2}
vp<maxmin_int>w\t{%2, %1, %0|%0, %1, %2}
@@ -11071,7 +11072,7 @@
(match_operand:VI24_128 2 "vector_operand" "YrBm,*xBm,vm")))]
"TARGET_SSE4_1
&& <mask_mode512bit_condition>
- && ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)"
+ && !(MEM_P (operands[1]) && MEM_P (operands[2]))"
"@
p<maxmin_int><ssemodesuffix>\t{%2, %0|%0, %2}
p<maxmin_int><ssemodesuffix>\t{%2, %0|%0, %2}
@@ -11087,7 +11088,7 @@
(umaxmin:V16QI
(match_operand:V16QI 1 "vector_operand" "%0,x,v")
(match_operand:V16QI 2 "vector_operand" "xBm,xm,vm")))]
- "TARGET_SSE2 && ix86_binary_operator_ok (<CODE>, V16QImode, operands)"
+ "TARGET_SSE2 && !(MEM_P (operands[1]) && MEM_P (operands[2]))"
"@
p<maxmin_int>b\t{%2, %0|%0, %2}
vp<maxmin_int>b\t{%2, %1, %0|%0, %1, %2}
@@ -11118,7 +11119,7 @@
(eq:VI_256
(match_operand:VI_256 1 "nonimmediate_operand" "%x")
(match_operand:VI_256 2 "nonimmediate_operand" "xm")))]
- "TARGET_AVX2 && ix86_binary_operator_ok (EQ, <MODE>mode, operands)"
+ "TARGET_AVX2 && !(MEM_P (operands[1]) && MEM_P (operands[2]))"
"vpcmpeq<ssemodesuffix>\t{%2, %1, %0|%0, %1, %2}"
[(set_attr "type" "ssecmp")
(set_attr "prefix_extra" "1")
@@ -11128,7 +11129,7 @@
(define_expand "<avx512>_eq<mode>3<mask_scalar_merge_name>"
[(set (match_operand:<avx512fmaskmode> 0 "register_operand")
(unspec:<avx512fmaskmode>
- [(match_operand:VI12_AVX512VL 1 "register_operand")
+ [(match_operand:VI12_AVX512VL 1 "nonimmediate_operand")
(match_operand:VI12_AVX512VL 2 "nonimmediate_operand")]
UNSPEC_MASKED_EQ))]
"TARGET_AVX512BW"
@@ -11137,7 +11138,7 @@
(define_expand "<avx512>_eq<mode>3<mask_scalar_merge_name>"
[(set (match_operand:<avx512fmaskmode> 0 "register_operand")
(unspec:<avx512fmaskmode>
- [(match_operand:VI48_AVX512VL 1 "register_operand")
+ [(match_operand:VI48_AVX512VL 1 "nonimmediate_operand")
(match_operand:VI48_AVX512VL 2 "nonimmediate_operand")]
UNSPEC_MASKED_EQ))]
"TARGET_AVX512F"
@@ -11146,10 +11147,10 @@
(define_insn "<avx512>_eq<mode>3<mask_scalar_merge_name>_1"
[(set (match_operand:<avx512fmaskmode> 0 "register_operand" "=Yk")
(unspec:<avx512fmaskmode>
- [(match_operand:VI12_AVX512VL 1 "register_operand" "%v")
+ [(match_operand:VI12_AVX512VL 1 "nonimmediate_operand" "%v")
(match_operand:VI12_AVX512VL 2 "nonimmediate_operand" "vm")]
UNSPEC_MASKED_EQ))]
- "TARGET_AVX512F && ix86_binary_operator_ok (EQ, <MODE>mode, operands)"
+ "TARGET_AVX512F && !(MEM_P (operands[1]) && MEM_P (operands[2]))"
"vpcmpeq<ssemodesuffix>\t{%2, %1, %0<mask_scalar_merge_operand3>|%0<mask_scalar_merge_operand3>, %1, %2}"
[(set_attr "type" "ssecmp")
(set_attr "prefix_extra" "1")
@@ -11159,10 +11160,10 @@
(define_insn "<avx512>_eq<mode>3<mask_scalar_merge_name>_1"
[(set (match_operand:<avx512fmaskmode> 0 "register_operand" "=Yk")
(unspec:<avx512fmaskmode>
- [(match_operand:VI48_AVX512VL 1 "register_operand" "%v")
+ [(match_operand:VI48_AVX512VL 1 "nonimmediate_operand" "%v")
(match_operand:VI48_AVX512VL 2 "nonimmediate_operand" "vm")]
UNSPEC_MASKED_EQ))]
- "TARGET_AVX512F && ix86_binary_operator_ok (EQ, <MODE>mode, operands)"
+ "TARGET_AVX512F && !(MEM_P (operands[1]) && MEM_P (operands[2]))"
"vpcmpeq<ssemodesuffix>\t{%2, %1, %0<mask_scalar_merge_operand3>|%0<mask_scalar_merge_operand3>, %1, %2}"
[(set_attr "type" "ssecmp")
(set_attr "prefix_extra" "1")
@@ -11174,7 +11175,7 @@
(eq:V2DI
(match_operand:V2DI 1 "vector_operand" "%0,0,x")
(match_operand:V2DI 2 "vector_operand" "YrBm,*xBm,xm")))]
- "TARGET_SSE4_1 && ix86_binary_operator_ok (EQ, V2DImode, operands)"
+ "TARGET_SSE4_1 && !(MEM_P (operands[1]) && MEM_P (operands[2]))"
"@
pcmpeqq\t{%2, %0|%0, %2}
pcmpeqq\t{%2, %0|%0, %2}
@@ -11191,7 +11192,7 @@
(match_operand:VI124_128 1 "vector_operand" "%0,x")
(match_operand:VI124_128 2 "vector_operand" "xBm,xm")))]
"TARGET_SSE2 && !TARGET_XOP
- && ix86_binary_operator_ok (EQ, <MODE>mode, operands)"
+ && !(MEM_P (operands[1]) && MEM_P (operands[2]))"
"@
pcmpeq<ssemodesuffix>\t{%2, %0|%0, %2}
vpcmpeq<ssemodesuffix>\t{%2, %1, %0|%0, %1, %2}"
@@ -11656,7 +11657,7 @@
(match_operand:VI48_AVX_AVX512F 1 "vector_operand" "%0,x,v")
(match_operand:VI48_AVX_AVX512F 2 "vector_operand" "xBm,xm,vm")))]
"TARGET_SSE && <mask_mode512bit_condition>
- && ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)"
+ && !(MEM_P (operands[1]) && MEM_P (operands[2]))"
{
static char buf[64];
const char *ops;
@@ -11753,10 +11754,10 @@
(define_insn "*<code><mode>3"
[(set (match_operand:VI12_AVX_AVX512F 0 "register_operand" "=x,x,v")
- (any_logic: VI12_AVX_AVX512F
+ (any_logic:VI12_AVX_AVX512F
(match_operand:VI12_AVX_AVX512F 1 "vector_operand" "%0,x,v")
(match_operand:VI12_AVX_AVX512F 2 "vector_operand" "xBm,xm,vm")))]
- "TARGET_SSE && ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)"
+ "TARGET_SSE && !(MEM_P (operands[1]) && MEM_P (operands[2]))"
{
static char buf[64];
const char *ops;
@@ -14067,7 +14068,7 @@
(match_operand:VI12_AVX2 <mask_expand_op3> "const1_operand"))
(const_int 1))))]
"TARGET_SSE2 && <mask_mode512bit_condition> && <mask_avx512bw_condition>
- && ix86_binary_operator_ok (PLUS, <MODE>mode, operands)"
+ && !(MEM_P (operands[1]) && MEM_P (operands[2]))"
"@
pavg<ssemodesuffix>\t{%2, %0|%0, %2}
vpavg<ssemodesuffix>\t{%2, %1, %0<mask_operand3>|%0<mask_operand3>, %1, %2}"
@@ -14741,7 +14742,7 @@
(match_operand:VI2_AVX2 3 "const1_operand"))
(const_int 1))))]
"TARGET_SSSE3 && <mask_mode512bit_condition> && <mask_avx512bw_condition>
- && ix86_binary_operator_ok (MULT, <MODE>mode, operands)"
+ && !(MEM_P (operands[1]) && MEM_P (operands[2]))"
"@
pmulhrsw\t{%2, %0|%0, %2}
vpmulhrsw\t{%2, %1, %0<mask_operand4>|%0<mask_operand4>, %1, %2}
@@ -14767,7 +14768,7 @@
(const_int 14))
(match_operand:V4HI 3 "const1_operand"))
(const_int 1))))]
- "TARGET_SSSE3 && ix86_binary_operator_ok (MULT, V4HImode, operands)"
+ "TARGET_SSSE3 && !(MEM_P (operands[1]) && MEM_P (operands[2]))"
"pmulhrsw\t{%2, %0|%0, %2}"
[(set_attr "type" "sseimul")
(set_attr "prefix_extra" "1")
@@ -19991,3 +19992,36 @@
(set_attr "prefix_extra" "1")
(set_attr "prefix" "orig,maybe_evex,evex")
(set_attr "mode" "<sseinsnmode>")])
+
+(define_insn "vgf2p8affineqb_<mode><mask_name>"
+ [(set (match_operand:VI1_AVX512F 0 "register_operand" "=x,x,v")
+ (unspec:VI1_AVX512F [(match_operand:VI1_AVX512F 1 "register_operand" "%0,x,v")
+ (match_operand:VI1_AVX512F 2 "nonimmediate_operand" "xBm,xm,vm")
+ (match_operand:QI 3 "const_0_to_255_operand" "n,n,n")]
+ UNSPEC_GF2P8AFFINE))]
+ "TARGET_GFNI"
+ "@
+ gf2p8affineqb\t{%3, %2, %0| %0, %2, %3}
+ vgf2p8affineqb\t{%3, %2, %1, %0<mask_operand4>| %0<mask_operand4>, %1, %2, %3}
+ vgf2p8affineqb\t{%3, %2, %1, %0<mask_operand4>| %0<mask_operand4>, %1, %2, %3}"
+ [(set_attr "isa" "noavx,avx,avx512bw")
+ (set_attr "prefix_data16" "1,*,*")
+ (set_attr "prefix_extra" "1")
+ (set_attr "prefix" "orig,maybe_evex,evex")
+ (set_attr "mode" "<sseinsnmode>")])
+
+(define_insn "vgf2p8mulb_<mode><mask_name>"
+ [(set (match_operand:VI1_AVX512F 0 "register_operand" "=x,x,v")
+ (unspec:VI1_AVX512F [(match_operand:VI1_AVX512F 1 "register_operand" "%0,x,v")
+ (match_operand:VI1_AVX512F 2 "nonimmediate_operand" "xBm,xm,vm")]
+ UNSPEC_GF2P8MUL))]
+ "TARGET_GFNI"
+ "@
+ gf2p8mulb\t{%2, %0| %0, %2}
+ vgf2p8mulb\t{%2, %1, %0<mask_operand3>| %0<mask_operand3>, %1, %2}
+ vgf2p8mulb\t{%2, %1, %0<mask_operand3>| %0<mask_operand3>, %1, %2}"
+ [(set_attr "isa" "noavx,avx,avx512bw")
+ (set_attr "prefix_data16" "1,*,*")
+ (set_attr "prefix_extra" "1")
+ (set_attr "prefix" "orig,maybe_evex,evex")
+ (set_attr "mode" "<sseinsnmode>")])
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