diff options
Diffstat (limited to 'gcc/config/arm')
| -rw-r--r-- | gcc/config/arm/arm-cpus.in | 20 | ||||
| -rw-r--r-- | gcc/config/arm/arm-fixed.md | 8 | ||||
| -rw-r--r-- | gcc/config/arm/arm-protos.h | 2 | ||||
| -rw-r--r-- | gcc/config/arm/arm-tables.opt | 13 | ||||
| -rw-r--r-- | gcc/config/arm/arm.c | 303 | ||||
| -rw-r--r-- | gcc/config/arm/arm.h | 5 | ||||
| -rw-r--r-- | gcc/config/arm/arm.md | 159 | ||||
| -rw-r--r-- | gcc/config/arm/ldmstm.md | 72 | ||||
| -rw-r--r-- | gcc/config/arm/sync.md | 36 | ||||
| -rw-r--r-- | gcc/config/arm/thumb2.md | 26 | ||||
| -rw-r--r-- | gcc/config/arm/vfp.md | 56 | ||||
| -rw-r--r-- | gcc/config/arm/xgene1.md | 124 |
12 files changed, 375 insertions, 449 deletions
diff --git a/gcc/config/arm/arm-cpus.in b/gcc/config/arm/arm-cpus.in index 0820ad74c2e..281ec162db8 100644 --- a/gcc/config/arm/arm-cpus.in +++ b/gcc/config/arm/arm-cpus.in @@ -114,9 +114,12 @@ define feature iwmmxt2 # Architecture rel 8.1. define feature armv8_1 -# Architecutre rel 8.2. +# Architecture rel 8.2. define feature armv8_2 +# Architecture rel 8.3. +define feature armv8_3 + # M-Profile security extensions. define feature cmse @@ -238,6 +241,7 @@ define fgroup ARMv7em ARMv7m armv7em define fgroup ARMv8a ARMv7ve armv8 define fgroup ARMv8_1a ARMv8a crc32 armv8_1 define fgroup ARMv8_2a ARMv8_1a armv8_2 +define fgroup ARMv8_3a ARMv8_2a armv8_3 define fgroup ARMv8m_base ARMv6m armv8 cmse tdiv define fgroup ARMv8m_main ARMv7m armv8 cmse define fgroup ARMv8r ARMv8a @@ -579,6 +583,20 @@ begin arch armv8.2-a option dotprod add FP_ARMv8 DOTPROD end arch armv8.2-a +begin arch armv8.3-a + tune for cortex-a53 + tune flags CO_PROC + base 8A + profile A + isa ARMv8_3a + option simd add FP_ARMv8 NEON + option fp16 add fp16 FP_ARMv8 NEON + option crypto add FP_ARMv8 CRYPTO + option nocrypto remove ALL_CRYPTO + option nofp remove ALL_FP + option dotprod add FP_ARMv8 DOTPROD +end arch armv8.3-a + begin arch armv8-m.base tune for cortex-m23 base 8M_BASE diff --git a/gcc/config/arm/arm-fixed.md b/gcc/config/arm/arm-fixed.md index ca721437792..6730a2bbad6 100644 --- a/gcc/config/arm/arm-fixed.md +++ b/gcc/config/arm/arm-fixed.md @@ -35,7 +35,6 @@ "TARGET_INT_SIMD" "sadd<qaddsub_suf>%?\\t%0, %1, %2" [(set_attr "predicable" "yes") - (set_attr "predicable_short_it" "no") (set_attr "type" "alu_dsp_reg")]) (define_insn "usadd<mode>3" @@ -45,7 +44,6 @@ "TARGET_INT_SIMD" "uqadd<qaddsub_suf>%?\\t%0, %1, %2" [(set_attr "predicable" "yes") - (set_attr "predicable_short_it" "no") (set_attr "type" "alu_dsp_reg")]) (define_insn "ssadd<mode>3" @@ -55,7 +53,6 @@ "TARGET_INT_SIMD" "qadd<qaddsub_suf>%?\\t%0, %1, %2" [(set_attr "predicable" "yes") - (set_attr "predicable_short_it" "no") (set_attr "type" "alu_dsp_reg")]) (define_insn "sub<mode>3" @@ -75,7 +72,6 @@ "TARGET_INT_SIMD" "ssub<qaddsub_suf>%?\\t%0, %1, %2" [(set_attr "predicable" "yes") - (set_attr "predicable_short_it" "no") (set_attr "type" "alu_dsp_reg")]) (define_insn "ussub<mode>3" @@ -86,7 +82,6 @@ "TARGET_INT_SIMD" "uqsub<qaddsub_suf>%?\\t%0, %1, %2" [(set_attr "predicable" "yes") - (set_attr "predicable_short_it" "no") (set_attr "type" "alu_dsp_reg")]) (define_insn "sssub<mode>3" @@ -96,7 +91,6 @@ "TARGET_INT_SIMD" "qsub<qaddsub_suf>%?\\t%0, %1, %2" [(set_attr "predicable" "yes") - (set_attr "predicable_short_it" "no") (set_attr "type" "alu_dsp_reg")]) ;; Fractional multiplies. @@ -414,7 +408,6 @@ "TARGET_32BIT && arm_arch6" "ssat%?\\t%0, #16, %2%S1" [(set_attr "predicable" "yes") - (set_attr "predicable_short_it" "no") (set_attr "shift" "1") (set_attr "type" "alu_shift_imm")]) @@ -424,6 +417,5 @@ "TARGET_INT_SIMD" "usat%?\\t%0, #16, %1" [(set_attr "predicable" "yes") - (set_attr "predicable_short_it" "no") (set_attr "type" "alu_imm")] ) diff --git a/gcc/config/arm/arm-protos.h b/gcc/config/arm/arm-protos.h index 4538078fe60..10c96390ea6 100644 --- a/gcc/config/arm/arm-protos.h +++ b/gcc/config/arm/arm-protos.h @@ -224,6 +224,8 @@ extern tree arm_valid_target_attribute_tree (tree, struct gcc_options *, extern void arm_configure_build_target (struct arm_build_target *, struct cl_target_option *, struct gcc_options *, bool); +extern void arm_option_reconfigure_globals (void); +extern void arm_options_perform_arch_sanity_checks (void); extern void arm_pr_long_calls (struct cpp_reader *); extern void arm_pr_no_long_calls (struct cpp_reader *); extern void arm_pr_long_calls_off (struct cpp_reader *); diff --git a/gcc/config/arm/arm-tables.opt b/gcc/config/arm/arm-tables.opt index 4e508b1555a..f7937256cd7 100644 --- a/gcc/config/arm/arm-tables.opt +++ b/gcc/config/arm/arm-tables.opt @@ -452,19 +452,22 @@ EnumValue Enum(arm_arch) String(armv8.2-a) Value(28) EnumValue -Enum(arm_arch) String(armv8-m.base) Value(29) +Enum(arm_arch) String(armv8.3-a) Value(29) EnumValue -Enum(arm_arch) String(armv8-m.main) Value(30) +Enum(arm_arch) String(armv8-m.base) Value(30) EnumValue -Enum(arm_arch) String(armv8-r) Value(31) +Enum(arm_arch) String(armv8-m.main) Value(31) EnumValue -Enum(arm_arch) String(iwmmxt) Value(32) +Enum(arm_arch) String(armv8-r) Value(32) EnumValue -Enum(arm_arch) String(iwmmxt2) Value(33) +Enum(arm_arch) String(iwmmxt) Value(33) + +EnumValue +Enum(arm_arch) String(iwmmxt2) Value(34) Enum Name(arm_fpu) Type(enum fpu_type) diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c index 47ba0dd09e3..67ec3bd9056 100644 --- a/gcc/config/arm/arm.c +++ b/gcc/config/arm/arm.c @@ -3337,8 +3337,9 @@ arm_option_override (void) SUBTARGET_OVERRIDE_OPTIONS; #endif - sprintf (arm_arch_name, "__ARM_ARCH_%s__", arm_active_target.arch_pp_name); - arm_base_arch = arm_active_target.base_arch; + /* Initialize boolean versions of the architectural flags, for use + in the arm.md file and for enabling feature flags. */ + arm_option_reconfigure_globals (); arm_tune = arm_active_target.tune_core; tune_flags = arm_active_target.tune_flags; @@ -3348,16 +3349,6 @@ arm_option_override (void) if (TARGET_APCS_FRAME) flag_shrink_wrap = false; - /* BPABI targets use linker tricks to allow interworking on cores - without thumb support. */ - if (TARGET_INTERWORK - && !TARGET_BPABI - && !bitmap_bit_p (arm_active_target.isa, isa_bit_thumb)) - { - warning (0, "target CPU does not support interworking" ); - target_flags &= ~MASK_INTERWORK; - } - if (TARGET_APCS_STACK && !TARGET_APCS_FRAME) { warning (0, "-mapcs-stack-check incompatible with -mno-apcs-frame"); @@ -3373,43 +3364,6 @@ arm_option_override (void) if (TARGET_APCS_REENT) warning (0, "APCS reentrant code not supported. Ignored"); - /* Initialize boolean versions of the architectural flags, for use - in the arm.md file. */ - arm_arch3m = bitmap_bit_p (arm_active_target.isa, isa_bit_armv3m); - arm_arch4 = bitmap_bit_p (arm_active_target.isa, isa_bit_armv4); - arm_arch4t = arm_arch4 && bitmap_bit_p (arm_active_target.isa, isa_bit_thumb); - arm_arch5 = bitmap_bit_p (arm_active_target.isa, isa_bit_armv5); - arm_arch5e = bitmap_bit_p (arm_active_target.isa, isa_bit_armv5e); - arm_arch5te = arm_arch5e - && bitmap_bit_p (arm_active_target.isa, isa_bit_thumb); - arm_arch6 = bitmap_bit_p (arm_active_target.isa, isa_bit_armv6); - arm_arch6k = bitmap_bit_p (arm_active_target.isa, isa_bit_armv6k); - arm_arch_notm = bitmap_bit_p (arm_active_target.isa, isa_bit_notm); - arm_arch6m = arm_arch6 && !arm_arch_notm; - arm_arch7 = bitmap_bit_p (arm_active_target.isa, isa_bit_armv7); - arm_arch7em = bitmap_bit_p (arm_active_target.isa, isa_bit_armv7em); - arm_arch8 = bitmap_bit_p (arm_active_target.isa, isa_bit_armv8); - arm_arch8_1 = bitmap_bit_p (arm_active_target.isa, isa_bit_armv8_1); - arm_arch8_2 = bitmap_bit_p (arm_active_target.isa, isa_bit_armv8_2); - arm_arch_thumb1 = bitmap_bit_p (arm_active_target.isa, isa_bit_thumb); - arm_arch_thumb2 = bitmap_bit_p (arm_active_target.isa, isa_bit_thumb2); - arm_arch_xscale = bitmap_bit_p (arm_active_target.isa, isa_bit_xscale); - arm_arch_iwmmxt = bitmap_bit_p (arm_active_target.isa, isa_bit_iwmmxt); - arm_arch_iwmmxt2 = bitmap_bit_p (arm_active_target.isa, isa_bit_iwmmxt2); - arm_arch_thumb_hwdiv = bitmap_bit_p (arm_active_target.isa, isa_bit_tdiv); - arm_arch_arm_hwdiv = bitmap_bit_p (arm_active_target.isa, isa_bit_adiv); - arm_arch_crc = bitmap_bit_p (arm_active_target.isa, isa_bit_crc32); - arm_arch_cmse = bitmap_bit_p (arm_active_target.isa, isa_bit_cmse); - arm_fp16_inst = bitmap_bit_p (arm_active_target.isa, isa_bit_fp16); - arm_arch_lpae = bitmap_bit_p (arm_active_target.isa, isa_bit_lpae); - if (arm_fp16_inst) - { - if (arm_fp16_format == ARM_FP16_FORMAT_ALTERNATIVE) - error ("selected fp16 options are incompatible"); - arm_fp16_format = ARM_FP16_FORMAT_IEEE; - } - - /* Set up some tuning parameters. */ arm_ld_sched = (tune_flags & TF_LDSCHED) != 0; arm_tune_strongarm = (tune_flags & TF_STRONG) != 0; @@ -3418,86 +3372,11 @@ arm_option_override (void) arm_tune_cortex_a9 = (arm_tune == TARGET_CPU_cortexa9) != 0; arm_m_profile_small_mul = (tune_flags & TF_SMALLMUL) != 0; - /* And finally, set up some quirks. */ - arm_arch_no_volatile_ce - = bitmap_bit_p (arm_active_target.isa, isa_bit_quirk_no_volatile_ce); - arm_arch6kz = arm_arch6k && bitmap_bit_p (arm_active_target.isa, - isa_bit_quirk_armv6kz); - - /* V5 code we generate is completely interworking capable, so we turn off - TARGET_INTERWORK here to avoid many tests later on. */ - - /* XXX However, we must pass the right pre-processor defines to CPP - or GLD can get confused. This is a hack. */ - if (TARGET_INTERWORK) - arm_cpp_interwork = 1; - - if (arm_arch5) - target_flags &= ~MASK_INTERWORK; - - if (TARGET_IWMMXT && !ARM_DOUBLEWORD_ALIGN) - error ("iwmmxt requires an AAPCS compatible ABI for proper operation"); - - if (TARGET_IWMMXT_ABI && !TARGET_IWMMXT) - error ("iwmmxt abi requires an iwmmxt capable cpu"); - - /* If soft-float is specified then don't use FPU. */ - if (TARGET_SOFT_FLOAT) - arm_fpu_attr = FPU_NONE; - else - arm_fpu_attr = FPU_VFP; - - if (TARGET_AAPCS_BASED) - { - if (TARGET_CALLER_INTERWORKING) - error ("AAPCS does not support -mcaller-super-interworking"); - else - if (TARGET_CALLEE_INTERWORKING) - error ("AAPCS does not support -mcallee-super-interworking"); - } - - /* __fp16 support currently assumes the core has ldrh. */ - if (!arm_arch4 && arm_fp16_format != ARM_FP16_FORMAT_NONE) - sorry ("__fp16 and no ldrh"); - - if (TARGET_AAPCS_BASED) - { - if (arm_abi == ARM_ABI_IWMMXT) - arm_pcs_default = ARM_PCS_AAPCS_IWMMXT; - else if (TARGET_HARD_FLOAT_ABI) - { - arm_pcs_default = ARM_PCS_AAPCS_VFP; - if (!bitmap_bit_p (arm_active_target.isa, isa_bit_vfpv2)) - error ("-mfloat-abi=hard: selected processor lacks an FPU"); - } - else - arm_pcs_default = ARM_PCS_AAPCS; - } - else - { - if (arm_float_abi == ARM_FLOAT_ABI_HARD) - sorry ("-mfloat-abi=hard and VFP"); - - if (arm_abi == ARM_ABI_APCS) - arm_pcs_default = ARM_PCS_APCS; - else - arm_pcs_default = ARM_PCS_ATPCS; - } - /* For arm2/3 there is no need to do any scheduling if we are doing software floating-point. */ if (TARGET_SOFT_FLOAT && (tune_flags & TF_NO_MODE32)) flag_schedule_insns = flag_schedule_insns_after_reload = 0; - /* Use the cp15 method if it is available. */ - if (target_thread_pointer == TP_AUTO) - { - if (arm_arch6k && !TARGET_THUMB1) - target_thread_pointer = TP_CP15; - else - target_thread_pointer = TP_SOFT; - } - /* Override the default structure alignment for AAPCS ABI. */ if (!global_options_set.x_arm_structure_size_boundary) { @@ -3671,14 +3550,6 @@ arm_option_override (void) if (target_slow_flash_data || target_pure_code) arm_disable_literal_pool = true; - if (use_cmse && !arm_arch_cmse) - error ("target CPU does not support ARMv8-M Security Extensions"); - - /* We don't clear D16-D31 VFP registers for cmse_nonsecure_call functions - and ARMv8-M Baseline and Mainline do not allow such configuration. */ - if (use_cmse && LAST_VFP_REGNUM > LAST_LO_VFP_REGNUM) - error ("ARMv8-M Security Extensions incompatible with selected FPU"); - /* Disable scheduling fusion by default if it's not armv7 processor or doesn't prefer ldrd/strd. */ if (flag_schedule_fusion == 2 @@ -3688,6 +3559,7 @@ arm_option_override (void) /* Need to remember initial options before they are overriden. */ init_optimize = build_optimization_node (&global_options); + arm_options_perform_arch_sanity_checks (); arm_option_override_internal (&global_options, &global_options_set); arm_option_check_internal (&global_options); arm_option_params_internal (); @@ -3703,6 +3575,151 @@ arm_option_override (void) thumb_flipper = TARGET_THUMB; } + +/* Reconfigure global status flags from the active_target.isa. */ +void +arm_option_reconfigure_globals (void) +{ + sprintf (arm_arch_name, "__ARM_ARCH_%s__", arm_active_target.arch_pp_name); + arm_base_arch = arm_active_target.base_arch; + + /* Initialize boolean versions of the architectural flags, for use + in the arm.md file. */ + arm_arch3m = bitmap_bit_p (arm_active_target.isa, isa_bit_armv3m); + arm_arch4 = bitmap_bit_p (arm_active_target.isa, isa_bit_armv4); + arm_arch4t = arm_arch4 && bitmap_bit_p (arm_active_target.isa, isa_bit_thumb); + arm_arch5 = bitmap_bit_p (arm_active_target.isa, isa_bit_armv5); + arm_arch5e = bitmap_bit_p (arm_active_target.isa, isa_bit_armv5e); + arm_arch5te = arm_arch5e + && bitmap_bit_p (arm_active_target.isa, isa_bit_thumb); + arm_arch6 = bitmap_bit_p (arm_active_target.isa, isa_bit_armv6); + arm_arch6k = bitmap_bit_p (arm_active_target.isa, isa_bit_armv6k); + arm_arch_notm = bitmap_bit_p (arm_active_target.isa, isa_bit_notm); + arm_arch6m = arm_arch6 && !arm_arch_notm; + arm_arch7 = bitmap_bit_p (arm_active_target.isa, isa_bit_armv7); + arm_arch7em = bitmap_bit_p (arm_active_target.isa, isa_bit_armv7em); + arm_arch8 = bitmap_bit_p (arm_active_target.isa, isa_bit_armv8); + arm_arch8_1 = bitmap_bit_p (arm_active_target.isa, isa_bit_armv8_1); + arm_arch8_2 = bitmap_bit_p (arm_active_target.isa, isa_bit_armv8_2); + arm_arch_thumb1 = bitmap_bit_p (arm_active_target.isa, isa_bit_thumb); + arm_arch_thumb2 = bitmap_bit_p (arm_active_target.isa, isa_bit_thumb2); + arm_arch_xscale = bitmap_bit_p (arm_active_target.isa, isa_bit_xscale); + arm_arch_iwmmxt = bitmap_bit_p (arm_active_target.isa, isa_bit_iwmmxt); + arm_arch_iwmmxt2 = bitmap_bit_p (arm_active_target.isa, isa_bit_iwmmxt2); + arm_arch_thumb_hwdiv = bitmap_bit_p (arm_active_target.isa, isa_bit_tdiv); + arm_arch_arm_hwdiv = bitmap_bit_p (arm_active_target.isa, isa_bit_adiv); + arm_arch_crc = bitmap_bit_p (arm_active_target.isa, isa_bit_crc32); + arm_arch_cmse = bitmap_bit_p (arm_active_target.isa, isa_bit_cmse); + arm_fp16_inst = bitmap_bit_p (arm_active_target.isa, isa_bit_fp16); + arm_arch_lpae = bitmap_bit_p (arm_active_target.isa, isa_bit_lpae); + if (arm_fp16_inst) + { + if (arm_fp16_format == ARM_FP16_FORMAT_ALTERNATIVE) + error ("selected fp16 options are incompatible"); + arm_fp16_format = ARM_FP16_FORMAT_IEEE; + } + + /* And finally, set up some quirks. */ + arm_arch_no_volatile_ce + = bitmap_bit_p (arm_active_target.isa, isa_bit_quirk_no_volatile_ce); + arm_arch6kz = arm_arch6k && bitmap_bit_p (arm_active_target.isa, + isa_bit_quirk_armv6kz); + + /* Use the cp15 method if it is available. */ + if (target_thread_pointer == TP_AUTO) + { + if (arm_arch6k && !TARGET_THUMB1) + target_thread_pointer = TP_CP15; + else + target_thread_pointer = TP_SOFT; + } +} + +/* Perform some validation between the desired architecture and the rest of the + options. */ +void +arm_options_perform_arch_sanity_checks (void) +{ + /* V5 code we generate is completely interworking capable, so we turn off + TARGET_INTERWORK here to avoid many tests later on. */ + + /* XXX However, we must pass the right pre-processor defines to CPP + or GLD can get confused. This is a hack. */ + if (TARGET_INTERWORK) + arm_cpp_interwork = 1; + + if (arm_arch5) + target_flags &= ~MASK_INTERWORK; + + if (TARGET_IWMMXT && !ARM_DOUBLEWORD_ALIGN) + error ("iwmmxt requires an AAPCS compatible ABI for proper operation"); + + if (TARGET_IWMMXT_ABI && !TARGET_IWMMXT) + error ("iwmmxt abi requires an iwmmxt capable cpu"); + + /* BPABI targets use linker tricks to allow interworking on cores + without thumb support. */ + if (TARGET_INTERWORK + && !TARGET_BPABI + && !bitmap_bit_p (arm_active_target.isa, isa_bit_thumb)) + { + warning (0, "target CPU does not support interworking" ); + target_flags &= ~MASK_INTERWORK; + } + + /* If soft-float is specified then don't use FPU. */ + if (TARGET_SOFT_FLOAT) + arm_fpu_attr = FPU_NONE; + else + arm_fpu_attr = FPU_VFP; + + if (TARGET_AAPCS_BASED) + { + if (TARGET_CALLER_INTERWORKING) + error ("AAPCS does not support -mcaller-super-interworking"); + else + if (TARGET_CALLEE_INTERWORKING) + error ("AAPCS does not support -mcallee-super-interworking"); + } + + /* __fp16 support currently assumes the core has ldrh. */ + if (!arm_arch4 && arm_fp16_format != ARM_FP16_FORMAT_NONE) + sorry ("__fp16 and no ldrh"); + + if (use_cmse && !arm_arch_cmse) + error ("target CPU does not support ARMv8-M Security Extensions"); + + /* We don't clear D16-D31 VFP registers for cmse_nonsecure_call functions + and ARMv8-M Baseline and Mainline do not allow such configuration. */ + if (use_cmse && LAST_VFP_REGNUM > LAST_LO_VFP_REGNUM) + error ("ARMv8-M Security Extensions incompatible with selected FPU"); + + + if (TARGET_AAPCS_BASED) + { + if (arm_abi == ARM_ABI_IWMMXT) + arm_pcs_default = ARM_PCS_AAPCS_IWMMXT; + else if (TARGET_HARD_FLOAT_ABI) + { + arm_pcs_default = ARM_PCS_AAPCS_VFP; + if (!bitmap_bit_p (arm_active_target.isa, isa_bit_vfpv2)) + error ("-mfloat-abi=hard: selected processor lacks an FPU"); + } + else + arm_pcs_default = ARM_PCS_AAPCS; + } + else + { + if (arm_float_abi == ARM_FLOAT_ABI_HARD) + sorry ("-mfloat-abi=hard and VFP"); + + if (arm_abi == ARM_ABI_APCS) + arm_pcs_default = ARM_PCS_APCS; + else + arm_pcs_default = ARM_PCS_ATPCS; + } +} + static void arm_add_gc_roots (void) { @@ -9224,7 +9241,7 @@ arm_unspec_cost (rtx x, enum rtx_code /* outer_code */, bool speed_p, int *cost) return true; \ } \ } \ - while (0); + while (0) /* RTX costs. Make an estimate of the cost of executing the operation X, which is contained with an operation with code OUTER_CODE. @@ -9656,8 +9673,8 @@ arm_rtx_costs_internal (rtx x, enum rtx_code code, enum rtx_code outer_code, /* We check both sides of the MINUS for shifter operands since, unlike PLUS, it's not commutative. */ - HANDLE_NARROW_SHIFT_ARITH (MINUS, 0) - HANDLE_NARROW_SHIFT_ARITH (MINUS, 1) + HANDLE_NARROW_SHIFT_ARITH (MINUS, 0); + HANDLE_NARROW_SHIFT_ARITH (MINUS, 1); /* Slightly disparage, as we might need to widen the result. */ *cost += 1; @@ -9768,7 +9785,7 @@ arm_rtx_costs_internal (rtx x, enum rtx_code code, enum rtx_code outer_code, rtx shift_op, shift_reg; shift_reg = NULL; - HANDLE_NARROW_SHIFT_ARITH (PLUS, 0) + HANDLE_NARROW_SHIFT_ARITH (PLUS, 0); if (CONST_INT_P (XEXP (x, 1))) { @@ -19419,7 +19436,12 @@ arm_get_vfp_saved_size (void) /* Generate a function exit sequence. If REALLY_RETURN is false, then do everything bar the final return instruction. If simple_return is true, - then do not output epilogue, because it has already been emitted in RTL. */ + then do not output epilogue, because it has already been emitted in RTL. + + Note: do not forget to update length attribute of corresponding insn pattern + when changing assembly output (eg. length attribute of + thumb2_cmse_entry_return when updating Armv8-M Mainline Security Extensions + register clearing sequences). */ const char * output_return_instruction (rtx operand, bool really_return, bool reverse, bool simple_return) @@ -23952,7 +23974,12 @@ thumb_pop (FILE *f, unsigned long mask) /* Generate code to return from a thumb function. If 'reg_containing_return_addr' is -1, then the return address is - actually on the stack, at the stack pointer. */ + actually on the stack, at the stack pointer. + + Note: do not forget to update length attribute of corresponding insn pattern + when changing assembly output (eg. length attribute of epilogue_insns when + updating Armv8-M Baseline Security Extensions register clearing + sequences). */ static void thumb_exit (FILE *f, int reg_containing_return_addr) { diff --git a/gcc/config/arm/arm.h b/gcc/config/arm/arm.h index 65d6db4d086..fa35670ac89 100644 --- a/gcc/config/arm/arm.h +++ b/gcc/config/arm/arm.h @@ -210,10 +210,11 @@ extern tree arm_fp16_type_node; /* FPU supports ARMv8.1 Adv.SIMD extensions. */ #define TARGET_NEON_RDMA (TARGET_NEON && arm_arch8_1) -/* Supports for Dot Product AdvSIMD extensions. */ +/* Supports the Dot Product AdvSIMD extensions. */ #define TARGET_DOTPROD (TARGET_NEON \ && bitmap_bit_p (arm_active_target.isa, \ - isa_bit_dotprod)) + isa_bit_dotprod) \ + && arm_arch8_2) /* FPU supports the floating point FP16 instructions for ARMv8.2 and later. */ #define TARGET_VFP_FP16INST \ diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md index ddb9d8f3590..fd3aebd428a 100644 --- a/gcc/config/arm/arm.md +++ b/gcc/config/arm/arm.md @@ -81,14 +81,17 @@ (const (if_then_else (symbol_ref "TARGET_THUMB1") (const_string "yes") (const_string "no")))) -; We use this attribute to disable alternatives that can produce 32-bit -; instructions inside an IT-block in Thumb2 state. ARMv8 deprecates IT blocks -; that contain 32-bit instructions. -(define_attr "enabled_for_depr_it" "no,yes" (const_string "yes")) - -; This attribute is used to disable a predicated alternative when we have -; arm_restrict_it. -(define_attr "predicable_short_it" "no,yes" (const_string "yes")) +; Mark an instruction as suitable for "short IT" blocks in Thumb-2. +; The arm_restrict_it flag enables the "short IT" feature which +; restricts IT blocks to a single 16-bit instruction. +; This attribute should only be used on 16-bit Thumb-2 instructions +; which may be predicated (the "predicable" attribute must be set). +(define_attr "predicable_short_it" "no,yes" (const_string "no")) + +; Mark an instruction as suitable for "short IT" blocks in Thumb-2. +; This attribute should only be used on instructions which may emit +; an IT block in their expansion which is not a short IT. +(define_attr "enabled_for_short_it" "no,yes" (const_string "yes")) ;; Operand number of an input operand that is shifted. Zero if the ;; given instruction does not shift one of its input operands. @@ -229,7 +232,7 @@ (match_test "arm_restrict_it"))) (const_string "no") - (and (eq_attr "enabled_for_depr_it" "no") + (and (eq_attr "enabled_for_short_it" "no") (match_test "arm_restrict_it")) (const_string "no") @@ -1036,7 +1039,6 @@ "adc%?\\t%0, %1, %3%S2" [(set_attr "conds" "use") (set_attr "predicable" "yes") - (set_attr "predicable_short_it" "no") (set (attr "type") (if_then_else (match_operand 4 "const_int_operand" "") (const_string "alu_shift_imm") (const_string "alu_shift_reg")))] @@ -1136,7 +1138,6 @@ [(set_attr "conds" "use") (set_attr "arch" "*,a,t2") (set_attr "predicable" "yes") - (set_attr "predicable_short_it" "no") (set_attr "type" "adc_reg,adc_imm,alu_shift_imm")] ) @@ -1666,8 +1667,7 @@ "TARGET_32BIT && arm_arch6" "mla%?\\t%0, %2, %1, %3" [(set_attr "type" "mla") - (set_attr "predicable" "yes") - (set_attr "predicable_short_it" "no")] + (set_attr "predicable" "yes")] ) (define_insn "*mulsi3addsi_compare0" @@ -1743,8 +1743,7 @@ "TARGET_32BIT && arm_arch_thumb2" "mls%?\\t%0, %2, %1, %3" [(set_attr "type" "mla") - (set_attr "predicable" "yes") - (set_attr "predicable_short_it" "no")] + (set_attr "predicable" "yes")] ) (define_expand "maddsidi4" @@ -1780,8 +1779,7 @@ "TARGET_32BIT && arm_arch6" "smlal%?\\t%Q0, %R0, %3, %2" [(set_attr "type" "smlal") - (set_attr "predicable" "yes") - (set_attr "predicable_short_it" "no")] + (set_attr "predicable" "yes")] ) ;; 32x32->64 widening multiply. @@ -1818,8 +1816,7 @@ "TARGET_32BIT && arm_arch6" "smull%?\\t%Q0, %R0, %1, %2" [(set_attr "type" "smull") - (set_attr "predicable" "yes") - (set_attr "predicable_short_it" "no")] + (set_attr "predicable" "yes")] ) (define_expand "umulsidi3" @@ -1850,8 +1847,7 @@ "TARGET_32BIT && arm_arch6" "umull%?\\t%Q0, %R0, %1, %2" [(set_attr "type" "umull") - (set_attr "predicable" "yes") - (set_attr "predicable_short_it" "no")] + (set_attr "predicable" "yes")] ) (define_expand "umaddsidi4" @@ -1887,8 +1883,7 @@ "TARGET_32BIT && arm_arch6" "umlal%?\\t%Q0, %R0, %3, %2" [(set_attr "type" "umlal") - (set_attr "predicable" "yes") - (set_attr "predicable_short_it" "no")] + (set_attr "predicable" "yes")] ) (define_expand "smulsi3_highpart" @@ -1932,8 +1927,7 @@ "TARGET_32BIT && arm_arch6" "smull%?\\t%3, %0, %2, %1" [(set_attr "type" "smull") - (set_attr "predicable" "yes") - (set_attr "predicable_short_it" "no")] + (set_attr "predicable" "yes")] ) (define_expand "umulsi3_highpart" @@ -1977,8 +1971,7 @@ "TARGET_32BIT && arm_arch6" "umull%?\\t%3, %0, %2, %1" [(set_attr "type" "umull") - (set_attr "predicable" "yes") - (set_attr "predicable_short_it" "no")] + (set_attr "predicable" "yes")] ) (define_insn "mulhisi3" @@ -2003,8 +1996,7 @@ "TARGET_DSP_MULTIPLY" "smultb%?\\t%0, %1, %2" [(set_attr "type" "smulxy") - (set_attr "predicable" "yes") - (set_attr "predicable_short_it" "no")] + (set_attr "predicable" "yes")] ) (define_insn "*mulhisi3bt" @@ -2017,8 +2009,7 @@ "TARGET_DSP_MULTIPLY" "smulbt%?\\t%0, %1, %2" [(set_attr "type" "smulxy") - (set_attr "predicable" "yes") - (set_attr "predicable_short_it" "no")] + (set_attr "predicable" "yes")] ) (define_insn "*mulhisi3tt" @@ -2032,8 +2023,7 @@ "TARGET_DSP_MULTIPLY" "smultt%?\\t%0, %1, %2" [(set_attr "type" "smulxy") - (set_attr "predicable" "yes") - (set_attr "predicable_short_it" "no")] + (set_attr "predicable" "yes")] ) (define_insn "maddhisi4" @@ -2046,8 +2036,7 @@ "TARGET_DSP_MULTIPLY" "smlabb%?\\t%0, %1, %2, %3" [(set_attr "type" "smlaxy") - (set_attr "predicable" "yes") - (set_attr "predicable_short_it" "no")] + (set_attr "predicable" "yes")] ) ;; Note: there is no maddhisi4ibt because this one is canonical form @@ -2062,8 +2051,7 @@ "TARGET_DSP_MULTIPLY" "smlatb%?\\t%0, %1, %2, %3" [(set_attr "type" "smlaxy") - (set_attr "predicable" "yes") - (set_attr "predicable_short_it" "no")] + (set_attr "predicable" "yes")] ) (define_insn "*maddhisi4tt" @@ -2078,8 +2066,7 @@ "TARGET_DSP_MULTIPLY" "smlatt%?\\t%0, %1, %2, %3" [(set_attr "type" "smlaxy") - (set_attr "predicable" "yes") - (set_attr "predicable_short_it" "no")] + (set_attr "predicable" "yes")] ) (define_insn "maddhidi4" @@ -2093,8 +2080,7 @@ "TARGET_DSP_MULTIPLY" "smlalbb%?\\t%Q0, %R0, %1, %2" [(set_attr "type" "smlalxy") - (set_attr "predicable" "yes") - (set_attr "predicable_short_it" "no")]) + (set_attr "predicable" "yes")]) ;; Note: there is no maddhidi4ibt because this one is canonical form (define_insn "*maddhidi4tb" @@ -2110,8 +2096,7 @@ "TARGET_DSP_MULTIPLY" "smlaltb%?\\t%Q0, %R0, %1, %2" [(set_attr "type" "smlalxy") - (set_attr "predicable" "yes") - (set_attr "predicable_short_it" "no")]) + (set_attr "predicable" "yes")]) (define_insn "*maddhidi4tt" [(set (match_operand:DI 0 "s_register_operand" "=r") @@ -2128,8 +2113,7 @@ "TARGET_DSP_MULTIPLY" "smlaltt%?\\t%Q0, %R0, %1, %2" [(set_attr "type" "smlalxy") - (set_attr "predicable" "yes") - (set_attr "predicable_short_it" "no")]) + (set_attr "predicable" "yes")]) (define_expand "mulsf3" [(set (match_operand:SF 0 "s_register_operand" "") @@ -2518,7 +2502,6 @@ " [(set_attr "conds" "set") (set_attr "predicable" "yes") - (set_attr "predicable_short_it" "no") (set_attr "type" "logics_imm")] ) @@ -2918,7 +2901,6 @@ "bfc%?\t%0, %2, %1" [(set_attr "length" "4") (set_attr "predicable" "yes") - (set_attr "predicable_short_it" "no") (set_attr "type" "bfm")] ) @@ -2931,7 +2913,6 @@ "bfi%?\t%0, %3, %2, %1" [(set_attr "length" "4") (set_attr "predicable" "yes") - (set_attr "predicable_short_it" "no") (set_attr "type" "bfm")] ) @@ -2986,7 +2967,6 @@ }" [(set_attr "length" "4,8") (set_attr "predicable" "yes") - (set_attr "predicable_short_it" "no") (set_attr "type" "multiple")] ) @@ -3008,7 +2988,6 @@ }" [(set_attr "length" "8") (set_attr "predicable" "yes") - (set_attr "predicable_short_it" "no") (set_attr "type" "multiple")] ) @@ -3033,7 +3012,6 @@ }" [(set_attr "length" "8") (set_attr "predicable" "yes") - (set_attr "predicable_short_it" "no") (set_attr "type" "multiple")] ) @@ -3044,7 +3022,6 @@ "TARGET_32BIT" "bic%?\\t%0, %1, %2" [(set_attr "predicable" "yes") - (set_attr "predicable_short_it" "no") (set_attr "type" "logic_reg")] ) @@ -3078,7 +3055,6 @@ "TARGET_ARM || (TARGET_THUMB2 && CONST_INT_P (operands[2]))" "bics%?\\t%4, %3, %1%S0" [(set_attr "predicable" "yes") - (set_attr "predicable_short_it" "no") (set_attr "conds" "set") (set_attr "shift" "1") (set (attr "type") (if_then_else (match_operand 2 "const_int_operand" "") @@ -3104,7 +3080,6 @@ "TARGET_ARM || (TARGET_THUMB2 && CONST_INT_P (operands[2]))" "bics%?\\t%4, %3, %1%S0" [(set_attr "predicable" "yes") - (set_attr "predicable_short_it" "no") (set_attr "conds" "set") (set_attr "shift" "1") (set (attr "type") (if_then_else (match_operand 2 "const_int_operand" "") @@ -3219,7 +3194,6 @@ #" [(set_attr "length" "4,8") (set_attr "predicable" "yes") - (set_attr "predicable_short_it" "no") (set_attr "type" "logic_reg,multiple")] ) @@ -3419,7 +3393,6 @@ #" [(set_attr "length" "4,8") (set_attr "predicable" "yes") - (set_attr "predicable_short_it" "no") (set_attr "type" "logic_reg")] ) @@ -3563,7 +3536,6 @@ [(set_attr "length" "8") (set_attr "ce_count" "2") (set_attr "predicable" "yes") - (set_attr "predicable_short_it" "no") (set_attr "type" "multiple")] ) @@ -3701,7 +3673,6 @@ "TARGET_32BIT" "bic%?\\t%0, %1, %1, asr #31" [(set_attr "predicable" "yes") - (set_attr "predicable_short_it" "no") (set_attr "type" "logic_shift_reg")] ) @@ -3712,7 +3683,6 @@ "TARGET_32BIT" "orr%?\\t%0, %1, %1, asr #31" [(set_attr "predicable" "yes") - (set_attr "predicable_short_it" "no") (set_attr "type" "logic_shift_reg")] ) @@ -3763,7 +3733,6 @@ "TARGET_32BIT" "and%?\\t%0, %1, %1, asr #31" [(set_attr "predicable" "yes") - (set_attr "predicable_short_it" "no") (set_attr "type" "logic_shift_reg")] ) @@ -4000,7 +3969,6 @@ return "usat%?\t%0, %1, %3"; } [(set_attr "predicable" "yes") - (set_attr "predicable_short_it" "no") (set_attr "type" "alus_imm")] ) @@ -4027,7 +3995,6 @@ return "usat%?\t%0, %1, %4%S3"; } [(set_attr "predicable" "yes") - (set_attr "predicable_short_it" "no") (set_attr "shift" "3") (set_attr "type" "logic_shift_reg")]) @@ -4278,7 +4245,6 @@ "TARGET_32BIT" "mvn%?\\t%0, %1%S3" [(set_attr "predicable" "yes") - (set_attr "predicable_short_it" "no") (set_attr "shift" "1") (set_attr "arch" "32,a") (set_attr "type" "mvn_shift,mvn_shift_reg")]) @@ -4554,7 +4520,6 @@ "sbfx%?\t%0, %1, %3, %2" [(set_attr "length" "4") (set_attr "predicable" "yes") - (set_attr "predicable_short_it" "no") (set_attr "type" "bfm")] ) @@ -4569,7 +4534,6 @@ "ubfx%?\t%0, %1, %3, %2" [(set_attr "length" "4") (set_attr "predicable" "yes") - (set_attr "predicable_short_it" "no") (set_attr "type" "bfm")] ) @@ -4585,7 +4549,6 @@ sdiv\t%0, %1, %2" [(set_attr "arch" "32,v8mb") (set_attr "predicable" "yes") - (set_attr "predicable_short_it" "no") (set_attr "type" "sdiv")] ) @@ -4599,7 +4562,6 @@ udiv\t%0, %1, %2" [(set_attr "arch" "32,v8mb") (set_attr "predicable" "yes") - (set_attr "predicable_short_it" "no") (set_attr "type" "udiv")] ) @@ -5377,8 +5339,7 @@ "TARGET_INT_SIMD" "uxtah%?\\t%0, %2, %1" [(set_attr "type" "alu_shift_reg") - (set_attr "predicable" "yes") - (set_attr "predicable_short_it" "no")] + (set_attr "predicable" "yes")] ) (define_expand "zero_extendqisi2" @@ -5448,7 +5409,6 @@ "TARGET_INT_SIMD" "uxtab%?\\t%0, %2, %1" [(set_attr "predicable" "yes") - (set_attr "predicable_short_it" "no") (set_attr "type" "alu_shift_reg")] ) @@ -5501,7 +5461,6 @@ "tst%?\\t%0, #255" [(set_attr "conds" "set") (set_attr "predicable" "yes") - (set_attr "predicable_short_it" "no") (set_attr "type" "logic_imm")] ) @@ -5611,8 +5570,7 @@ sxth%?\\t%0, %1 ldrsh%?\\t%0, %1" [(set_attr "type" "extend,load_byte") - (set_attr "predicable" "yes") - (set_attr "predicable_short_it" "no")] + (set_attr "predicable" "yes")] ) (define_insn "*arm_extendhisi2addsi" @@ -5716,8 +5674,7 @@ "TARGET_INT_SIMD" "sxtab%?\\t%0, %2, %1" [(set_attr "type" "alu_shift_reg") - (set_attr "predicable" "yes") - (set_attr "predicable_short_it" "no")] + (set_attr "predicable" "yes")] ) (define_expand "extendsfdf2" @@ -6084,7 +6041,6 @@ movt\t%0, #:upper16:%c2" [(set_attr "arch" "32,v8mb") (set_attr "predicable" "yes") - (set_attr "predicable_short_it" "no") (set_attr "length" "4") (set_attr "type" "alu_sreg")] ) @@ -6964,8 +6920,7 @@ [(set_attr "conds" "unconditional") (set_attr "type" "load_4,store_4,mov_reg,multiple") (set_attr "length" "4,4,4,8") - (set_attr "predicable" "yes") - (set_attr "predicable_short_it" "no")] + (set_attr "predicable" "yes")] ) (define_expand "movsf" @@ -7018,7 +6973,6 @@ ldr%?\\t%0, %1\\t%@ float str%?\\t%1, %0\\t%@ float" [(set_attr "predicable" "yes") - (set_attr "predicable_short_it" "no") (set_attr "type" "mov_reg,load_4,store_4") (set_attr "arm_pool_range" "*,4096,*") (set_attr "thumb2_pool_range" "*,4094,*") @@ -7436,7 +7390,7 @@ operands[1] = gen_lowpart (SImode, operands[1]); } [(set_attr "conds" "set") - (set_attr "enabled_for_depr_it" "yes,yes,no,*") + (set_attr "enabled_for_short_it" "yes,yes,no,*") (set_attr "arch" "t2,t2,t2,a") (set_attr "length" "6,6,10,8") (set_attr "type" "multiple")] @@ -8823,7 +8777,6 @@ "TARGET_32BIT" "<arith_shift_insn>%?\\t%0, %1, %2, lsl %b3" [(set_attr "predicable" "yes") - (set_attr "predicable_short_it" "no") (set_attr "shift" "2") (set_attr "arch" "a,t2") (set_attr "type" "alu_shift_imm")]) @@ -8838,7 +8791,6 @@ "TARGET_32BIT && GET_CODE (operands[2]) != MULT" "<arith_shift_insn>%?\\t%0, %1, %3%S2" [(set_attr "predicable" "yes") - (set_attr "predicable_short_it" "no") (set_attr "shift" "3") (set_attr "arch" "a,t2,a") (set_attr "type" "alu_shift_imm,alu_shift_imm,alu_shift_reg")]) @@ -8906,6 +8858,7 @@ "TARGET_32BIT" "sub%?\\t%0, %1, %3%S2" [(set_attr "predicable" "yes") + (set_attr "predicable_short_it" "no") (set_attr "shift" "3") (set_attr "arch" "32,a") (set_attr "type" "alus_shift_imm,alus_shift_reg")]) @@ -9344,6 +9297,7 @@ }" [(set_attr "conds" "set") (set_attr "arch" "t2,t2,t2,t2,t2,any,any,any,any") + (set_attr "enabled_for_short_it" "yes,no,no,no,no,no,no,no,no") (set_attr "type" "multiple") (set_attr_alternative "length" [(const_int 6) @@ -9427,6 +9381,7 @@ }" [(set_attr "conds" "set") (set_attr "arch" "t2,t2,t2,t2,t2,any,any,any,any") + (set_attr "enabled_for_short_it" "yes,no,no,no,no,no,no,no,no") (set_attr_alternative "length" [(const_int 6) (const_int 8) @@ -9509,7 +9464,7 @@ [(set_attr "conds" "set") (set_attr "predicable" "no") (set_attr "arch" "t2,t2,t2,t2,t2,any,any,any,any") - (set_attr "enabled_for_depr_it" "yes,no,no,no,no,no,no,no,no") + (set_attr "enabled_for_short_it" "yes,no,no,no,no,no,no,no,no") (set_attr_alternative "length" [(const_int 6) (const_int 8) @@ -9592,7 +9547,7 @@ " [(set_attr "conds" "set") (set_attr "arch" "t2,t2,t2,t2,t2,any,any,any,any") - (set_attr "enabled_for_depr_it" "yes,no,no,no,no,no,no,no,no") + (set_attr "enabled_for_short_it" "yes,no,no,no,no,no,no,no,no") (set_attr_alternative "length" [(const_int 6) (const_int 8) @@ -9640,7 +9595,7 @@ DOM_CC_X_OR_Y), CC_REGNUM);" [(set_attr "conds" "clob") - (set_attr "enabled_for_depr_it" "yes,no") + (set_attr "enabled_for_short_it" "yes,no") (set_attr "length" "16") (set_attr "type" "multiple")] ) @@ -9671,7 +9626,7 @@ (set (match_dup 7) (ne:SI (match_dup 0) (const_int 0)))] "" [(set_attr "conds" "set") - (set_attr "enabled_for_depr_it" "yes,no") + (set_attr "enabled_for_short_it" "yes,no") (set_attr "length" "16") (set_attr "type" "multiple")] ) @@ -9704,7 +9659,7 @@ DOM_CC_X_AND_Y), CC_REGNUM);" [(set_attr "conds" "clob") - (set_attr "enabled_for_depr_it" "yes,no") + (set_attr "enabled_for_short_it" "yes,no") (set_attr "length" "16") (set_attr "type" "multiple")] ) @@ -9735,7 +9690,7 @@ (set (match_dup 7) (ne:SI (match_dup 0) (const_int 0)))] "" [(set_attr "conds" "set") - (set_attr "enabled_for_depr_it" "yes,no") + (set_attr "enabled_for_short_it" "yes,no") (set_attr "length" "16") (set_attr "type" "multiple")] ) @@ -9922,7 +9877,7 @@ } " [(set_attr "conds" "clob") - (set_attr "enabled_for_depr_it" "no,yes,yes") + (set_attr "enabled_for_short_it" "no,yes,yes") (set_attr "type" "multiple")] ) @@ -10540,7 +10495,7 @@ [(set_attr "conds" "use") (set_attr "length" "4") (set_attr "arch" "t2,32") - (set_attr "enabled_for_depr_it" "yes,no") + (set_attr "enabled_for_short_it" "yes,no") (set_attr "type" "logic_shift_imm")] ) @@ -10586,7 +10541,7 @@ [(set_attr "conds" "use") (set_attr "length" "4") (set_attr "arch" "t2,32") - (set_attr "enabled_for_depr_it" "yes,no") + (set_attr "enabled_for_short_it" "yes,no") (set_attr "type" "logic_shift_imm")] ) @@ -11322,7 +11277,6 @@ "TARGET_32BIT && arm_arch5" "clz%?\\t%0, %1" [(set_attr "predicable" "yes") - (set_attr "predicable_short_it" "no") (set_attr "type" "clz")]) (define_insn "rbitsi2" @@ -11331,7 +11285,6 @@ "TARGET_32BIT && arm_arch_thumb2" "rbit%?\\t%0, %1" [(set_attr "predicable" "yes") - (set_attr "predicable_short_it" "no") (set_attr "type" "clz")]) ;; Keep this as a CTZ expression until after reload and then split @@ -11483,7 +11436,6 @@ movt\t%0, %L1" [(set_attr "arch" "32,v8mb") (set_attr "predicable" "yes") - (set_attr "predicable_short_it" "no") (set_attr "length" "4") (set_attr "type" "alu_sreg")] ) @@ -11499,7 +11451,6 @@ [(set_attr "arch" "t1,t2,32") (set_attr "length" "2,2,4") (set_attr "predicable" "no,yes,yes") - (set_attr "predicable_short_it" "no") (set_attr "type" "rev")] ) @@ -11747,8 +11698,7 @@ false, true))" "ldrd%?\t%0, %3, [%1, %2]" [(set_attr "type" "load_8") - (set_attr "predicable" "yes") - (set_attr "predicable_short_it" "no")]) + (set_attr "predicable" "yes")]) (define_insn "*thumb2_ldrd_base" [(set (match_operand:SI 0 "s_register_operand" "=r") @@ -11761,8 +11711,7 @@ operands[1], 0, false, true))" "ldrd%?\t%0, %2, [%1]" [(set_attr "type" "load_8") - (set_attr "predicable" "yes") - (set_attr "predicable_short_it" "no")]) + (set_attr "predicable" "yes")]) (define_insn "*thumb2_ldrd_base_neg" [(set (match_operand:SI 0 "s_register_operand" "=r") @@ -11775,8 +11724,7 @@ operands[1], -4, false, true))" "ldrd%?\t%0, %2, [%1, #-4]" [(set_attr "type" "load_8") - (set_attr "predicable" "yes") - (set_attr "predicable_short_it" "no")]) + (set_attr "predicable" "yes")]) (define_insn "*thumb2_strd" [(set (mem:SI (plus:SI (match_operand:SI 0 "s_register_operand" "rk") @@ -11792,8 +11740,7 @@ false, false))" "strd%?\t%2, %4, [%0, %1]" [(set_attr "type" "store_8") - (set_attr "predicable" "yes") - (set_attr "predicable_short_it" "no")]) + (set_attr "predicable" "yes")]) (define_insn "*thumb2_strd_base" [(set (mem:SI (match_operand:SI 0 "s_register_operand" "rk")) @@ -11806,8 +11753,7 @@ operands[0], 0, false, false))" "strd%?\t%1, %2, [%0]" [(set_attr "type" "store_8") - (set_attr "predicable" "yes") - (set_attr "predicable_short_it" "no")]) + (set_attr "predicable" "yes")]) (define_insn "*thumb2_strd_base_neg" [(set (mem:SI (plus:SI (match_operand:SI 0 "s_register_operand" "rk") @@ -11820,8 +11766,7 @@ operands[0], -4, false, false))" "strd%?\t%1, %2, [%0, #-4]" [(set_attr "type" "store_8") - (set_attr "predicable" "yes") - (set_attr "predicable_short_it" "no")]) + (set_attr "predicable" "yes")]) ;; ARMv8 CRC32 instructions. (define_insn "<crc_variant>" diff --git a/gcc/config/arm/ldmstm.md b/gcc/config/arm/ldmstm.md index 01fbb553fbc..d7650d4f809 100644 --- a/gcc/config/arm/ldmstm.md +++ b/gcc/config/arm/ldmstm.md @@ -37,8 +37,7 @@ "TARGET_32BIT && XVECLEN (operands[0], 0) == 4" "ldm%?\t%5, {%1, %2, %3, %4}" [(set_attr "type" "load_16") - (set_attr "predicable" "yes") - (set_attr "predicable_short_it" "no")]) + (set_attr "predicable" "yes")]) (define_insn "*thumb_ldm4_ia" [(match_parallel 0 "load_multiple_operation" @@ -75,8 +74,7 @@ "TARGET_32BIT && XVECLEN (operands[0], 0) == 5" "ldmia%?\t%5!, {%1, %2, %3, %4}" [(set_attr "type" "load_16") - (set_attr "predicable" "yes") - (set_attr "predicable_short_it" "no")]) + (set_attr "predicable" "yes")]) (define_insn "*thumb_ldm4_ia_update" [(match_parallel 0 "load_multiple_operation" @@ -110,8 +108,7 @@ "TARGET_32BIT && XVECLEN (operands[0], 0) == 4" "stm%?\t%5, {%1, %2, %3, %4}" [(set_attr "type" "store_16") - (set_attr "predicable" "yes") - (set_attr "predicable_short_it" "no")]) + (set_attr "predicable" "yes")]) (define_insn "*stm4_ia_update" [(match_parallel 0 "store_multiple_operation" @@ -128,8 +125,7 @@ "TARGET_32BIT && XVECLEN (operands[0], 0) == 5" "stmia%?\t%5!, {%1, %2, %3, %4}" [(set_attr "type" "store_16") - (set_attr "predicable" "yes") - (set_attr "predicable_short_it" "no")]) + (set_attr "predicable" "yes")]) (define_insn "*thumb_stm4_ia_update" [(match_parallel 0 "store_multiple_operation" @@ -306,8 +302,7 @@ "TARGET_32BIT && XVECLEN (operands[0], 0) == 4" "ldmdb%?\t%5, {%1, %2, %3, %4}" [(set_attr "type" "load_16") - (set_attr "predicable" "yes") - (set_attr "predicable_short_it" "no")]) + (set_attr "predicable" "yes")]) (define_insn "*ldm4_db_update" [(match_parallel 0 "load_multiple_operation" @@ -328,8 +323,7 @@ "TARGET_32BIT && XVECLEN (operands[0], 0) == 5" "ldmdb%?\t%5!, {%1, %2, %3, %4}" [(set_attr "type" "load_16") - (set_attr "predicable" "yes") - (set_attr "predicable_short_it" "no")]) + (set_attr "predicable" "yes")]) (define_insn "*stm4_db" [(match_parallel 0 "store_multiple_operation" @@ -344,8 +338,7 @@ "TARGET_32BIT && XVECLEN (operands[0], 0) == 4" "stmdb%?\t%5, {%1, %2, %3, %4}" [(set_attr "type" "store_16") - (set_attr "predicable" "yes") - (set_attr "predicable_short_it" "no")]) + (set_attr "predicable" "yes")]) (define_insn "*stm4_db_update" [(match_parallel 0 "store_multiple_operation" @@ -362,8 +355,7 @@ "TARGET_32BIT && XVECLEN (operands[0], 0) == 5" "stmdb%?\t%5!, {%1, %2, %3, %4}" [(set_attr "type" "store_16") - (set_attr "predicable" "yes") - (set_attr "predicable_short_it" "no")]) + (set_attr "predicable" "yes")]) (define_peephole2 [(set (match_operand:SI 0 "s_register_operand" "") @@ -485,8 +477,7 @@ "TARGET_32BIT && XVECLEN (operands[0], 0) == 3" "ldm%?\t%4, {%1, %2, %3}" [(set_attr "type" "load_12") - (set_attr "predicable" "yes") - (set_attr "predicable_short_it" "no")]) + (set_attr "predicable" "yes")]) (define_insn "*thumb_ldm3_ia" [(match_parallel 0 "load_multiple_operation" @@ -517,8 +508,7 @@ "TARGET_32BIT && XVECLEN (operands[0], 0) == 4" "ldmia%?\t%4!, {%1, %2, %3}" [(set_attr "type" "load_12") - (set_attr "predicable" "yes") - (set_attr "predicable_short_it" "no")]) + (set_attr "predicable" "yes")]) (define_insn "*thumb_ldm3_ia_update" [(match_parallel 0 "load_multiple_operation" @@ -547,8 +537,7 @@ "TARGET_32BIT && XVECLEN (operands[0], 0) == 3" "stm%?\t%4, {%1, %2, %3}" [(set_attr "type" "store_12") - (set_attr "predicable" "yes") - (set_attr "predicable_short_it" "no")]) + (set_attr "predicable" "yes")]) (define_insn "*stm3_ia_update" [(match_parallel 0 "store_multiple_operation" @@ -563,8 +552,7 @@ "TARGET_32BIT && XVECLEN (operands[0], 0) == 4" "stmia%?\t%4!, {%1, %2, %3}" [(set_attr "type" "store_12") - (set_attr "predicable" "yes") - (set_attr "predicable_short_it" "no")]) + (set_attr "predicable" "yes")]) (define_insn "*thumb_stm3_ia_update" [(match_parallel 0 "store_multiple_operation" @@ -716,8 +704,7 @@ "TARGET_32BIT && XVECLEN (operands[0], 0) == 3" "ldmdb%?\t%4, {%1, %2, %3}" [(set_attr "type" "load_12") - (set_attr "predicable" "yes") - (set_attr "predicable_short_it" "no")]) + (set_attr "predicable" "yes")]) (define_insn "*ldm3_db_update" [(match_parallel 0 "load_multiple_operation" @@ -735,8 +722,7 @@ "TARGET_32BIT && XVECLEN (operands[0], 0) == 4" "ldmdb%?\t%4!, {%1, %2, %3}" [(set_attr "type" "load_12") - (set_attr "predicable" "yes") - (set_attr "predicable_short_it" "no")]) + (set_attr "predicable" "yes")]) (define_insn "*stm3_db" [(match_parallel 0 "store_multiple_operation" @@ -749,8 +735,7 @@ "TARGET_32BIT && XVECLEN (operands[0], 0) == 3" "stmdb%?\t%4, {%1, %2, %3}" [(set_attr "type" "store_12") - (set_attr "predicable" "yes") - (set_attr "predicable_short_it" "no")]) + (set_attr "predicable" "yes")]) (define_insn "*stm3_db_update" [(match_parallel 0 "store_multiple_operation" @@ -765,8 +750,7 @@ "TARGET_32BIT && XVECLEN (operands[0], 0) == 4" "stmdb%?\t%4!, {%1, %2, %3}" [(set_attr "type" "store_12") - (set_attr "predicable" "yes") - (set_attr "predicable_short_it" "no")]) + (set_attr "predicable" "yes")]) (define_peephole2 [(set (match_operand:SI 0 "s_register_operand" "") @@ -871,8 +855,7 @@ "TARGET_32BIT && XVECLEN (operands[0], 0) == 2" "ldm%?\t%3, {%1, %2}" [(set_attr "type" "load_8") - (set_attr "predicable" "yes") - (set_attr "predicable_short_it" "no")]) + (set_attr "predicable" "yes")]) (define_insn "*thumb_ldm2_ia" [(match_parallel 0 "load_multiple_operation" @@ -897,8 +880,7 @@ "TARGET_32BIT && XVECLEN (operands[0], 0) == 3" "ldmia%?\t%3!, {%1, %2}" [(set_attr "type" "load_8") - (set_attr "predicable" "yes") - (set_attr "predicable_short_it" "no")]) + (set_attr "predicable" "yes")]) (define_insn "*thumb_ldm2_ia_update" [(match_parallel 0 "load_multiple_operation" @@ -922,8 +904,7 @@ "TARGET_32BIT && XVECLEN (operands[0], 0) == 2" "stm%?\t%3, {%1, %2}" [(set_attr "type" "store_8") - (set_attr "predicable" "yes") - (set_attr "predicable_short_it" "no")]) + (set_attr "predicable" "yes")]) (define_insn "*stm2_ia_update" [(match_parallel 0 "store_multiple_operation" @@ -936,8 +917,7 @@ "TARGET_32BIT && XVECLEN (operands[0], 0) == 3" "stmia%?\t%3!, {%1, %2}" [(set_attr "type" "store_8") - (set_attr "predicable" "yes") - (set_attr "predicable_short_it" "no")]) + (set_attr "predicable" "yes")]) (define_insn "*thumb_stm2_ia_update" [(match_parallel 0 "store_multiple_operation" @@ -1064,8 +1044,7 @@ "TARGET_32BIT && XVECLEN (operands[0], 0) == 2" "ldmdb%?\t%3, {%1, %2}" [(set_attr "type" "load_8") - (set_attr "predicable" "yes") - (set_attr "predicable_short_it" "no")]) + (set_attr "predicable" "yes")]) (define_insn "*ldm2_db_update" [(match_parallel 0 "load_multiple_operation" @@ -1080,8 +1059,7 @@ "TARGET_32BIT && XVECLEN (operands[0], 0) == 3" "ldmdb%?\t%3!, {%1, %2}" [(set_attr "type" "load_8") - (set_attr "predicable" "yes") - (set_attr "predicable_short_it" "no")]) + (set_attr "predicable" "yes")]) (define_insn "*stm2_db" [(match_parallel 0 "store_multiple_operation" @@ -1092,8 +1070,7 @@ "TARGET_32BIT && XVECLEN (operands[0], 0) == 2" "stmdb%?\t%3, {%1, %2}" [(set_attr "type" "store_8") - (set_attr "predicable" "yes") - (set_attr "predicable_short_it" "no")]) + (set_attr "predicable" "yes")]) (define_insn "*stm2_db_update" [(match_parallel 0 "store_multiple_operation" @@ -1106,8 +1083,7 @@ "TARGET_32BIT && XVECLEN (operands[0], 0) == 3" "stmdb%?\t%3!, {%1, %2}" [(set_attr "type" "store_8") - (set_attr "predicable" "yes") - (set_attr "predicable_short_it" "no")]) + (set_attr "predicable" "yes")]) (define_peephole2 [(set (match_operand:SI 0 "s_register_operand" "") diff --git a/gcc/config/arm/sync.md b/gcc/config/arm/sync.md index b4b4f2e6815..37a4cb3f1c5 100644 --- a/gcc/config/arm/sync.md +++ b/gcc/config/arm/sync.md @@ -87,8 +87,7 @@ } } [(set_attr "arch" "32,v8mb,any") - (set_attr "predicable" "yes") - (set_attr "predicable_short_it" "no")]) + (set_attr "predicable" "yes")]) (define_insn "atomic_store<mode>" [(set (match_operand:QHSI 0 "memory_operand" "=Q,Q,Q") @@ -115,8 +114,7 @@ } } [(set_attr "arch" "32,v8mb,any") - (set_attr "predicable" "yes") - (set_attr "predicable_short_it" "no")]) + (set_attr "predicable" "yes")]) ;; An LDRD instruction usable by the atomic_loaddi expander on LPAE targets @@ -127,8 +125,7 @@ VUNSPEC_LDRD_ATOMIC))] "ARM_DOUBLEWORD_ALIGN && TARGET_HAVE_LPAE" "ldrd%?\t%0, %H0, %C1" - [(set_attr "predicable" "yes") - (set_attr "predicable_short_it" "no")]) + [(set_attr "predicable" "yes")]) ;; There are three ways to expand this depending on the architecture ;; features available. As for the barriers, a load needs a barrier @@ -461,8 +458,7 @@ ldrex<sync_sfx>%?\t%0, %C1 ldrex<sync_sfx>\t%0, %C1" [(set_attr "arch" "32,v8mb") - (set_attr "predicable" "yes") - (set_attr "predicable_short_it" "no")]) + (set_attr "predicable" "yes")]) (define_insn "arm_load_acquire_exclusive<mode>" [(set (match_operand:SI 0 "s_register_operand" "=r,r") @@ -475,8 +471,7 @@ ldaex<sync_sfx>%?\\t%0, %C1 ldaex<sync_sfx>\\t%0, %C1" [(set_attr "arch" "32,v8mb") - (set_attr "predicable" "yes") - (set_attr "predicable_short_it" "no")]) + (set_attr "predicable" "yes")]) (define_insn "arm_load_exclusivesi" [(set (match_operand:SI 0 "s_register_operand" "=r,r") @@ -488,8 +483,7 @@ ldrex%?\t%0, %C1 ldrex\t%0, %C1" [(set_attr "arch" "32,v8mb") - (set_attr "predicable" "yes") - (set_attr "predicable_short_it" "no")]) + (set_attr "predicable" "yes")]) (define_insn "arm_load_acquire_exclusivesi" [(set (match_operand:SI 0 "s_register_operand" "=r,r") @@ -501,8 +495,7 @@ ldaex%?\t%0, %C1 ldaex\t%0, %C1" [(set_attr "arch" "32,v8mb") - (set_attr "predicable" "yes") - (set_attr "predicable_short_it" "no")]) + (set_attr "predicable" "yes")]) (define_insn "arm_load_exclusivedi" [(set (match_operand:DI 0 "s_register_operand" "=r") @@ -511,8 +504,7 @@ VUNSPEC_LL))] "TARGET_HAVE_LDREXD" "ldrexd%?\t%0, %H0, %C1" - [(set_attr "predicable" "yes") - (set_attr "predicable_short_it" "no")]) + [(set_attr "predicable" "yes")]) (define_insn "arm_load_acquire_exclusivedi" [(set (match_operand:DI 0 "s_register_operand" "=r") @@ -521,8 +513,7 @@ VUNSPEC_LAX))] "TARGET_HAVE_LDACQEXD && ARM_DOUBLEWORD_ALIGN" "ldaexd%?\t%0, %H0, %C1" - [(set_attr "predicable" "yes") - (set_attr "predicable_short_it" "no")]) + [(set_attr "predicable" "yes")]) (define_insn "arm_store_exclusive<mode>" [(set (match_operand:SI 0 "s_register_operand" "=&r") @@ -548,8 +539,7 @@ else return "strex<sync_sfx>%?\t%0, %2, %C1"; } - [(set_attr "predicable" "yes") - (set_attr "predicable_short_it" "no")]) + [(set_attr "predicable" "yes")]) (define_insn "arm_store_release_exclusivedi" [(set (match_operand:SI 0 "s_register_operand" "=&r") @@ -564,8 +554,7 @@ gcc_assert ((REGNO (operands[2]) & 1) == 0 || TARGET_THUMB2); return "stlexd%?\t%0, %2, %H2, %C1"; } - [(set_attr "predicable" "yes") - (set_attr "predicable_short_it" "no")]) + [(set_attr "predicable" "yes")]) (define_insn "arm_store_release_exclusive<mode>" [(set (match_operand:SI 0 "s_register_operand" "=&r,&r") @@ -579,5 +568,4 @@ stlex<sync_sfx>%?\t%0, %2, %C1 stlex<sync_sfx>\t%0, %2, %C1" [(set_attr "arch" "32,v8mb") - (set_attr "predicable" "yes") - (set_attr "predicable_short_it" "no")]) + (set_attr "predicable" "yes")]) diff --git a/gcc/config/arm/thumb2.md b/gcc/config/arm/thumb2.md index b78c3d256ae..abe90d4f4e4 100644 --- a/gcc/config/arm/thumb2.md +++ b/gcc/config/arm/thumb2.md @@ -34,7 +34,6 @@ "TARGET_THUMB2" "bic%?\\t%0, %1, %2%S4" [(set_attr "predicable" "yes") - (set_attr "predicable_short_it" "no") (set_attr "shift" "2") (set_attr "type" "alu_shift_imm")] ) @@ -57,7 +56,7 @@ (match_dup 2)))] "" [(set_attr "conds" "clob") - (set_attr "enabled_for_depr_it" "yes,yes,no") + (set_attr "enabled_for_short_it" "yes,yes,no") (set_attr "length" "6,6,10") (set_attr "type" "multiple")] ) @@ -78,7 +77,7 @@ (match_dup 2)))] "" [(set_attr "conds" "clob") - (set_attr "enabled_for_depr_it" "yes,yes,no") + (set_attr "enabled_for_short_it" "yes,yes,no") (set_attr "length" "6,6,10") (set_attr "type" "multiple")] ) @@ -100,7 +99,7 @@ "" [(set_attr "conds" "clob") (set_attr "length" "6,6,10") - (set_attr "enabled_for_depr_it" "yes,yes,no") + (set_attr "enabled_for_short_it" "yes,yes,no") (set_attr "type" "multiple")] ) @@ -121,7 +120,7 @@ "" [(set_attr "conds" "clob") (set_attr "length" "6,6,10") - (set_attr "enabled_for_depr_it" "yes,yes,no") + (set_attr "enabled_for_short_it" "yes,yes,no") (set_attr "type" "multiple")] ) @@ -172,8 +171,7 @@ [(set_attr "conds" "*,clob,clob") (set_attr "shift" "1") (set_attr "predicable" "yes,no,no") - (set_attr "predicable_short_it" "no") - (set_attr "enabled_for_depr_it" "yes,yes,no") + (set_attr "enabled_for_short_it" "yes,yes,no") (set_attr "ce_count" "2") (set_attr "length" "8,6,10") (set_attr "type" "multiple")] @@ -226,8 +224,7 @@ [(set_attr "conds" "*,clob,clob") (set_attr "shift" "1") (set_attr "predicable" "yes,no,no") - (set_attr "enabled_for_depr_it" "yes,yes,no") - (set_attr "predicable_short_it" "no") + (set_attr "enabled_for_short_it" "yes,yes,no") (set_attr "ce_count" "2") (set_attr "length" "8,6,10") (set_attr "type" "multiple")] @@ -354,7 +351,7 @@ (const_int 0)))] "" [(set_attr "conds" "use") - (set_attr "enabled_for_depr_it" "yes,no") + (set_attr "enabled_for_short_it" "yes,no") (set_attr "length" "8,10") (set_attr "type" "multiple")] ) @@ -504,7 +501,7 @@ DONE; } [(set_attr "length" "4,4,6,6,6,6,10,8,10,10,10,6") - (set_attr "enabled_for_depr_it" "yes,yes,no,no,no,no,no,no,no,no,no,yes") + (set_attr "enabled_for_short_it" "yes,yes,no,no,no,no,no,no,no,no,no,yes") (set_attr "conds" "use") (set_attr_alternative "type" [(if_then_else (match_operand 2 "const_int_operand" "") @@ -1044,7 +1041,6 @@ ldrsb%?\\t%0, %1" [(set_attr "type" "extend,load_byte") (set_attr "predicable" "yes") - (set_attr "predicable_short_it" "no") (set_attr "pool_range" "*,4094") (set_attr "neg_pool_range" "*,250")] ) @@ -1058,7 +1054,6 @@ ldrh%?\\t%0, %1" [(set_attr "type" "extend,load_byte") (set_attr "predicable" "yes") - (set_attr "predicable_short_it" "no") (set_attr "pool_range" "*,4094") (set_attr "neg_pool_range" "*,250")] ) @@ -1072,7 +1067,6 @@ ldrb%?\\t%0, %1\\t%@ zero_extendqisi2" [(set_attr "type" "extend,load_byte") (set_attr "predicable" "yes") - (set_attr "predicable_short_it" "no") (set_attr "pool_range" "*,4094") (set_attr "neg_pool_range" "*,250")] ) @@ -1132,7 +1126,7 @@ ; we adapt the length accordingly. (set (attr "length") (if_then_else (match_test "TARGET_HARD_FLOAT") - (const_int 12) + (const_int 34) (const_int 8))) ; We do not support predicate execution of returns from cmse_nonsecure_entry ; functions because we need to clear the APSR. Since predicable has to be @@ -1538,7 +1532,6 @@ "TARGET_THUMB2" "orn%?\\t%0, %1, %2" [(set_attr "predicable" "yes") - (set_attr "predicable_short_it" "no") (set_attr "type" "logic_reg")] ) @@ -1551,7 +1544,6 @@ "TARGET_THUMB2" "orn%?\\t%0, %1, %2%S4" [(set_attr "predicable" "yes") - (set_attr "predicable_short_it" "no") (set_attr "shift" "2") (set_attr "type" "alu_shift_imm")] ) diff --git a/gcc/config/arm/vfp.md b/gcc/config/arm/vfp.md index a541413c263..075a938d22e 100644 --- a/gcc/config/arm/vfp.md +++ b/gcc/config/arm/vfp.md @@ -612,7 +612,6 @@ } " [(set_attr "predicable" "yes") - (set_attr "predicable_short_it" "no") (set_attr "type" "f_mcr,f_mrc,fconsts,f_loads,f_stores,load_4,store_4,fmov,mov_reg") (set_attr "pool_range" "*,*,*,1018,*,4090,*,*,*") @@ -824,7 +823,6 @@ "TARGET_32BIT && TARGET_HARD_FLOAT" "vabs%?.f32\\t%0, %1" [(set_attr "predicable" "yes") - (set_attr "predicable_short_it" "no") (set_attr "type" "ffariths")] ) @@ -834,7 +832,6 @@ "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE" "vabs%?.f64\\t%P0, %P1" [(set_attr "predicable" "yes") - (set_attr "predicable_short_it" "no") (set_attr "type" "ffarithd")] ) @@ -846,7 +843,6 @@ vneg%?.f32\\t%0, %1 eor%?\\t%0, %1, #-2147483648" [(set_attr "predicable" "yes") - (set_attr "predicable_short_it" "no") (set_attr "type" "ffariths")] ) @@ -892,7 +888,6 @@ } " [(set_attr "predicable" "yes") - (set_attr "predicable_short_it" "no") (set_attr "length" "4,4,8") (set_attr "type" "ffarithd")] ) @@ -961,7 +956,6 @@ "TARGET_32BIT && TARGET_HARD_FLOAT" "vadd%?.f32\\t%0, %1, %2" [(set_attr "predicable" "yes") - (set_attr "predicable_short_it" "no") (set_attr "type" "fadds")] ) @@ -972,7 +966,6 @@ "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE" "vadd%?.f64\\t%P0, %P1, %P2" [(set_attr "predicable" "yes") - (set_attr "predicable_short_it" "no") (set_attr "type" "faddd")] ) @@ -995,7 +988,6 @@ "TARGET_32BIT && TARGET_HARD_FLOAT" "vsub%?.f32\\t%0, %1, %2" [(set_attr "predicable" "yes") - (set_attr "predicable_short_it" "no") (set_attr "type" "fadds")] ) @@ -1006,7 +998,6 @@ "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE" "vsub%?.f64\\t%P0, %P1, %P2" [(set_attr "predicable" "yes") - (set_attr "predicable_short_it" "no") (set_attr "type" "faddd")] ) @@ -1036,7 +1027,6 @@ "TARGET_32BIT && TARGET_HARD_FLOAT" "vdiv%?.f32\\t%0, %1, %2" [(set_attr "predicable" "yes") - (set_attr "predicable_short_it" "no") (set_attr "arch" "*,armv6_or_vfpv3") (set_attr "type" "fdivs")] ) @@ -1048,7 +1038,6 @@ "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE" "vdiv%?.f64\\t%P0, %P1, %P2" [(set_attr "predicable" "yes") - (set_attr "predicable_short_it" "no") (set_attr "arch" "*,armv6_or_vfpv3") (set_attr "type" "fdivd")] ) @@ -1074,7 +1063,6 @@ "TARGET_32BIT && TARGET_HARD_FLOAT" "vmul%?.f32\\t%0, %1, %2" [(set_attr "predicable" "yes") - (set_attr "predicable_short_it" "no") (set_attr "type" "fmuls")] ) @@ -1085,7 +1073,6 @@ "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE" "vmul%?.f64\\t%P0, %P1, %P2" [(set_attr "predicable" "yes") - (set_attr "predicable_short_it" "no") (set_attr "type" "fmuld")] ) @@ -1116,7 +1103,6 @@ "TARGET_32BIT && TARGET_HARD_FLOAT && !flag_rounding_math" "vnmul%?.f32\\t%0, %1, %2" [(set_attr "predicable" "yes") - (set_attr "predicable_short_it" "no") (set_attr "type" "fmuls")] ) @@ -1127,7 +1113,6 @@ "TARGET_32BIT && TARGET_HARD_FLOAT" "vnmul%?.f32\\t%0, %1, %2" [(set_attr "predicable" "yes") - (set_attr "predicable_short_it" "no") (set_attr "type" "fmuls")] ) @@ -1139,7 +1124,6 @@ && !flag_rounding_math" "vnmul%?.f64\\t%P0, %P1, %P2" [(set_attr "predicable" "yes") - (set_attr "predicable_short_it" "no") (set_attr "type" "fmuld")] ) @@ -1150,7 +1134,6 @@ "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE" "vnmul%?.f64\\t%P0, %P1, %P2" [(set_attr "predicable" "yes") - (set_attr "predicable_short_it" "no") (set_attr "type" "fmuld")] ) @@ -1178,7 +1161,6 @@ "TARGET_32BIT && TARGET_HARD_FLOAT" "vmla%?.f32\\t%0, %2, %3" [(set_attr "predicable" "yes") - (set_attr "predicable_short_it" "no") (set_attr "type" "fmacs")] ) @@ -1190,7 +1172,6 @@ "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE" "vmla%?.f64\\t%P0, %P2, %P3" [(set_attr "predicable" "yes") - (set_attr "predicable_short_it" "no") (set_attr "type" "fmacd")] ) @@ -1214,7 +1195,6 @@ "TARGET_32BIT && TARGET_HARD_FLOAT" "vnmls%?.f32\\t%0, %2, %3" [(set_attr "predicable" "yes") - (set_attr "predicable_short_it" "no") (set_attr "type" "fmacs")] ) @@ -1226,7 +1206,6 @@ "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE" "vnmls%?.f64\\t%P0, %P2, %P3" [(set_attr "predicable" "yes") - (set_attr "predicable_short_it" "no") (set_attr "type" "fmacd")] ) @@ -1250,7 +1229,6 @@ "TARGET_32BIT && TARGET_HARD_FLOAT" "vmls%?.f32\\t%0, %2, %3" [(set_attr "predicable" "yes") - (set_attr "predicable_short_it" "no") (set_attr "type" "fmacs")] ) @@ -1262,7 +1240,6 @@ "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE" "vmls%?.f64\\t%P0, %P2, %P3" [(set_attr "predicable" "yes") - (set_attr "predicable_short_it" "no") (set_attr "type" "fmacd")] ) @@ -1289,7 +1266,6 @@ "TARGET_32BIT && TARGET_HARD_FLOAT" "vnmla%?.f32\\t%0, %2, %3" [(set_attr "predicable" "yes") - (set_attr "predicable_short_it" "no") (set_attr "type" "fmacs")] ) @@ -1302,7 +1278,6 @@ "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE" "vnmla%?.f64\\t%P0, %P2, %P3" [(set_attr "predicable" "yes") - (set_attr "predicable_short_it" "no") (set_attr "type" "fmacd")] ) @@ -1340,7 +1315,6 @@ "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_FMA" "vfma%?.<V_if_elem>\\t%<V_reg>0, %<V_reg>1, %<V_reg>2" [(set_attr "predicable" "yes") - (set_attr "predicable_short_it" "no") (set_attr "type" "ffma<vfp_type>")] ) @@ -1377,7 +1351,6 @@ "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_FMA" "vfms%?.<V_if_elem>\\t%<V_reg>0, %<V_reg>1, %<V_reg>2" [(set_attr "predicable" "yes") - (set_attr "predicable_short_it" "no") (set_attr "type" "ffma<vfp_type>")] ) @@ -1400,7 +1373,6 @@ "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_FMA" "vfnms%?.<V_if_elem>\\t%<V_reg>0, %<V_reg>1, %<V_reg>2" [(set_attr "predicable" "yes") - (set_attr "predicable_short_it" "no") (set_attr "type" "ffma<vfp_type>")] ) @@ -1424,7 +1396,6 @@ "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_FMA" "vfnma%?.<V_if_elem>\\t%<V_reg>0, %<V_reg>1, %<V_reg>2" [(set_attr "predicable" "yes") - (set_attr "predicable_short_it" "no") (set_attr "type" "ffma<vfp_type>")] ) @@ -1437,7 +1408,6 @@ "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE" "vcvt%?.f64.f32\\t%P0, %1" [(set_attr "predicable" "yes") - (set_attr "predicable_short_it" "no") (set_attr "type" "f_cvt")] ) @@ -1447,7 +1417,6 @@ "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE" "vcvt%?.f32.f64\\t%0, %P1" [(set_attr "predicable" "yes") - (set_attr "predicable_short_it" "no") (set_attr "type" "f_cvt")] ) @@ -1457,7 +1426,6 @@ "TARGET_32BIT && TARGET_HARD_FLOAT && (TARGET_FP16 || TARGET_VFP_FP16INST)" "vcvtb%?.f32.f16\\t%0, %1" [(set_attr "predicable" "yes") - (set_attr "predicable_short_it" "no") (set_attr "type" "f_cvt")] ) @@ -1467,7 +1435,6 @@ "TARGET_32BIT && TARGET_FP16_TO_DOUBLE" "vcvtb%?.f16.f64\\t%0, %P1" [(set_attr "predicable" "yes") - (set_attr "predicable_short_it" "no") (set_attr "type" "f_cvt")] ) @@ -1477,7 +1444,6 @@ "TARGET_32BIT && TARGET_FP16_TO_DOUBLE" "vcvtb%?.f64.f16\\t%P0, %1" [(set_attr "predicable" "yes") - (set_attr "predicable_short_it" "no") (set_attr "type" "f_cvt")] ) @@ -1487,7 +1453,6 @@ "TARGET_32BIT && TARGET_HARD_FLOAT && (TARGET_FP16 || TARGET_VFP_FP16INST)" "vcvtb%?.f16.f32\\t%0, %1" [(set_attr "predicable" "yes") - (set_attr "predicable_short_it" "no") (set_attr "type" "f_cvt")] ) @@ -1497,7 +1462,6 @@ "TARGET_32BIT && TARGET_HARD_FLOAT" "vcvt%?.s32.f32\\t%0, %1" [(set_attr "predicable" "yes") - (set_attr "predicable_short_it" "no") (set_attr "type" "f_cvtf2i")] ) @@ -1507,7 +1471,6 @@ "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE" "vcvt%?.s32.f64\\t%0, %P1" [(set_attr "predicable" "yes") - (set_attr "predicable_short_it" "no") (set_attr "type" "f_cvtf2i")] ) @@ -1518,7 +1481,6 @@ "TARGET_32BIT && TARGET_HARD_FLOAT" "vcvt%?.u32.f32\\t%0, %1" [(set_attr "predicable" "yes") - (set_attr "predicable_short_it" "no") (set_attr "type" "f_cvtf2i")] ) @@ -1528,7 +1490,6 @@ "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE" "vcvt%?.u32.f64\\t%0, %P1" [(set_attr "predicable" "yes") - (set_attr "predicable_short_it" "no") (set_attr "type" "f_cvtf2i")] ) @@ -1539,7 +1500,6 @@ "TARGET_32BIT && TARGET_HARD_FLOAT" "vcvt%?.f32.s32\\t%0, %1" [(set_attr "predicable" "yes") - (set_attr "predicable_short_it" "no") (set_attr "type" "f_cvti2f")] ) @@ -1549,7 +1509,6 @@ "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE" "vcvt%?.f64.s32\\t%P0, %1" [(set_attr "predicable" "yes") - (set_attr "predicable_short_it" "no") (set_attr "type" "f_cvti2f")] ) @@ -1560,7 +1519,6 @@ "TARGET_32BIT && TARGET_HARD_FLOAT" "vcvt%?.f32.u32\\t%0, %1" [(set_attr "predicable" "yes") - (set_attr "predicable_short_it" "no") (set_attr "type" "f_cvti2f")] ) @@ -1570,7 +1528,6 @@ "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE" "vcvt%?.f64.u32\\t%P0, %1" [(set_attr "predicable" "yes") - (set_attr "predicable_short_it" "no") (set_attr "type" "f_cvti2f")] ) @@ -1607,7 +1564,6 @@ "TARGET_32BIT && TARGET_HARD_FLOAT" "vsqrt%?.f32\\t%0, %1" [(set_attr "predicable" "yes") - (set_attr "predicable_short_it" "no") (set_attr "arch" "*,armv6_or_vfpv3") (set_attr "type" "fsqrts")] ) @@ -1618,7 +1574,6 @@ "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE" "vsqrt%?.f64\\t%P0, %P1" [(set_attr "predicable" "yes") - (set_attr "predicable_short_it" "no") (set_attr "arch" "*,armv6_or_vfpv3") (set_attr "type" "fsqrtd")] ) @@ -1710,7 +1665,6 @@ vcmp%?.f32\\t%0, %1 vcmp%?.f32\\t%0, #0" [(set_attr "predicable" "yes") - (set_attr "predicable_short_it" "no") (set_attr "type" "fcmps")] ) @@ -1723,7 +1677,6 @@ vcmpe%?.f32\\t%0, %1 vcmpe%?.f32\\t%0, #0" [(set_attr "predicable" "yes") - (set_attr "predicable_short_it" "no") (set_attr "type" "fcmps")] ) @@ -1736,7 +1689,6 @@ vcmp%?.f64\\t%P0, %P1 vcmp%?.f64\\t%P0, #0" [(set_attr "predicable" "yes") - (set_attr "predicable_short_it" "no") (set_attr "type" "fcmpd")] ) @@ -1749,7 +1701,6 @@ vcmpe%?.f64\\t%P0, %P1 vcmpe%?.f64\\t%P0, #0" [(set_attr "predicable" "yes") - (set_attr "predicable_short_it" "no") (set_attr "type" "fcmpd")] ) @@ -1762,7 +1713,6 @@ "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP3 && !flag_rounding_math" "vcvt%?.f32.<FCVTI32typename>\\t%0, %1, %v2" [(set_attr "predicable" "yes") - (set_attr "predicable_short_it" "no") (set_attr "type" "f_cvti2f")] ) @@ -1781,7 +1731,6 @@ vmov%?.f64\\t%P0, %1, %1\;vcvt%?.f64.<FCVTI32typename>\\t%P0, %P0, %v2" [(set_attr "predicable" "yes") (set_attr "ce_count" "2") - (set_attr "predicable_short_it" "no") (set_attr "type" "f_cvti2f") (set_attr "length" "8")] ) @@ -1794,7 +1743,6 @@ "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP3 && !flag_rounding_math" "vcvt%?.s32.f32\\t%0, %1, %v2" [(set_attr "predicable" "yes") - (set_attr "predicable_short_it" "no") (set_attr "type" "f_cvtf2i")] ) @@ -1940,7 +1888,6 @@ "TARGET_HARD_FLOAT && TARGET_VFP5 <vfp_double_cond>" "vrint<vrint_variant>%?.<V_if_elem>\\t%<V_reg>0, %<V_reg>1" [(set_attr "predicable" "<vrint_predicable>") - (set_attr "predicable_short_it" "no") (set_attr "type" "f_rint<vfp_type>") (set_attr "conds" "<vrint_conds>")] ) @@ -1953,8 +1900,7 @@ "register_operand" "<F_constraint>")] VCVT)))] "TARGET_HARD_FLOAT && TARGET_VFP5 <vfp_double_cond>" "vcvt<vrint_variant>.<su>32.<V_if_elem>\\t%0, %<V_reg>1" - [(set_attr "predicable" "no") - (set_attr "conds" "unconditional") + [(set_attr "conds" "unconditional") (set_attr "type" "f_cvtf2i")] ) diff --git a/gcc/config/arm/xgene1.md b/gcc/config/arm/xgene1.md index c4b377354db..cf0694a5cc7 100644 --- a/gcc/config/arm/xgene1.md +++ b/gcc/config/arm/xgene1.md @@ -20,17 +20,26 @@ ;; Pipeline description for the xgene1 micro-architecture -(define_automaton "xgene1") +(define_automaton "xgene1_main, xgene1_decoder, xgene1_div, xgene1_simd") -(define_cpu_unit "xgene1_decode_out0" "xgene1") -(define_cpu_unit "xgene1_decode_out1" "xgene1") -(define_cpu_unit "xgene1_decode_out2" "xgene1") -(define_cpu_unit "xgene1_decode_out3" "xgene1") +(define_cpu_unit "xgene1_decode_out0" "xgene1_decoder") +(define_cpu_unit "xgene1_decode_out1" "xgene1_decoder") +(define_cpu_unit "xgene1_decode_out2" "xgene1_decoder") +(define_cpu_unit "xgene1_decode_out3" "xgene1_decoder") -(define_cpu_unit "xgene1_divide" "xgene1") -(define_cpu_unit "xgene1_fp_divide" "xgene1") -(define_cpu_unit "xgene1_fsu" "xgene1") -(define_cpu_unit "xgene1_fcmp" "xgene1") +(define_cpu_unit "xgene1_IXA" "xgene1_main") +(define_cpu_unit "xgene1_IXB" "xgene1_main") +(define_cpu_unit "xgene1_IXB_compl" "xgene1_main") + +(define_reservation "xgene1_IXn" "(xgene1_IXA | xgene1_IXB)") + +(define_cpu_unit "xgene1_multiply" "xgene1_main") +(define_cpu_unit "xgene1_divide" "xgene1_div") +(define_cpu_unit "xgene1_fp_divide" "xgene1_div") +(define_cpu_unit "xgene1_fsu" "xgene1_simd") +(define_cpu_unit "xgene1_fcmp" "xgene1_simd") +(define_cpu_unit "xgene1_ld" "xgene1_main") +(define_cpu_unit "xgene1_st" "xgene1_main") (define_reservation "xgene1_decode1op" "( xgene1_decode_out0 ) @@ -68,12 +77,12 @@ (define_insn_reservation "xgene1_f_load" 10 (and (eq_attr "tune" "xgene1") (eq_attr "type" "f_loadd,f_loads")) - "xgene1_decode2op") + "xgene1_decode2op, xgene1_ld") (define_insn_reservation "xgene1_f_store" 4 (and (eq_attr "tune" "xgene1") (eq_attr "type" "f_stored,f_stores")) - "xgene1_decode2op") + "xgene1_decode2op, xgene1_st") (define_insn_reservation "xgene1_fmov" 2 (and (eq_attr "tune" "xgene1") @@ -92,85 +101,108 @@ (define_insn_reservation "xgene1_load_pair" 6 (and (eq_attr "tune" "xgene1") - (eq_attr "type" "load_8, load_16")) - "xgene1_decodeIsolated") + (eq_attr "type" "load_16")) + "xgene1_decodeIsolated, xgene1_ld*2") (define_insn_reservation "xgene1_store_pair" 2 (and (eq_attr "tune" "xgene1") - (eq_attr "type" "store_8, store_16")) - "xgene1_decodeIsolated") + (eq_attr "type" "store_16")) + "xgene1_decodeIsolated, xgene1_st*2") (define_insn_reservation "xgene1_fp_load1" 10 (and (eq_attr "tune" "xgene1") - (eq_attr "type" "load_4") + (eq_attr "type" "load_4, load_8") (eq_attr "fp" "yes")) - "xgene1_decode1op") + "xgene1_decode1op, xgene1_ld") (define_insn_reservation "xgene1_load1" 5 (and (eq_attr "tune" "xgene1") - (eq_attr "type" "load_4")) - "xgene1_decode1op") + (eq_attr "type" "load_4, load_8")) + "xgene1_decode1op, xgene1_ld") -(define_insn_reservation "xgene1_store1" 2 +(define_insn_reservation "xgene1_store1" 1 (and (eq_attr "tune" "xgene1") - (eq_attr "type" "store_4")) - "xgene1_decode2op") + (eq_attr "type" "store_4, store_8")) + "xgene1_decode1op, xgene1_st") (define_insn_reservation "xgene1_move" 1 (and (eq_attr "tune" "xgene1") (eq_attr "type" "mov_reg,mov_imm,mrs")) - "xgene1_decode1op") + "xgene1_decode1op, xgene1_IXn") + +(define_insn_reservation "xgene1_alu_cond" 1 + (and (eq_attr "tune" "xgene1") + (eq_attr "type" "csel")) + "xgene1_decode1op, xgene1_IXn") (define_insn_reservation "xgene1_alu" 1 (and (eq_attr "tune" "xgene1") (eq_attr "type" "alu_imm,alu_sreg,alu_shift_imm,\ - alu_ext,adc_reg,csel,logic_imm,\ + alu_ext,adc_reg,logic_imm,\ logic_reg,logic_shift_imm,clz,\ - rbit,shift_reg,adr,mov_reg,\ - mov_imm,extend")) - "xgene1_decode1op") + rbit,adr,mov_reg,shift_imm,\ + mov_imm,extend,multiple")) + "xgene1_decode1op, xgene1_IXn") + +(define_insn_reservation "xgene1_shift_rotate" 2 + (and (eq_attr "tune" "xgene1") + (eq_attr "type" "shift_reg")) + "xgene1_decode1op, xgene1_IXB, xgene1_IXB_compl") -(define_insn_reservation "xgene1_simd" 1 +(define_insn_reservation "xgene1_simd" 2 (and (eq_attr "tune" "xgene1") (eq_attr "type" "rev")) - "xgene1_decode1op") + "xgene1_decode1op, xgene1_IXB, xgene1_IXB_compl") (define_insn_reservation "xgene1_alus" 1 (and (eq_attr "tune" "xgene1") - (eq_attr "type" "alus_imm,alu_sreg,alus_shift_imm,\ + (eq_attr "type" "alus_imm,alus_sreg,alus_shift_imm,\ alus_ext,logics_imm,logics_reg,\ logics_shift_imm")) - "xgene1_decode1op") + "xgene1_decode1op, xgene1_IXB, xgene1_IXB_compl") + +(define_bypass 2 "xgene1_alus" + "xgene1_alu_cond, xgene1_branch") -(define_insn_reservation "xgene1_mul" 6 +(define_insn_reservation "xgene1_mul32" 4 (and (eq_attr "tune" "xgene1") - (eq_attr "type" "mul,mla,smull,umull,smlal,umlal")) - "xgene1_decode2op") + (eq_attr "mul32" "yes")) + "xgene1_decode2op, xgene1_IXB + xgene1_multiply, xgene1_multiply, nothing, xgene1_IXB_compl") + +(define_insn_reservation "xgene1_mul64" 5 + (and (eq_attr "tune" "xgene1") + (eq_attr "mul64" "yes")) + "xgene1_decode2op, xgene1_IXB + xgene1_multiply, xgene1_multiply, nothing*2, xgene1_IXB_compl") (define_insn_reservation "xgene1_div" 34 (and (eq_attr "tune" "xgene1") (eq_attr "type" "sdiv,udiv")) - "xgene1_decode1op,xgene1_divide*7") + "xgene1_decode1op, xgene1_IXB + xgene1_divide*7") (define_insn_reservation "xgene1_fcmp" 10 (and (eq_attr "tune" "xgene1") (eq_attr "type" "fcmpd,fcmps,fccmpd,fccmps")) - "xgene1_decode1op,xgene1_fsu+xgene1_fcmp*3") + "xgene1_decode1op, xgene1_fsu + xgene1_fcmp*3") (define_insn_reservation "xgene1_fcsel" 3 (and (eq_attr "tune" "xgene1") (eq_attr "type" "fcsel")) - "xgene1_decode1op,xgene1_fsu") + "xgene1_decode1op, xgene1_fsu") + +(define_insn_reservation "xgene1_bfx" 1 + (and (eq_attr "tune" "xgene1") + (eq_attr "type" "bfx")) + "xgene1_decode1op, xgene1_IXn") (define_insn_reservation "xgene1_bfm" 2 (and (eq_attr "tune" "xgene1") - (eq_attr "type" "bfm,bfx")) - "xgene1_decode1op,xgene1_fsu") + (eq_attr "type" "bfm")) + "xgene1_decode1op, xgene1_IXB, xgene1_IXB_compl") (define_insn_reservation "xgene1_f_rint" 5 (and (eq_attr "tune" "xgene1") (eq_attr "type" "f_rintd,f_rints")) - "xgene1_decode1op,xgene1_fsu") + "xgene1_decode1op, xgene1_fsu") (define_insn_reservation "xgene1_f_cvt" 3 (and (eq_attr "tune" "xgene1") @@ -225,12 +257,12 @@ (define_insn_reservation "xgene1_neon_load1" 11 (and (eq_attr "tune" "xgene1") (eq_attr "type" "neon_load1_1reg, neon_load1_1reg_q")) - "xgene1_decode2op,xgene1_fsu") + "xgene1_decode2op, xgene1_ld") (define_insn_reservation "xgene1_neon_store1" 5 (and (eq_attr "tune" "xgene1") (eq_attr "type" "neon_store1_1reg, neon_store1_1reg_q")) - "xgene1_decode2op,xgene1_fsu") + "xgene1_decode2op, xgene1_st") (define_insn_reservation "xgene1_neon_logic" 2 (and (eq_attr "tune" "xgene1") @@ -300,6 +332,8 @@ neon_compare_zero_q,\ neon_tst,\ neon_tst_q,\ + neon_minmax,\ + neon_minmax_q,\ ")) "xgene1_decode1op,xgene1_fsu") @@ -439,8 +473,10 @@ (and (eq_attr "tune" "xgene1") (eq_attr "type" "neon_store1_one_lane,\ neon_store1_one_lane_q,\ + neon_stp,\ + neon_stp_q,\ ")) - "xgene1_decode1op") + "xgene1_decodeIsolated, xgene1_st") (define_insn_reservation "xgene1_neon_halve_narrow" 6 (and (eq_attr "tune" "xgene1") @@ -499,7 +535,7 @@ (and (eq_attr "tune" "xgene1") (eq_attr "type" "neon_load1_all_lanes,\ ")) - "xgene1_decode1op") + "xgene1_decode1op, xgene1_ld") (define_insn_reservation "xgene1_neon_fp_recp" 3 (and (eq_attr "tune" "xgene1") |