diff options
Diffstat (limited to 'gcc/config/arm/fpa.md')
| -rw-r--r-- | gcc/config/arm/fpa.md | 242 |
1 files changed, 191 insertions, 51 deletions
diff --git a/gcc/config/arm/fpa.md b/gcc/config/arm/fpa.md index b801f5a5391..d821a507ebd 100644 --- a/gcc/config/arm/fpa.md +++ b/gcc/config/arm/fpa.md @@ -1,6 +1,6 @@ ;;- Machine description for FPA co-processor for ARM cpus. ;; Copyright 1991, 1993, 1994, 1995, 1996, 1996, 1997, 1998, 1999, 2000, -;; 2001, 2002, 2003, 2004, 2005 Free Software Foundation, Inc. +;; 2001, 2002, 2003, 2004, 2005, 2007 Free Software Foundation, Inc. ;; Contributed by Pieter `Tiggr' Schoenmakers (rcpieter@win.tue.nl) ;; and Martin Simmons (@harleqn.co.uk). ;; More major hacks by Richard Earnshaw (rearnsha@arm.com). @@ -22,6 +22,10 @@ ;; the Free Software Foundation, 51 Franklin Street, Fifth Floor, ;; Boston, MA 02110-1301, USA. +;; Some FPA mnemonics are ambiguous between conditional infixes and +;; conditional suffixes. All instructions use a conditional infix, +;; even in unified assembly mode. + ;; FPA automaton. (define_automaton "armfp") @@ -101,7 +105,7 @@ [(set (match_operand:SF 0 "s_register_operand" "=f,f") (plus:SF (match_operand:SF 1 "s_register_operand" "%f,f") (match_operand:SF 2 "arm_float_add_operand" "fG,H")))] - "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_FPA" + "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_FPA" "@ adf%?s\\t%0, %1, %2 suf%?s\\t%0, %1, #%N2" @@ -113,7 +117,7 @@ [(set (match_operand:DF 0 "s_register_operand" "=f,f") (plus:DF (match_operand:DF 1 "s_register_operand" "%f,f") (match_operand:DF 2 "arm_float_add_operand" "fG,H")))] - "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_FPA" + "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_FPA" "@ adf%?d\\t%0, %1, %2 suf%?d\\t%0, %1, #%N2" @@ -126,7 +130,7 @@ (plus:DF (float_extend:DF (match_operand:SF 1 "s_register_operand" "f,f")) (match_operand:DF 2 "arm_float_add_operand" "fG,H")))] - "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_FPA" + "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_FPA" "@ adf%?d\\t%0, %1, %2 suf%?d\\t%0, %1, #%N2" @@ -139,7 +143,7 @@ (plus:DF (match_operand:DF 1 "s_register_operand" "f") (float_extend:DF (match_operand:SF 2 "s_register_operand" "f"))))] - "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_FPA" + "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_FPA" "adf%?d\\t%0, %1, %2" [(set_attr "type" "farith") (set_attr "predicable" "yes")] @@ -151,7 +155,7 @@ (match_operand:SF 1 "s_register_operand" "f")) (float_extend:DF (match_operand:SF 2 "s_register_operand" "f"))))] - "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_FPA" + "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_FPA" "adf%?d\\t%0, %1, %2" [(set_attr "type" "farith") (set_attr "predicable" "yes")] @@ -161,7 +165,7 @@ [(set (match_operand:SF 0 "s_register_operand" "=f,f") (minus:SF (match_operand:SF 1 "arm_float_rhs_operand" "f,G") (match_operand:SF 2 "arm_float_rhs_operand" "fG,f")))] - "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_FPA" + "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_FPA" "@ suf%?s\\t%0, %1, %2 rsf%?s\\t%0, %2, %1" @@ -172,7 +176,7 @@ [(set (match_operand:DF 0 "s_register_operand" "=f,f") (minus:DF (match_operand:DF 1 "arm_float_rhs_operand" "f,G") (match_operand:DF 2 "arm_float_rhs_operand" "fG,f")))] - "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_FPA" + "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_FPA" "@ suf%?d\\t%0, %1, %2 rsf%?d\\t%0, %2, %1" @@ -185,7 +189,7 @@ (minus:DF (float_extend:DF (match_operand:SF 1 "s_register_operand" "f")) (match_operand:DF 2 "arm_float_rhs_operand" "fG")))] - "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_FPA" + "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_FPA" "suf%?d\\t%0, %1, %2" [(set_attr "type" "farith") (set_attr "predicable" "yes")] @@ -196,7 +200,7 @@ (minus:DF (match_operand:DF 1 "arm_float_rhs_operand" "f,G") (float_extend:DF (match_operand:SF 2 "s_register_operand" "f,f"))))] - "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_FPA" + "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_FPA" "@ suf%?d\\t%0, %1, %2 rsf%?d\\t%0, %2, %1" @@ -210,7 +214,7 @@ (match_operand:SF 1 "s_register_operand" "f")) (float_extend:DF (match_operand:SF 2 "s_register_operand" "f"))))] - "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_FPA" + "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_FPA" "suf%?d\\t%0, %1, %2" [(set_attr "type" "farith") (set_attr "predicable" "yes")] @@ -220,7 +224,7 @@ [(set (match_operand:SF 0 "s_register_operand" "=f") (mult:SF (match_operand:SF 1 "s_register_operand" "f") (match_operand:SF 2 "arm_float_rhs_operand" "fG")))] - "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_FPA" + "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_FPA" "fml%?s\\t%0, %1, %2" [(set_attr "type" "ffmul") (set_attr "predicable" "yes")] @@ -230,7 +234,7 @@ [(set (match_operand:DF 0 "s_register_operand" "=f") (mult:DF (match_operand:DF 1 "s_register_operand" "f") (match_operand:DF 2 "arm_float_rhs_operand" "fG")))] - "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_FPA" + "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_FPA" "muf%?d\\t%0, %1, %2" [(set_attr "type" "fmul") (set_attr "predicable" "yes")] @@ -241,7 +245,7 @@ (mult:DF (float_extend:DF (match_operand:SF 1 "s_register_operand" "f")) (match_operand:DF 2 "arm_float_rhs_operand" "fG")))] - "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_FPA" + "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_FPA" "muf%?d\\t%0, %1, %2" [(set_attr "type" "fmul") (set_attr "predicable" "yes")] @@ -252,7 +256,7 @@ (mult:DF (match_operand:DF 1 "s_register_operand" "f") (float_extend:DF (match_operand:SF 2 "s_register_operand" "f"))))] - "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_FPA" + "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_FPA" "muf%?d\\t%0, %1, %2" [(set_attr "type" "fmul") (set_attr "predicable" "yes")] @@ -263,7 +267,7 @@ (mult:DF (float_extend:DF (match_operand:SF 1 "s_register_operand" "f")) (float_extend:DF (match_operand:SF 2 "s_register_operand" "f"))))] - "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_FPA" + "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_FPA" "muf%?d\\t%0, %1, %2" [(set_attr "type" "fmul") (set_attr "predicable" "yes")] @@ -275,7 +279,7 @@ [(set (match_operand:SF 0 "s_register_operand" "=f,f") (div:SF (match_operand:SF 1 "arm_float_rhs_operand" "f,G") (match_operand:SF 2 "arm_float_rhs_operand" "fG,f")))] - "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_FPA" + "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_FPA" "@ fdv%?s\\t%0, %1, %2 frd%?s\\t%0, %2, %1" @@ -287,7 +291,7 @@ [(set (match_operand:DF 0 "s_register_operand" "=f,f") (div:DF (match_operand:DF 1 "arm_float_rhs_operand" "f,G") (match_operand:DF 2 "arm_float_rhs_operand" "fG,f")))] - "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_FPA" + "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_FPA" "@ dvf%?d\\t%0, %1, %2 rdf%?d\\t%0, %2, %1" @@ -300,7 +304,7 @@ (div:DF (float_extend:DF (match_operand:SF 1 "s_register_operand" "f")) (match_operand:DF 2 "arm_float_rhs_operand" "fG")))] - "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_FPA" + "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_FPA" "dvf%?d\\t%0, %1, %2" [(set_attr "type" "fdivd") (set_attr "predicable" "yes")] @@ -311,7 +315,7 @@ (div:DF (match_operand:DF 1 "arm_float_rhs_operand" "fG") (float_extend:DF (match_operand:SF 2 "s_register_operand" "f"))))] - "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_FPA" + "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_FPA" "rdf%?d\\t%0, %2, %1" [(set_attr "type" "fdivd") (set_attr "predicable" "yes")] @@ -323,7 +327,7 @@ (match_operand:SF 1 "s_register_operand" "f")) (float_extend:DF (match_operand:SF 2 "s_register_operand" "f"))))] - "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_FPA" + "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_FPA" "dvf%?d\\t%0, %1, %2" [(set_attr "type" "fdivd") (set_attr "predicable" "yes")] @@ -333,7 +337,7 @@ [(set (match_operand:SF 0 "s_register_operand" "=f") (mod:SF (match_operand:SF 1 "s_register_operand" "f") (match_operand:SF 2 "arm_float_rhs_operand" "fG")))] - "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_FPA" + "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_FPA" "rmf%?s\\t%0, %1, %2" [(set_attr "type" "fdivs") (set_attr "predicable" "yes")] @@ -343,7 +347,7 @@ [(set (match_operand:DF 0 "s_register_operand" "=f") (mod:DF (match_operand:DF 1 "s_register_operand" "f") (match_operand:DF 2 "arm_float_rhs_operand" "fG")))] - "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_FPA" + "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_FPA" "rmf%?d\\t%0, %1, %2" [(set_attr "type" "fdivd") (set_attr "predicable" "yes")] @@ -354,7 +358,7 @@ (mod:DF (float_extend:DF (match_operand:SF 1 "s_register_operand" "f")) (match_operand:DF 2 "arm_float_rhs_operand" "fG")))] - "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_FPA" + "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_FPA" "rmf%?d\\t%0, %1, %2" [(set_attr "type" "fdivd") (set_attr "predicable" "yes")] @@ -365,7 +369,7 @@ (mod:DF (match_operand:DF 1 "s_register_operand" "f") (float_extend:DF (match_operand:SF 2 "s_register_operand" "f"))))] - "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_FPA" + "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_FPA" "rmf%?d\\t%0, %1, %2" [(set_attr "type" "fdivd") (set_attr "predicable" "yes")] @@ -377,7 +381,7 @@ (match_operand:SF 1 "s_register_operand" "f")) (float_extend:DF (match_operand:SF 2 "s_register_operand" "f"))))] - "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_FPA" + "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_FPA" "rmf%?d\\t%0, %1, %2" [(set_attr "type" "fdivd") (set_attr "predicable" "yes")] @@ -386,7 +390,7 @@ (define_insn "*negsf2_fpa" [(set (match_operand:SF 0 "s_register_operand" "=f") (neg:SF (match_operand:SF 1 "s_register_operand" "f")))] - "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_FPA" + "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_FPA" "mnf%?s\\t%0, %1" [(set_attr "type" "ffarith") (set_attr "predicable" "yes")] @@ -395,7 +399,7 @@ (define_insn "*negdf2_fpa" [(set (match_operand:DF 0 "s_register_operand" "=f") (neg:DF (match_operand:DF 1 "s_register_operand" "f")))] - "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_FPA" + "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_FPA" "mnf%?d\\t%0, %1" [(set_attr "type" "ffarith") (set_attr "predicable" "yes")] @@ -405,7 +409,7 @@ [(set (match_operand:DF 0 "s_register_operand" "=f") (neg:DF (float_extend:DF (match_operand:SF 1 "s_register_operand" "f"))))] - "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_FPA" + "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_FPA" "mnf%?d\\t%0, %1" [(set_attr "type" "ffarith") (set_attr "predicable" "yes")] @@ -414,7 +418,7 @@ (define_insn "*abssf2_fpa" [(set (match_operand:SF 0 "s_register_operand" "=f") (abs:SF (match_operand:SF 1 "s_register_operand" "f")))] - "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_FPA" + "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_FPA" "abs%?s\\t%0, %1" [(set_attr "type" "ffarith") (set_attr "predicable" "yes")] @@ -423,7 +427,7 @@ (define_insn "*absdf2_fpa" [(set (match_operand:DF 0 "s_register_operand" "=f") (abs:DF (match_operand:DF 1 "s_register_operand" "f")))] - "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_FPA" + "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_FPA" "abs%?d\\t%0, %1" [(set_attr "type" "ffarith") (set_attr "predicable" "yes")] @@ -433,7 +437,7 @@ [(set (match_operand:DF 0 "s_register_operand" "=f") (abs:DF (float_extend:DF (match_operand:SF 1 "s_register_operand" "f"))))] - "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_FPA" + "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_FPA" "abs%?d\\t%0, %1" [(set_attr "type" "ffarith") (set_attr "predicable" "yes")] @@ -442,7 +446,7 @@ (define_insn "*sqrtsf2_fpa" [(set (match_operand:SF 0 "s_register_operand" "=f") (sqrt:SF (match_operand:SF 1 "s_register_operand" "f")))] - "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_FPA" + "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_FPA" "sqt%?s\\t%0, %1" [(set_attr "type" "float_em") (set_attr "predicable" "yes")] @@ -451,7 +455,7 @@ (define_insn "*sqrtdf2_fpa" [(set (match_operand:DF 0 "s_register_operand" "=f") (sqrt:DF (match_operand:DF 1 "s_register_operand" "f")))] - "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_FPA" + "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_FPA" "sqt%?d\\t%0, %1" [(set_attr "type" "float_em") (set_attr "predicable" "yes")] @@ -461,7 +465,7 @@ [(set (match_operand:DF 0 "s_register_operand" "=f") (sqrt:DF (float_extend:DF (match_operand:SF 1 "s_register_operand" "f"))))] - "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_FPA" + "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_FPA" "sqt%?d\\t%0, %1" [(set_attr "type" "float_em") (set_attr "predicable" "yes")] @@ -470,7 +474,7 @@ (define_insn "*floatsisf2_fpa" [(set (match_operand:SF 0 "s_register_operand" "=f") (float:SF (match_operand:SI 1 "s_register_operand" "r")))] - "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_FPA" + "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_FPA" "flt%?s\\t%0, %1" [(set_attr "type" "r_2_f") (set_attr "predicable" "yes")] @@ -479,7 +483,7 @@ (define_insn "*floatsidf2_fpa" [(set (match_operand:DF 0 "s_register_operand" "=f") (float:DF (match_operand:SI 1 "s_register_operand" "r")))] - "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_FPA" + "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_FPA" "flt%?d\\t%0, %1" [(set_attr "type" "r_2_f") (set_attr "predicable" "yes")] @@ -488,7 +492,7 @@ (define_insn "*fix_truncsfsi2_fpa" [(set (match_operand:SI 0 "s_register_operand" "=r") (fix:SI (fix:SF (match_operand:SF 1 "s_register_operand" "f"))))] - "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_FPA" + "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_FPA" "fix%?z\\t%0, %1" [(set_attr "type" "f_2_r") (set_attr "predicable" "yes")] @@ -497,7 +501,7 @@ (define_insn "*fix_truncdfsi2_fpa" [(set (match_operand:SI 0 "s_register_operand" "=r") (fix:SI (fix:DF (match_operand:DF 1 "s_register_operand" "f"))))] - "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_FPA" + "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_FPA" "fix%?z\\t%0, %1" [(set_attr "type" "f_2_r") (set_attr "predicable" "yes")] @@ -507,7 +511,7 @@ [(set (match_operand:SF 0 "s_register_operand" "=f") (float_truncate:SF (match_operand:DF 1 "s_register_operand" "f")))] - "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_FPA" + "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_FPA" "mvf%?s\\t%0, %1" [(set_attr "type" "ffarith") (set_attr "predicable" "yes")] @@ -516,7 +520,7 @@ (define_insn "*extendsfdf2_fpa" [(set (match_operand:DF 0 "s_register_operand" "=f") (float_extend:DF (match_operand:SF 1 "s_register_operand" "f")))] - "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_FPA" + "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_FPA" "mvf%?d\\t%0, %1" [(set_attr "type" "ffarith") (set_attr "predicable" "yes")] @@ -561,8 +565,8 @@ switch (which_alternative) { default: - case 0: return \"ldm%?ia\\t%m1, %M0\\t%@ double\"; - case 1: return \"stm%?ia\\t%m0, %M1\\t%@ double\"; + case 0: return \"ldm%(ia%)\\t%m1, %M0\\t%@ double\"; + case 1: return \"stm%(ia%)\\t%m0, %M1\\t%@ double\"; case 2: return \"#\"; case 3: case 4: return output_move_double (operands); case 5: return \"mvf%?d\\t%0, %1\"; @@ -609,11 +613,102 @@ (set_attr "type" "ffarith,f_load,f_store")] ) +;; stfs/ldfs always use a conditional infix. This works around the +;; ambiguity between "stf pl s" and "sftp ls". +(define_insn "*thumb2_movsf_fpa" + [(set (match_operand:SF 0 "nonimmediate_operand" "=f,f,f, m,f,r,r,r, m") + (match_operand:SF 1 "general_operand" "fG,H,mE,f,r,f,r,mE,r"))] + "TARGET_THUMB2 + && TARGET_HARD_FLOAT && TARGET_FPA + && (GET_CODE (operands[0]) != MEM + || register_operand (operands[1], SFmode))" + "@ + mvf%?s\\t%0, %1 + mnf%?s\\t%0, #%N1 + ldf%?s\\t%0, %1 + stf%?s\\t%1, %0 + str%?\\t%1, [%|sp, #-4]!\;ldf%?s\\t%0, [%|sp], #4 + stf%?s\\t%1, [%|sp, #-4]!\;ldr%?\\t%0, [%|sp], #4 + mov%?\\t%0, %1 @bar + ldr%?\\t%0, %1\\t%@ float + str%?\\t%1, %0\\t%@ float" + [(set_attr "length" "4,4,4,4,8,8,4,4,4") + (set_attr "ce_count" "1,1,1,1,2,2,1,1,1") + (set_attr "predicable" "yes") + (set_attr "type" + "ffarith,ffarith,f_load,f_store,r_mem_f,f_mem_r,*,load1,store1") + (set_attr "pool_range" "*,*,1024,*,*,*,*,4096,*") + (set_attr "neg_pool_range" "*,*,1012,*,*,*,*,0,*")] +) + +;; Not predicable because we don't know the number of instructions. +(define_insn "*thumb2_movdf_fpa" + [(set (match_operand:DF 0 "nonimmediate_operand" + "=r,Q,r,m,r, f, f,f, m,!f,!r") + (match_operand:DF 1 "general_operand" + "Q, r,r,r,mF,fG,H,mF,f,r, f"))] + "TARGET_THUMB2 + && TARGET_HARD_FLOAT && TARGET_FPA + && (GET_CODE (operands[0]) != MEM + || register_operand (operands[1], DFmode))" + "* + { + switch (which_alternative) + { + default: + case 0: return \"ldm%(ia%)\\t%m1, %M0\\t%@ double\"; + case 1: return \"stm%(ia%)\\t%m0, %M1\\t%@ double\"; + case 2: case 3: case 4: return output_move_double (operands); + case 5: return \"mvf%?d\\t%0, %1\"; + case 6: return \"mnf%?d\\t%0, #%N1\"; + case 7: return \"ldf%?d\\t%0, %1\"; + case 8: return \"stf%?d\\t%1, %0\"; + case 9: return output_mov_double_fpa_from_arm (operands); + case 10: return output_mov_double_arm_from_fpa (operands); + } + } + " + [(set_attr "length" "4,4,8,8,8,4,4,4,4,8,8") + (set_attr "type" + "load1,store2,*,store2,load1,ffarith,ffarith,f_load,f_store,r_mem_f,f_mem_r") + (set_attr "pool_range" "*,*,*,*,4092,*,*,1024,*,*,*") + (set_attr "neg_pool_range" "*,*,*,*,0,*,*,1020,*,*,*")] +) + +;; Saving and restoring the floating point registers in the prologue should +;; be done in XFmode, even though we don't support that for anything else +;; (Well, strictly it's 'internal representation', but that's effectively +;; XFmode). +;; Not predicable because we don't know the number of instructions. + +(define_insn "*thumb2_movxf_fpa" + [(set (match_operand:XF 0 "nonimmediate_operand" "=f,f,f,m,f,r,r") + (match_operand:XF 1 "general_operand" "fG,H,m,f,r,f,r"))] + "TARGET_THUMB2 && TARGET_HARD_FLOAT && TARGET_FPA && reload_completed" + "* + switch (which_alternative) + { + default: + case 0: return \"mvf%?e\\t%0, %1\"; + case 1: return \"mnf%?e\\t%0, #%N1\"; + case 2: return \"ldf%?e\\t%0, %1\"; + case 3: return \"stf%?e\\t%1, %0\"; + case 4: return output_mov_long_double_fpa_from_arm (operands); + case 5: return output_mov_long_double_arm_from_fpa (operands); + case 6: return output_mov_long_double_arm_from_arm (operands); + } + " + [(set_attr "length" "4,4,4,4,8,8,12") + (set_attr "type" "ffarith,ffarith,f_load,f_store,r_mem_f,f_mem_r,*") + (set_attr "pool_range" "*,*,1024,*,*,*,*") + (set_attr "neg_pool_range" "*,*,1004,*,*,*,*")] +) + (define_insn "*cmpsf_fpa" [(set (reg:CCFP CC_REGNUM) (compare:CCFP (match_operand:SF 0 "s_register_operand" "f,f") (match_operand:SF 1 "arm_float_add_operand" "fG,H")))] - "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_FPA" + "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_FPA" "@ cmf%?\\t%0, %1 cnf%?\\t%0, #%N1" @@ -625,7 +720,7 @@ [(set (reg:CCFP CC_REGNUM) (compare:CCFP (match_operand:DF 0 "s_register_operand" "f,f") (match_operand:DF 1 "arm_float_add_operand" "fG,H")))] - "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_FPA" + "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_FPA" "@ cmf%?\\t%0, %1 cnf%?\\t%0, #%N1" @@ -638,7 +733,7 @@ (compare:CCFP (float_extend:DF (match_operand:SF 0 "s_register_operand" "f,f")) (match_operand:DF 1 "arm_float_add_operand" "fG,H")))] - "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_FPA" + "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_FPA" "@ cmf%?\\t%0, %1 cnf%?\\t%0, #%N1" @@ -651,7 +746,7 @@ (compare:CCFP (match_operand:DF 0 "s_register_operand" "f") (float_extend:DF (match_operand:SF 1 "s_register_operand" "f"))))] - "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_FPA" + "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_FPA" "cmf%?\\t%0, %1" [(set_attr "conds" "set") (set_attr "type" "f_2_r")] @@ -661,7 +756,7 @@ [(set (reg:CCFPE CC_REGNUM) (compare:CCFPE (match_operand:SF 0 "s_register_operand" "f,f") (match_operand:SF 1 "arm_float_add_operand" "fG,H")))] - "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_FPA" + "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_FPA" "@ cmf%?e\\t%0, %1 cnf%?e\\t%0, #%N1" @@ -673,7 +768,7 @@ [(set (reg:CCFPE CC_REGNUM) (compare:CCFPE (match_operand:DF 0 "s_register_operand" "f,f") (match_operand:DF 1 "arm_float_add_operand" "fG,H")))] - "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_FPA" + "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_FPA" "@ cmf%?e\\t%0, %1 cnf%?e\\t%0, #%N1" @@ -686,7 +781,7 @@ (compare:CCFPE (float_extend:DF (match_operand:SF 0 "s_register_operand" "f,f")) (match_operand:DF 1 "arm_float_add_operand" "fG,H")))] - "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_FPA" + "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_FPA" "@ cmf%?e\\t%0, %1 cnf%?e\\t%0, #%N1" @@ -699,7 +794,7 @@ (compare:CCFPE (match_operand:DF 0 "s_register_operand" "f") (float_extend:DF (match_operand:SF 1 "s_register_operand" "f"))))] - "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_FPA" + "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_FPA" "cmf%?e\\t%0, %1" [(set_attr "conds" "set") (set_attr "type" "f_2_r")] @@ -748,3 +843,48 @@ (set_attr "type" "ffarith") (set_attr "conds" "use")] ) + +(define_insn "*thumb2_movsfcc_fpa" + [(set (match_operand:SF 0 "s_register_operand" "=f,f,f,f,f,f,f,f") + (if_then_else:SF + (match_operator 3 "arm_comparison_operator" + [(match_operand 4 "cc_register" "") (const_int 0)]) + (match_operand:SF 1 "arm_float_add_operand" "0,0,fG,H,fG,fG,H,H") + (match_operand:SF 2 "arm_float_add_operand" "fG,H,0,0,fG,H,fG,H")))] + "TARGET_THUMB2 && TARGET_HARD_FLOAT && TARGET_FPA" + "@ + it\\t%D3\;mvf%D3s\\t%0, %2 + it\\t%D3\;mnf%D3s\\t%0, #%N2 + it\\t%d3\;mvf%d3s\\t%0, %1 + it\\t%d3\;mnf%d3s\\t%0, #%N1 + ite\\t%d3\;mvf%d3s\\t%0, %1\;mvf%D3s\\t%0, %2 + ite\\t%d3\;mvf%d3s\\t%0, %1\;mnf%D3s\\t%0, #%N2 + ite\\t%d3\;mnf%d3s\\t%0, #%N1\;mvf%D3s\\t%0, %2 + ite\\t%d3\;mnf%d3s\\t%0, #%N1\;mnf%D3s\\t%0, #%N2" + [(set_attr "length" "6,6,6,6,10,10,10,10") + (set_attr "type" "ffarith") + (set_attr "conds" "use")] +) + +(define_insn "*thumb2_movdfcc_fpa" + [(set (match_operand:DF 0 "s_register_operand" "=f,f,f,f,f,f,f,f") + (if_then_else:DF + (match_operator 3 "arm_comparison_operator" + [(match_operand 4 "cc_register" "") (const_int 0)]) + (match_operand:DF 1 "arm_float_add_operand" "0,0,fG,H,fG,fG,H,H") + (match_operand:DF 2 "arm_float_add_operand" "fG,H,0,0,fG,H,fG,H")))] + "TARGET_THUMB2 && TARGET_HARD_FLOAT && TARGET_FPA" + "@ + it\\t%D3\;mvf%D3d\\t%0, %2 + it\\t%D3\;mnf%D3d\\t%0, #%N2 + it\\t%d3\;mvf%d3d\\t%0, %1 + it\\t%d3\;mnf%d3d\\t%0, #%N1 + ite\\t%d3\;mvf%d3d\\t%0, %1\;mvf%D3d\\t%0, %2 + ite\\t%d3\;mvf%d3d\\t%0, %1\;mnf%D3d\\t%0, #%N2 + ite\\t%d3\;mnf%d3d\\t%0, #%N1\;mvf%D3d\\t%0, %2 + ite\\t%d3\;mnf%d3d\\t%0, #%N1\;mnf%D3d\\t%0, #%N2" + [(set_attr "length" "6,6,6,6,10,10,10,10") + (set_attr "type" "ffarith") + (set_attr "conds" "use")] +) + |