diff options
Diffstat (limited to 'gcc/config/arm/arm.md')
| -rw-r--r-- | gcc/config/arm/arm.md | 159 |
1 files changed, 52 insertions, 107 deletions
diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md index ddb9d8f3590..fd3aebd428a 100644 --- a/gcc/config/arm/arm.md +++ b/gcc/config/arm/arm.md @@ -81,14 +81,17 @@ (const (if_then_else (symbol_ref "TARGET_THUMB1") (const_string "yes") (const_string "no")))) -; We use this attribute to disable alternatives that can produce 32-bit -; instructions inside an IT-block in Thumb2 state. ARMv8 deprecates IT blocks -; that contain 32-bit instructions. -(define_attr "enabled_for_depr_it" "no,yes" (const_string "yes")) - -; This attribute is used to disable a predicated alternative when we have -; arm_restrict_it. -(define_attr "predicable_short_it" "no,yes" (const_string "yes")) +; Mark an instruction as suitable for "short IT" blocks in Thumb-2. +; The arm_restrict_it flag enables the "short IT" feature which +; restricts IT blocks to a single 16-bit instruction. +; This attribute should only be used on 16-bit Thumb-2 instructions +; which may be predicated (the "predicable" attribute must be set). +(define_attr "predicable_short_it" "no,yes" (const_string "no")) + +; Mark an instruction as suitable for "short IT" blocks in Thumb-2. +; This attribute should only be used on instructions which may emit +; an IT block in their expansion which is not a short IT. +(define_attr "enabled_for_short_it" "no,yes" (const_string "yes")) ;; Operand number of an input operand that is shifted. Zero if the ;; given instruction does not shift one of its input operands. @@ -229,7 +232,7 @@ (match_test "arm_restrict_it"))) (const_string "no") - (and (eq_attr "enabled_for_depr_it" "no") + (and (eq_attr "enabled_for_short_it" "no") (match_test "arm_restrict_it")) (const_string "no") @@ -1036,7 +1039,6 @@ "adc%?\\t%0, %1, %3%S2" [(set_attr "conds" "use") (set_attr "predicable" "yes") - (set_attr "predicable_short_it" "no") (set (attr "type") (if_then_else (match_operand 4 "const_int_operand" "") (const_string "alu_shift_imm") (const_string "alu_shift_reg")))] @@ -1136,7 +1138,6 @@ [(set_attr "conds" "use") (set_attr "arch" "*,a,t2") (set_attr "predicable" "yes") - (set_attr "predicable_short_it" "no") (set_attr "type" "adc_reg,adc_imm,alu_shift_imm")] ) @@ -1666,8 +1667,7 @@ "TARGET_32BIT && arm_arch6" "mla%?\\t%0, %2, %1, %3" [(set_attr "type" "mla") - (set_attr "predicable" "yes") - (set_attr "predicable_short_it" "no")] + (set_attr "predicable" "yes")] ) (define_insn "*mulsi3addsi_compare0" @@ -1743,8 +1743,7 @@ "TARGET_32BIT && arm_arch_thumb2" "mls%?\\t%0, %2, %1, %3" [(set_attr "type" "mla") - (set_attr "predicable" "yes") - (set_attr "predicable_short_it" "no")] + (set_attr "predicable" "yes")] ) (define_expand "maddsidi4" @@ -1780,8 +1779,7 @@ "TARGET_32BIT && arm_arch6" "smlal%?\\t%Q0, %R0, %3, %2" [(set_attr "type" "smlal") - (set_attr "predicable" "yes") - (set_attr "predicable_short_it" "no")] + (set_attr "predicable" "yes")] ) ;; 32x32->64 widening multiply. @@ -1818,8 +1816,7 @@ "TARGET_32BIT && arm_arch6" "smull%?\\t%Q0, %R0, %1, %2" [(set_attr "type" "smull") - (set_attr "predicable" "yes") - (set_attr "predicable_short_it" "no")] + (set_attr "predicable" "yes")] ) (define_expand "umulsidi3" @@ -1850,8 +1847,7 @@ "TARGET_32BIT && arm_arch6" "umull%?\\t%Q0, %R0, %1, %2" [(set_attr "type" "umull") - (set_attr "predicable" "yes") - (set_attr "predicable_short_it" "no")] + (set_attr "predicable" "yes")] ) (define_expand "umaddsidi4" @@ -1887,8 +1883,7 @@ "TARGET_32BIT && arm_arch6" "umlal%?\\t%Q0, %R0, %3, %2" [(set_attr "type" "umlal") - (set_attr "predicable" "yes") - (set_attr "predicable_short_it" "no")] + (set_attr "predicable" "yes")] ) (define_expand "smulsi3_highpart" @@ -1932,8 +1927,7 @@ "TARGET_32BIT && arm_arch6" "smull%?\\t%3, %0, %2, %1" [(set_attr "type" "smull") - (set_attr "predicable" "yes") - (set_attr "predicable_short_it" "no")] + (set_attr "predicable" "yes")] ) (define_expand "umulsi3_highpart" @@ -1977,8 +1971,7 @@ "TARGET_32BIT && arm_arch6" "umull%?\\t%3, %0, %2, %1" [(set_attr "type" "umull") - (set_attr "predicable" "yes") - (set_attr "predicable_short_it" "no")] + (set_attr "predicable" "yes")] ) (define_insn "mulhisi3" @@ -2003,8 +1996,7 @@ "TARGET_DSP_MULTIPLY" "smultb%?\\t%0, %1, %2" [(set_attr "type" "smulxy") - (set_attr "predicable" "yes") - (set_attr "predicable_short_it" "no")] + (set_attr "predicable" "yes")] ) (define_insn "*mulhisi3bt" @@ -2017,8 +2009,7 @@ "TARGET_DSP_MULTIPLY" "smulbt%?\\t%0, %1, %2" [(set_attr "type" "smulxy") - (set_attr "predicable" "yes") - (set_attr "predicable_short_it" "no")] + (set_attr "predicable" "yes")] ) (define_insn "*mulhisi3tt" @@ -2032,8 +2023,7 @@ "TARGET_DSP_MULTIPLY" "smultt%?\\t%0, %1, %2" [(set_attr "type" "smulxy") - (set_attr "predicable" "yes") - (set_attr "predicable_short_it" "no")] + (set_attr "predicable" "yes")] ) (define_insn "maddhisi4" @@ -2046,8 +2036,7 @@ "TARGET_DSP_MULTIPLY" "smlabb%?\\t%0, %1, %2, %3" [(set_attr "type" "smlaxy") - (set_attr "predicable" "yes") - (set_attr "predicable_short_it" "no")] + (set_attr "predicable" "yes")] ) ;; Note: there is no maddhisi4ibt because this one is canonical form @@ -2062,8 +2051,7 @@ "TARGET_DSP_MULTIPLY" "smlatb%?\\t%0, %1, %2, %3" [(set_attr "type" "smlaxy") - (set_attr "predicable" "yes") - (set_attr "predicable_short_it" "no")] + (set_attr "predicable" "yes")] ) (define_insn "*maddhisi4tt" @@ -2078,8 +2066,7 @@ "TARGET_DSP_MULTIPLY" "smlatt%?\\t%0, %1, %2, %3" [(set_attr "type" "smlaxy") - (set_attr "predicable" "yes") - (set_attr "predicable_short_it" "no")] + (set_attr "predicable" "yes")] ) (define_insn "maddhidi4" @@ -2093,8 +2080,7 @@ "TARGET_DSP_MULTIPLY" "smlalbb%?\\t%Q0, %R0, %1, %2" [(set_attr "type" "smlalxy") - (set_attr "predicable" "yes") - (set_attr "predicable_short_it" "no")]) + (set_attr "predicable" "yes")]) ;; Note: there is no maddhidi4ibt because this one is canonical form (define_insn "*maddhidi4tb" @@ -2110,8 +2096,7 @@ "TARGET_DSP_MULTIPLY" "smlaltb%?\\t%Q0, %R0, %1, %2" [(set_attr "type" "smlalxy") - (set_attr "predicable" "yes") - (set_attr "predicable_short_it" "no")]) + (set_attr "predicable" "yes")]) (define_insn "*maddhidi4tt" [(set (match_operand:DI 0 "s_register_operand" "=r") @@ -2128,8 +2113,7 @@ "TARGET_DSP_MULTIPLY" "smlaltt%?\\t%Q0, %R0, %1, %2" [(set_attr "type" "smlalxy") - (set_attr "predicable" "yes") - (set_attr "predicable_short_it" "no")]) + (set_attr "predicable" "yes")]) (define_expand "mulsf3" [(set (match_operand:SF 0 "s_register_operand" "") @@ -2518,7 +2502,6 @@ " [(set_attr "conds" "set") (set_attr "predicable" "yes") - (set_attr "predicable_short_it" "no") (set_attr "type" "logics_imm")] ) @@ -2918,7 +2901,6 @@ "bfc%?\t%0, %2, %1" [(set_attr "length" "4") (set_attr "predicable" "yes") - (set_attr "predicable_short_it" "no") (set_attr "type" "bfm")] ) @@ -2931,7 +2913,6 @@ "bfi%?\t%0, %3, %2, %1" [(set_attr "length" "4") (set_attr "predicable" "yes") - (set_attr "predicable_short_it" "no") (set_attr "type" "bfm")] ) @@ -2986,7 +2967,6 @@ }" [(set_attr "length" "4,8") (set_attr "predicable" "yes") - (set_attr "predicable_short_it" "no") (set_attr "type" "multiple")] ) @@ -3008,7 +2988,6 @@ }" [(set_attr "length" "8") (set_attr "predicable" "yes") - (set_attr "predicable_short_it" "no") (set_attr "type" "multiple")] ) @@ -3033,7 +3012,6 @@ }" [(set_attr "length" "8") (set_attr "predicable" "yes") - (set_attr "predicable_short_it" "no") (set_attr "type" "multiple")] ) @@ -3044,7 +3022,6 @@ "TARGET_32BIT" "bic%?\\t%0, %1, %2" [(set_attr "predicable" "yes") - (set_attr "predicable_short_it" "no") (set_attr "type" "logic_reg")] ) @@ -3078,7 +3055,6 @@ "TARGET_ARM || (TARGET_THUMB2 && CONST_INT_P (operands[2]))" "bics%?\\t%4, %3, %1%S0" [(set_attr "predicable" "yes") - (set_attr "predicable_short_it" "no") (set_attr "conds" "set") (set_attr "shift" "1") (set (attr "type") (if_then_else (match_operand 2 "const_int_operand" "") @@ -3104,7 +3080,6 @@ "TARGET_ARM || (TARGET_THUMB2 && CONST_INT_P (operands[2]))" "bics%?\\t%4, %3, %1%S0" [(set_attr "predicable" "yes") - (set_attr "predicable_short_it" "no") (set_attr "conds" "set") (set_attr "shift" "1") (set (attr "type") (if_then_else (match_operand 2 "const_int_operand" "") @@ -3219,7 +3194,6 @@ #" [(set_attr "length" "4,8") (set_attr "predicable" "yes") - (set_attr "predicable_short_it" "no") (set_attr "type" "logic_reg,multiple")] ) @@ -3419,7 +3393,6 @@ #" [(set_attr "length" "4,8") (set_attr "predicable" "yes") - (set_attr "predicable_short_it" "no") (set_attr "type" "logic_reg")] ) @@ -3563,7 +3536,6 @@ [(set_attr "length" "8") (set_attr "ce_count" "2") (set_attr "predicable" "yes") - (set_attr "predicable_short_it" "no") (set_attr "type" "multiple")] ) @@ -3701,7 +3673,6 @@ "TARGET_32BIT" "bic%?\\t%0, %1, %1, asr #31" [(set_attr "predicable" "yes") - (set_attr "predicable_short_it" "no") (set_attr "type" "logic_shift_reg")] ) @@ -3712,7 +3683,6 @@ "TARGET_32BIT" "orr%?\\t%0, %1, %1, asr #31" [(set_attr "predicable" "yes") - (set_attr "predicable_short_it" "no") (set_attr "type" "logic_shift_reg")] ) @@ -3763,7 +3733,6 @@ "TARGET_32BIT" "and%?\\t%0, %1, %1, asr #31" [(set_attr "predicable" "yes") - (set_attr "predicable_short_it" "no") (set_attr "type" "logic_shift_reg")] ) @@ -4000,7 +3969,6 @@ return "usat%?\t%0, %1, %3"; } [(set_attr "predicable" "yes") - (set_attr "predicable_short_it" "no") (set_attr "type" "alus_imm")] ) @@ -4027,7 +3995,6 @@ return "usat%?\t%0, %1, %4%S3"; } [(set_attr "predicable" "yes") - (set_attr "predicable_short_it" "no") (set_attr "shift" "3") (set_attr "type" "logic_shift_reg")]) @@ -4278,7 +4245,6 @@ "TARGET_32BIT" "mvn%?\\t%0, %1%S3" [(set_attr "predicable" "yes") - (set_attr "predicable_short_it" "no") (set_attr "shift" "1") (set_attr "arch" "32,a") (set_attr "type" "mvn_shift,mvn_shift_reg")]) @@ -4554,7 +4520,6 @@ "sbfx%?\t%0, %1, %3, %2" [(set_attr "length" "4") (set_attr "predicable" "yes") - (set_attr "predicable_short_it" "no") (set_attr "type" "bfm")] ) @@ -4569,7 +4534,6 @@ "ubfx%?\t%0, %1, %3, %2" [(set_attr "length" "4") (set_attr "predicable" "yes") - (set_attr "predicable_short_it" "no") (set_attr "type" "bfm")] ) @@ -4585,7 +4549,6 @@ sdiv\t%0, %1, %2" [(set_attr "arch" "32,v8mb") (set_attr "predicable" "yes") - (set_attr "predicable_short_it" "no") (set_attr "type" "sdiv")] ) @@ -4599,7 +4562,6 @@ udiv\t%0, %1, %2" [(set_attr "arch" "32,v8mb") (set_attr "predicable" "yes") - (set_attr "predicable_short_it" "no") (set_attr "type" "udiv")] ) @@ -5377,8 +5339,7 @@ "TARGET_INT_SIMD" "uxtah%?\\t%0, %2, %1" [(set_attr "type" "alu_shift_reg") - (set_attr "predicable" "yes") - (set_attr "predicable_short_it" "no")] + (set_attr "predicable" "yes")] ) (define_expand "zero_extendqisi2" @@ -5448,7 +5409,6 @@ "TARGET_INT_SIMD" "uxtab%?\\t%0, %2, %1" [(set_attr "predicable" "yes") - (set_attr "predicable_short_it" "no") (set_attr "type" "alu_shift_reg")] ) @@ -5501,7 +5461,6 @@ "tst%?\\t%0, #255" [(set_attr "conds" "set") (set_attr "predicable" "yes") - (set_attr "predicable_short_it" "no") (set_attr "type" "logic_imm")] ) @@ -5611,8 +5570,7 @@ sxth%?\\t%0, %1 ldrsh%?\\t%0, %1" [(set_attr "type" "extend,load_byte") - (set_attr "predicable" "yes") - (set_attr "predicable_short_it" "no")] + (set_attr "predicable" "yes")] ) (define_insn "*arm_extendhisi2addsi" @@ -5716,8 +5674,7 @@ "TARGET_INT_SIMD" "sxtab%?\\t%0, %2, %1" [(set_attr "type" "alu_shift_reg") - (set_attr "predicable" "yes") - (set_attr "predicable_short_it" "no")] + (set_attr "predicable" "yes")] ) (define_expand "extendsfdf2" @@ -6084,7 +6041,6 @@ movt\t%0, #:upper16:%c2" [(set_attr "arch" "32,v8mb") (set_attr "predicable" "yes") - (set_attr "predicable_short_it" "no") (set_attr "length" "4") (set_attr "type" "alu_sreg")] ) @@ -6964,8 +6920,7 @@ [(set_attr "conds" "unconditional") (set_attr "type" "load_4,store_4,mov_reg,multiple") (set_attr "length" "4,4,4,8") - (set_attr "predicable" "yes") - (set_attr "predicable_short_it" "no")] + (set_attr "predicable" "yes")] ) (define_expand "movsf" @@ -7018,7 +6973,6 @@ ldr%?\\t%0, %1\\t%@ float str%?\\t%1, %0\\t%@ float" [(set_attr "predicable" "yes") - (set_attr "predicable_short_it" "no") (set_attr "type" "mov_reg,load_4,store_4") (set_attr "arm_pool_range" "*,4096,*") (set_attr "thumb2_pool_range" "*,4094,*") @@ -7436,7 +7390,7 @@ operands[1] = gen_lowpart (SImode, operands[1]); } [(set_attr "conds" "set") - (set_attr "enabled_for_depr_it" "yes,yes,no,*") + (set_attr "enabled_for_short_it" "yes,yes,no,*") (set_attr "arch" "t2,t2,t2,a") (set_attr "length" "6,6,10,8") (set_attr "type" "multiple")] @@ -8823,7 +8777,6 @@ "TARGET_32BIT" "<arith_shift_insn>%?\\t%0, %1, %2, lsl %b3" [(set_attr "predicable" "yes") - (set_attr "predicable_short_it" "no") (set_attr "shift" "2") (set_attr "arch" "a,t2") (set_attr "type" "alu_shift_imm")]) @@ -8838,7 +8791,6 @@ "TARGET_32BIT && GET_CODE (operands[2]) != MULT" "<arith_shift_insn>%?\\t%0, %1, %3%S2" [(set_attr "predicable" "yes") - (set_attr "predicable_short_it" "no") (set_attr "shift" "3") (set_attr "arch" "a,t2,a") (set_attr "type" "alu_shift_imm,alu_shift_imm,alu_shift_reg")]) @@ -8906,6 +8858,7 @@ "TARGET_32BIT" "sub%?\\t%0, %1, %3%S2" [(set_attr "predicable" "yes") + (set_attr "predicable_short_it" "no") (set_attr "shift" "3") (set_attr "arch" "32,a") (set_attr "type" "alus_shift_imm,alus_shift_reg")]) @@ -9344,6 +9297,7 @@ }" [(set_attr "conds" "set") (set_attr "arch" "t2,t2,t2,t2,t2,any,any,any,any") + (set_attr "enabled_for_short_it" "yes,no,no,no,no,no,no,no,no") (set_attr "type" "multiple") (set_attr_alternative "length" [(const_int 6) @@ -9427,6 +9381,7 @@ }" [(set_attr "conds" "set") (set_attr "arch" "t2,t2,t2,t2,t2,any,any,any,any") + (set_attr "enabled_for_short_it" "yes,no,no,no,no,no,no,no,no") (set_attr_alternative "length" [(const_int 6) (const_int 8) @@ -9509,7 +9464,7 @@ [(set_attr "conds" "set") (set_attr "predicable" "no") (set_attr "arch" "t2,t2,t2,t2,t2,any,any,any,any") - (set_attr "enabled_for_depr_it" "yes,no,no,no,no,no,no,no,no") + (set_attr "enabled_for_short_it" "yes,no,no,no,no,no,no,no,no") (set_attr_alternative "length" [(const_int 6) (const_int 8) @@ -9592,7 +9547,7 @@ " [(set_attr "conds" "set") (set_attr "arch" "t2,t2,t2,t2,t2,any,any,any,any") - (set_attr "enabled_for_depr_it" "yes,no,no,no,no,no,no,no,no") + (set_attr "enabled_for_short_it" "yes,no,no,no,no,no,no,no,no") (set_attr_alternative "length" [(const_int 6) (const_int 8) @@ -9640,7 +9595,7 @@ DOM_CC_X_OR_Y), CC_REGNUM);" [(set_attr "conds" "clob") - (set_attr "enabled_for_depr_it" "yes,no") + (set_attr "enabled_for_short_it" "yes,no") (set_attr "length" "16") (set_attr "type" "multiple")] ) @@ -9671,7 +9626,7 @@ (set (match_dup 7) (ne:SI (match_dup 0) (const_int 0)))] "" [(set_attr "conds" "set") - (set_attr "enabled_for_depr_it" "yes,no") + (set_attr "enabled_for_short_it" "yes,no") (set_attr "length" "16") (set_attr "type" "multiple")] ) @@ -9704,7 +9659,7 @@ DOM_CC_X_AND_Y), CC_REGNUM);" [(set_attr "conds" "clob") - (set_attr "enabled_for_depr_it" "yes,no") + (set_attr "enabled_for_short_it" "yes,no") (set_attr "length" "16") (set_attr "type" "multiple")] ) @@ -9735,7 +9690,7 @@ (set (match_dup 7) (ne:SI (match_dup 0) (const_int 0)))] "" [(set_attr "conds" "set") - (set_attr "enabled_for_depr_it" "yes,no") + (set_attr "enabled_for_short_it" "yes,no") (set_attr "length" "16") (set_attr "type" "multiple")] ) @@ -9922,7 +9877,7 @@ } " [(set_attr "conds" "clob") - (set_attr "enabled_for_depr_it" "no,yes,yes") + (set_attr "enabled_for_short_it" "no,yes,yes") (set_attr "type" "multiple")] ) @@ -10540,7 +10495,7 @@ [(set_attr "conds" "use") (set_attr "length" "4") (set_attr "arch" "t2,32") - (set_attr "enabled_for_depr_it" "yes,no") + (set_attr "enabled_for_short_it" "yes,no") (set_attr "type" "logic_shift_imm")] ) @@ -10586,7 +10541,7 @@ [(set_attr "conds" "use") (set_attr "length" "4") (set_attr "arch" "t2,32") - (set_attr "enabled_for_depr_it" "yes,no") + (set_attr "enabled_for_short_it" "yes,no") (set_attr "type" "logic_shift_imm")] ) @@ -11322,7 +11277,6 @@ "TARGET_32BIT && arm_arch5" "clz%?\\t%0, %1" [(set_attr "predicable" "yes") - (set_attr "predicable_short_it" "no") (set_attr "type" "clz")]) (define_insn "rbitsi2" @@ -11331,7 +11285,6 @@ "TARGET_32BIT && arm_arch_thumb2" "rbit%?\\t%0, %1" [(set_attr "predicable" "yes") - (set_attr "predicable_short_it" "no") (set_attr "type" "clz")]) ;; Keep this as a CTZ expression until after reload and then split @@ -11483,7 +11436,6 @@ movt\t%0, %L1" [(set_attr "arch" "32,v8mb") (set_attr "predicable" "yes") - (set_attr "predicable_short_it" "no") (set_attr "length" "4") (set_attr "type" "alu_sreg")] ) @@ -11499,7 +11451,6 @@ [(set_attr "arch" "t1,t2,32") (set_attr "length" "2,2,4") (set_attr "predicable" "no,yes,yes") - (set_attr "predicable_short_it" "no") (set_attr "type" "rev")] ) @@ -11747,8 +11698,7 @@ false, true))" "ldrd%?\t%0, %3, [%1, %2]" [(set_attr "type" "load_8") - (set_attr "predicable" "yes") - (set_attr "predicable_short_it" "no")]) + (set_attr "predicable" "yes")]) (define_insn "*thumb2_ldrd_base" [(set (match_operand:SI 0 "s_register_operand" "=r") @@ -11761,8 +11711,7 @@ operands[1], 0, false, true))" "ldrd%?\t%0, %2, [%1]" [(set_attr "type" "load_8") - (set_attr "predicable" "yes") - (set_attr "predicable_short_it" "no")]) + (set_attr "predicable" "yes")]) (define_insn "*thumb2_ldrd_base_neg" [(set (match_operand:SI 0 "s_register_operand" "=r") @@ -11775,8 +11724,7 @@ operands[1], -4, false, true))" "ldrd%?\t%0, %2, [%1, #-4]" [(set_attr "type" "load_8") - (set_attr "predicable" "yes") - (set_attr "predicable_short_it" "no")]) + (set_attr "predicable" "yes")]) (define_insn "*thumb2_strd" [(set (mem:SI (plus:SI (match_operand:SI 0 "s_register_operand" "rk") @@ -11792,8 +11740,7 @@ false, false))" "strd%?\t%2, %4, [%0, %1]" [(set_attr "type" "store_8") - (set_attr "predicable" "yes") - (set_attr "predicable_short_it" "no")]) + (set_attr "predicable" "yes")]) (define_insn "*thumb2_strd_base" [(set (mem:SI (match_operand:SI 0 "s_register_operand" "rk")) @@ -11806,8 +11753,7 @@ operands[0], 0, false, false))" "strd%?\t%1, %2, [%0]" [(set_attr "type" "store_8") - (set_attr "predicable" "yes") - (set_attr "predicable_short_it" "no")]) + (set_attr "predicable" "yes")]) (define_insn "*thumb2_strd_base_neg" [(set (mem:SI (plus:SI (match_operand:SI 0 "s_register_operand" "rk") @@ -11820,8 +11766,7 @@ operands[0], -4, false, false))" "strd%?\t%1, %2, [%0, #-4]" [(set_attr "type" "store_8") - (set_attr "predicable" "yes") - (set_attr "predicable_short_it" "no")]) + (set_attr "predicable" "yes")]) ;; ARMv8 CRC32 instructions. (define_insn "<crc_variant>" |