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-rw-r--r--gcc/config/arm/arm.c16
1 files changed, 16 insertions, 0 deletions
diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c
index 1f3f9b3171c..701ab4cfe2d 100644
--- a/gcc/config/arm/arm.c
+++ b/gcc/config/arm/arm.c
@@ -255,6 +255,7 @@ static bool arm_array_mode_supported_p (enum machine_mode,
unsigned HOST_WIDE_INT);
static enum machine_mode arm_preferred_simd_mode (enum machine_mode);
static bool arm_class_likely_spilled_p (reg_class_t);
+static HOST_WIDE_INT arm_vector_alignment (const_tree type);
static bool arm_vector_alignment_reachable (const_tree type, bool is_packed);
static bool arm_builtin_support_vector_misalignment (enum machine_mode mode,
const_tree type,
@@ -606,6 +607,9 @@ static const struct attribute_spec arm_attribute_table[] =
#undef TARGET_CLASS_LIKELY_SPILLED_P
#define TARGET_CLASS_LIKELY_SPILLED_P arm_class_likely_spilled_p
+#undef TARGET_VECTOR_ALIGNMENT
+#define TARGET_VECTOR_ALIGNMENT arm_vector_alignment
+
#undef TARGET_VECTORIZE_VECTOR_ALIGNMENT_REACHABLE
#define TARGET_VECTORIZE_VECTOR_ALIGNMENT_REACHABLE \
arm_vector_alignment_reachable
@@ -25063,6 +25067,18 @@ arm_have_conditional_execution (void)
return !TARGET_THUMB1;
}
+/* The AAPCS sets the maximum alignment of a vector to 64 bits. */
+static HOST_WIDE_INT
+arm_vector_alignment (const_tree type)
+{
+ HOST_WIDE_INT align = tree_low_cst (TYPE_SIZE (type), 0);
+
+ if (TARGET_AAPCS_BASED)
+ align = MIN (align, 64);
+
+ return align;
+}
+
static unsigned int
arm_autovectorize_vector_sizes (void)
{