diff options
Diffstat (limited to 'gcc/config/arc/arc.h')
| -rw-r--r-- | gcc/config/arc/arc.h | 46 |
1 files changed, 42 insertions, 4 deletions
diff --git a/gcc/config/arc/arc.h b/gcc/config/arc/arc.h index e8baf5b8d79..d312f9f14a7 100644 --- a/gcc/config/arc/arc.h +++ b/gcc/config/arc/arc.h @@ -80,6 +80,14 @@ along with GCC; see the file COPYING3. If not see builtin_define ("__A7__"); \ builtin_define ("__ARC700__"); \ } \ + else if (TARGET_EM) \ + { \ + builtin_define ("__EM__"); \ + } \ + else if (TARGET_HS) \ + { \ + builtin_define ("__HS__"); \ + } \ if (TARGET_NORM) \ { \ builtin_define ("__ARC_NORM__");\ @@ -143,6 +151,8 @@ along with GCC; see the file COPYING3. If not see %{mcpu=ARC700|!mcpu=*:%{mlock}} \ %{mcpu=ARC700|!mcpu=*:%{mswape}} \ %{mcpu=ARC700|!mcpu=*:%{mrtsc}} \ +%{mcpu=ARCHS:-mHS} \ +%{mcpu=ARCEM:-mEM} \ " #if DEFAULT_LIBC == LIBC_UCLIBC @@ -246,12 +256,13 @@ along with GCC; see the file COPYING3. If not see /* Non-zero means the cpu supports norm instruction. This flag is set by default for A7, and only for pre A7 cores when -mnorm is given. */ -#define TARGET_NORM (TARGET_ARC700 || TARGET_NORM_SET) +#define TARGET_NORM (TARGET_ARC700 || TARGET_NORM_SET || TARGET_HS) /* Indicate if an optimized floating point emulation library is available. */ #define TARGET_OPTFPE \ (TARGET_ARC700 \ /* We need a barrel shifter and NORM. */ \ - || (TARGET_ARC600 && TARGET_NORM_SET)) + || (TARGET_ARC600 && TARGET_NORM_SET) \ + || TARGET_HS) /* Non-zero means the cpu supports swap instruction. This flag is set by default for A7, and only for pre A7 cores when -mswap is given. */ @@ -271,11 +282,15 @@ along with GCC; see the file COPYING3. If not see /* For an anulled-true delay slot insn for a delayed branch, should we only use conditional execution? */ -#define TARGET_AT_DBR_CONDEXEC (!TARGET_ARC700) +#define TARGET_AT_DBR_CONDEXEC (!TARGET_ARC700 && !TARGET_V2) #define TARGET_ARC600 (arc_cpu == PROCESSOR_ARC600) #define TARGET_ARC601 (arc_cpu == PROCESSOR_ARC601) #define TARGET_ARC700 (arc_cpu == PROCESSOR_ARC700) +#define TARGET_EM (arc_cpu == PROCESSOR_ARCEM) +#define TARGET_HS (arc_cpu == PROCESSOR_ARCHS) +#define TARGET_V2 \ + ((arc_cpu == PROCESSOR_ARCHS) || (arc_cpu == PROCESSOR_ARCEM)) /* Recast the cpu class to be the cpu attribute. */ #define arc_cpu_attr ((enum attr_cpu)arc_cpu) @@ -744,6 +759,7 @@ extern enum reg_class arc_regno_reg_class[]; ((unsigned) (((X) >> (SHIFT)) + 0x100) \ < 0x200 - ((unsigned) (OFFSET) >> (SHIFT))) #define SIGNED_INT12(X) ((unsigned) ((X) + 0x800) < 0x1000) +#define SIGNED_INT16(X) ((unsigned) ((X) + 0x8000) < 0x10000) #define LARGE_INT(X) \ (((X) < 0) \ ? (X) >= (-(HOST_WIDE_INT) 0x7fffffff - 1) \ @@ -1305,6 +1321,7 @@ do { \ #endif #define SET_ASM_OP "\t.set\t" +extern char rname29[], rname30[]; extern char rname56[], rname57[], rname58[], rname59[]; /* How to refer to registers in assembler output. This sequence is indexed by compiler's hard-register-number (see above). */ @@ -1312,7 +1329,7 @@ extern char rname56[], rname57[], rname58[], rname59[]; { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", \ "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", \ "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", \ - "r24", "r25", "gp", "fp", "sp", "ilink1", "ilink2", "blink", \ + "r24", "r25", "gp", "fp", "sp", rname29, rname30, "blink", \ "r32", "r33", "r34", "r35", "r36", "r37", "r38", "r39", \ "d1", "d1", "d2", "d2", "r44", "r45", "r46", "r47", \ "r48", "r49", "r50", "r51", "r52", "r53", "r54", "r55", \ @@ -1678,4 +1695,25 @@ enum #define SFUNC_CHECK_PREDICABLE \ (GET_CODE (PATTERN (insn)) != COND_EXEC || !flag_pic || !TARGET_MEDIUM_CALLS) +/* MPYW feature macro. Only valid for ARCHS and ARCEM cores. */ +#define TARGET_MPYW ((arc_mpy_option > 0) && TARGET_V2) +/* Full ARCv2 multiplication feature macro. */ +#define TARGET_MULTI ((arc_mpy_option > 1) && TARGET_V2) +/* General MPY feature macro. */ +#define TARGET_MPY ((TARGET_ARC700 && (!TARGET_NOMPY_SET)) || TARGET_MULTI) +/* ARC700 MPY feature macro. */ +#define TARGET_ARC700_MPY (TARGET_ARC700 && (!TARGET_NOMPY_SET)) +/* Any multiplication feature macro. */ +#define TARGET_ANY_MPY \ + (TARGET_MPY || TARGET_MUL64_SET || TARGET_MULMAC_32BY16_SET) + +/* ARC600 and ARC601 feature macro. */ +#define TARGET_ARC600_FAMILY (TARGET_ARC600 || TARGET_ARC601) +/* ARC600, ARC601 and ARC700 feature macro. */ +#define TARGET_ARCOMPACT_FAMILY \ + (TARGET_ARC600 || TARGET_ARC601 || TARGET_ARC700) +/* Loop count register can be read in very next instruction after has + been written to by an ordinary instruction. */ +#define TARGET_LP_WR_INTERLOCK (!TARGET_ARC600_FAMILY) + #endif /* GCC_ARC_H */ |