diff options
Diffstat (limited to 'gcc/config/aarch64/aarch64.c')
| -rw-r--r-- | gcc/config/aarch64/aarch64.c | 47 |
1 files changed, 42 insertions, 5 deletions
diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c index df74ad96949..b7d4640826a 100644 --- a/gcc/config/aarch64/aarch64.c +++ b/gcc/config/aarch64/aarch64.c @@ -2936,12 +2936,18 @@ aarch64_layout_frame (void) cfun->machine->frame.laid_out = true; } +/* Return true if the register REGNO is saved on entry to + the current function. */ + static bool aarch64_register_saved_on_entry (int regno) { return cfun->machine->frame.reg_offset[regno] >= 0; } +/* Return the next register up from REGNO up to LIMIT for the callee + to save. */ + static unsigned aarch64_next_callee_save (unsigned regno, unsigned limit) { @@ -2950,6 +2956,9 @@ aarch64_next_callee_save (unsigned regno, unsigned limit) return regno; } +/* Push the register number REGNO of mode MODE to the stack with write-back + adjusting the stack by ADJUSTMENT. */ + static void aarch64_pushwb_single_reg (machine_mode mode, unsigned regno, HOST_WIDE_INT adjustment) @@ -2966,6 +2975,10 @@ aarch64_pushwb_single_reg (machine_mode mode, unsigned regno, RTX_FRAME_RELATED_P (insn) = 1; } +/* Generate and return an instruction to store the pair of registers + REG and REG2 of mode MODE to location BASE with write-back adjusting + the stack location BASE by ADJUSTMENT. */ + static rtx aarch64_gen_storewb_pair (machine_mode mode, rtx base, rtx reg, rtx reg2, HOST_WIDE_INT adjustment) @@ -2985,6 +2998,9 @@ aarch64_gen_storewb_pair (machine_mode mode, rtx base, rtx reg, rtx reg2, } } +/* Push registers numbered REGNO1 and REGNO2 to the stack, adjusting the + stack pointer by ADJUSTMENT. */ + static void aarch64_push_regs (unsigned regno1, unsigned regno2, HOST_WIDE_INT adjustment) { @@ -3004,6 +3020,9 @@ aarch64_push_regs (unsigned regno1, unsigned regno2, HOST_WIDE_INT adjustment) RTX_FRAME_RELATED_P (insn) = 1; } +/* Load the pair of register REG, REG2 of mode MODE from stack location BASE, + adjusting it by ADJUSTMENT afterwards. */ + static rtx aarch64_gen_loadwb_pair (machine_mode mode, rtx base, rtx reg, rtx reg2, HOST_WIDE_INT adjustment) @@ -3021,6 +3040,10 @@ aarch64_gen_loadwb_pair (machine_mode mode, rtx base, rtx reg, rtx reg2, } } +/* Pop the two registers numbered REGNO1, REGNO2 from the stack, adjusting it + afterwards by ADJUSTMENT and writing the appropriate REG_CFA_RESTORE notes + into CFI_OPS. */ + static void aarch64_pop_regs (unsigned regno1, unsigned regno2, HOST_WIDE_INT adjustment, rtx *cfi_ops) @@ -3045,6 +3068,9 @@ aarch64_pop_regs (unsigned regno1, unsigned regno2, HOST_WIDE_INT adjustment, } } +/* Generate and return a store pair instruction of mode MODE to store + register REG1 to MEM1 and register REG2 to MEM2. */ + static rtx aarch64_gen_store_pair (machine_mode mode, rtx mem1, rtx reg1, rtx mem2, rtx reg2) @@ -3062,6 +3088,9 @@ aarch64_gen_store_pair (machine_mode mode, rtx mem1, rtx reg1, rtx mem2, } } +/* Generate and regurn a load pair isntruction of mode MODE to load register + REG1 from MEM1 and register REG2 from MEM2. */ + static rtx aarch64_gen_load_pair (machine_mode mode, rtx reg1, rtx mem1, rtx reg2, rtx mem2) @@ -3079,6 +3108,9 @@ aarch64_gen_load_pair (machine_mode mode, rtx reg1, rtx mem1, rtx reg2, } } +/* Emit code to save the callee-saved registers from register number START + to LIMIT to the stack at the location starting at offset START_OFFSET, + skipping any write-back candidates if SKIP_WB is true. */ static void aarch64_save_callee_saves (machine_mode mode, HOST_WIDE_INT start_offset, @@ -3137,6 +3169,11 @@ aarch64_save_callee_saves (machine_mode mode, HOST_WIDE_INT start_offset, } } +/* Emit code to restore the callee registers of mode MODE from register + number START up to and including LIMIT. Restore from the stack offset + START_OFFSET, skipping any write-back candidates if SKIP_WB is true. + Write the appropriate REG_CFA_RESTORE notes into CFI_OPS. */ + static void aarch64_restore_callee_saves (machine_mode mode, HOST_WIDE_INT start_offset, unsigned start, @@ -13197,7 +13234,7 @@ aarch64_use_by_pieces_infrastructure_p (unsigned HOST_WIDE_INT size, } static rtx -aarch64_gen_ccmp_first (rtx *prep_seq, rtx *gen_seq, +aarch64_gen_ccmp_first (rtx_insn **prep_seq, rtx_insn **gen_seq, int code, tree treeop0, tree treeop1) { machine_mode op_mode, cmp_mode, cc_mode = CCmode; @@ -13271,8 +13308,8 @@ aarch64_gen_ccmp_first (rtx *prep_seq, rtx *gen_seq, } static rtx -aarch64_gen_ccmp_next (rtx *prep_seq, rtx *gen_seq, rtx prev, int cmp_code, - tree treeop0, tree treeop1, int bit_code) +aarch64_gen_ccmp_next (rtx_insn **prep_seq, rtx_insn **gen_seq, rtx prev, + int cmp_code, tree treeop0, tree treeop1, int bit_code) { rtx op0, op1, target; machine_mode op_mode, cmp_mode, cc_mode = CCmode; @@ -13281,7 +13318,7 @@ aarch64_gen_ccmp_next (rtx *prep_seq, rtx *gen_seq, rtx prev, int cmp_code, struct expand_operand ops[6]; int aarch64_cond; - push_to_sequence ((rtx_insn*) *prep_seq); + push_to_sequence (*prep_seq); expand_operands (treeop0, treeop1, NULL_RTX, &op0, &op1, EXPAND_NORMAL); op_mode = GET_MODE (op0); @@ -13347,7 +13384,7 @@ aarch64_gen_ccmp_next (rtx *prep_seq, rtx *gen_seq, rtx prev, int cmp_code, create_fixed_operand (&ops[4], prev); create_fixed_operand (&ops[5], GEN_INT (aarch64_cond)); - push_to_sequence ((rtx_insn*) *gen_seq); + push_to_sequence (*gen_seq); if (!maybe_expand_insn (icode, 6, ops)) { end_sequence (); |