diff options
| -rw-r--r-- | gcc/ChangeLog.addr32 | 33 | ||||
| -rw-r--r-- | gcc/ChangeLog.list | 9 | ||||
| -rw-r--r-- | gcc/ChangeLog.unwind | 118 | ||||
| -rw-r--r-- | gcc/ChangeLog.x32 | 1113 | ||||
| -rw-r--r-- | gcc/explow.c | 19 | ||||
| -rw-r--r-- | gcc/testsuite/ChangeLog.x32 | 851 | ||||
| -rw-r--r-- | gcc/testsuite/gfortran.dg/pr49721.f | 35 | ||||
| -rw-r--r-- | libgcc/ChangeLog.unwind | 11 | ||||
| -rw-r--r-- | libgcc/ChangeLog.x32 | 31 | ||||
| -rw-r--r-- | libgomp/ChangeLog.x32 | 19 | ||||
| -rw-r--r-- | libstdc++-v3/ChangeLog.x32 | 3 |
11 files changed, 2235 insertions, 7 deletions
diff --git a/gcc/ChangeLog.addr32 b/gcc/ChangeLog.addr32 new file mode 100644 index 00000000000..77c0ff428ab --- /dev/null +++ b/gcc/ChangeLog.addr32 @@ -0,0 +1,33 @@ +2011-07-18 Uros Bizjak <ubizjak@gmail.com> + + PR target/47744 + * config/i386/i386.c (ix86_decompose_address): Allow only subregs + of DImode hard regs in PLUS chains. + +2011-07-17 H.J. Lu <hongjiu.lu@intel.com> + + * config/i386/i386.c (ix86_decompose_address): Don't support + 32bit address in x32 mode. + +2011-07-17 H.J. Lu <hongjiu.lu@intel.com> + + * config/i386/i386.c (ix86_fixup_binary_operands): Revert x32 + change. + +2011-07-17 H.J. Lu <hongjiu.lu@intel.com> + + * config/i386/i386.md (*lea_0_x32): Removed. + (*lea_2_x32): Likewise. + (*lea_2_zext_x32): Likewise. + (X32 LEA zero-extend split): Likewise. + +2011-07-17 Uros Bizjak <ubizjak@gmail.com> + + PR target/47744 + * config/i386/i386.c (ix86_decompose_address): Properly handle + SUBREG for x32. + +2011-07-17 H.J. Lu <hongjiu.lu@intel.com> + + * config/i386/i386.c (ix86_simplify_base_index_disp): Removed. + (ix86_decompose_address): Don't call it. diff --git a/gcc/ChangeLog.list b/gcc/ChangeLog.list new file mode 100644 index 00000000000..e6de9ad07e5 --- /dev/null +++ b/gcc/ChangeLog.list @@ -0,0 +1,9 @@ +2011-07-07 H.J. Lu <hongjiu.lu@intel.com> + + * config.gcc: Treat with_multilib_list as a list. + + * config/i386/t-linux64: Support TM_MULTILIB_CONFIG. + + * config/i386/t-linux-x32: Removed. + + * doc/install.texi: Update --with-multilib-list=x32. diff --git a/gcc/ChangeLog.unwind b/gcc/ChangeLog.unwind new file mode 100644 index 00000000000..a44b835d1cc --- /dev/null +++ b/gcc/ChangeLog.unwind @@ -0,0 +1,118 @@ +2011-08-02 H.J. Lu <hongjiu.lu@intel.com> + + * system.h (ASSUME_EXTENDED_UNWIND_CONTEXT): Poisoned. + +2011-08-02 H.J. Lu <hongjiu.lu@intel.com> + + * unwind-dw2.c (ASSUME_EXTENDED_UNWIND_CONTEXT): New. + (_Unwind_IsExtendedContext): Check ASSUME_EXTENDED_UNWIND_CONTEXT + for EXTENDED_CONTEXT_BIT. + (__frame_state_for): Likewise. + (uw_init_context_1): Likewise. + + * doc/tm.texi.in: Update REG_VALUE_IN_UNWIND_CONTEXT and + document ASSUME_EXTENDED_UNWIND_CONTEXT. + * doc/tm.texi: Regenerated. + +2011-06-30 H.J. Lu <hongjiu.lu@intel.com> + + * unwind-dw2.c (SIGNAL_FRAME_BIT): Don't redefine for x32. + +2011-06-30 H.J. Lu <hongjiu.lu@intel.com> + + * unwind-dw2.c (_Unwind_Context_Reg_Val): New. + (_Unwind_Get_Unwind_Word): Likewise. + (_Unwind_Get_Unwind_Context_Reg_Val): Likewise. + (_Unwind_Context): Use _Unwind_Context_Reg_Val on the reg field. + (SIGNAL_FRAME_BIT): Define if REG_VALUE_IN_UNWIND_CONTEXT is + defined. + (_Unwind_IsExtendedContext): Likewise. + (EXTENDED_CONTEXT_BIT): Don't define if REG_VALUE_IN_UNWIND_CONTEXT + is defined. + (_Unwind_GetGR): Updated. + (_Unwind_SetGR): Likewise. + (_Unwind_GetGRPtr): Likewise. + (_Unwind_SetGRPtr): Likewise. + (_Unwind_SetGRValue): Likewise. + (_Unwind_GRByValue): Likewise. + (__frame_state_for): Likewise. + (uw_install_context_1): Likewise. + +2011-06-28 H.J. Lu <hongjiu.lu@intel.com> + + * config.gcc (libgcc_tm_file): Add i386/value-unwind.h for + Linux/x86. + + * system.h (REG_VALUE_IN_UNWIND_CONTEXT): Poisoned. + + * unwind-dw2.c (_Unwind_Context): If REG_VALUE_IN_UNWIND_CONTEXT + is defined, add value and remove by_value. + (SIGNAL_FRAME_BIT): Define if REG_VALUE_IN_UNWIND_CONTEXT is + defined. + (EXTENDED_CONTEXT_BIT): Don't define if REG_VALUE_IN_UNWIND_CONTEXT + is defined. + (_Unwind_IsExtendedContext): Likewise. + (_Unwind_GetGR): Support REG_VALUE_IN_UNWIND_CONTEXT. + (_Unwind_SetGR): Likewise. + (_Unwind_GetGRPtr): Likewise. + (_Unwind_SetGRPtr): Likewise. + (_Unwind_SetGRValue): Likewise. + (_Unwind_GRByValue): Likewise. + (__frame_state_for): Likewise. + (uw_install_context_1): Likewise. + + * doc/tm.texi.in: Document REG_VALUE_IN_UNWIND_CONTEXT. + * doc/tm.texi: Regenerated. + +2011-06-28 H.J. Lu <hongjiu.lu@intel.com> + + * config.gcc (libgcc_tm_file): Don't add i386/unique-unwind.h + for Linux/x86. + + * system.h (UNIQUE_UNWIND_CONTEXT): Don't poison. + + * doc/tm.texi.in: Remove UNIQUE_UNWIND_CONTEXT. + * doc/tm.texi: Regenerated. + +2011-06-25 H.J. Lu <hongjiu.lu@intel.com> + + * config.gcc (libgcc_tm_file): Add i386/unique-unwind.h for + Linux/x86. + + * system.h (UNIQUE_UNWIND_CONTEXT): Poisoned. + + * unwind-dw2.c (UNIQUE_UNWIND_CONTEXT): Don't define here. + + * doc/tm.texi.in: Document UNIQUE_UNWIND_CONTEXT. + * doc/tm.texi: Regenerated. + +2011-04-09 H.J. Lu <hongjiu.lu@intel.com> + + PR other/48007 + * unwind-dw2.c (UNIQUE_UNWIND_CONTEXT): New. + (_Unwind_Context): If UNIQUE_UNWIND_CONTEXT is defined, add + dwarf_reg_size_table and value, remove version and by_value. + (EXTENDED_CONTEXT_BIT): Don't define if UNIQUE_UNWIND_CONTEXT + is defined. + (_Unwind_IsExtendedContext): Likewise. + (_Unwind_GetGR): Support UNIQUE_UNWIND_CONTEXT. + (_Unwind_SetGR): Likewise. + (_Unwind_GetGRPtr): Likewise. + (_Unwind_SetGRPtr): Likewise. + (_Unwind_SetGRValue): Likewise. + (_Unwind_GRByValue): Likewise. + (__frame_state_for): Initialize dwarf_reg_size_table field if + UNIQUE_UNWIND_CONTEXT is defined. + (uw_install_context_1): Likewise. Support UNIQUE_UNWIND_CONTEXT. + +2011-04-09 H.J. Lu <hongjiu.lu@intel.com> + + PR other/48007 + * unwind-dw2.c (_Unwind_Context): Revert saving call frame hard + registers as _Unwind_Word. + (_Unwind_GetGR): Don't get GR value as _Unwind_Word. + (_Unwind_SetGR): Don't set GR value as _Unwind_Word. + (_Unwind_SetGRValue): Likewise. + (_Unwind_GetGRPtr): Don't cast return to "void *". + (_Unwind_SetGRPtr): Don't cast pointer to _Unwind_Word. + (uw_install_context_1): Don't cast pointer to "void *". diff --git a/gcc/ChangeLog.x32 b/gcc/ChangeLog.x32 new file mode 100644 index 00000000000..2f102758614 --- /dev/null +++ b/gcc/ChangeLog.x32 @@ -0,0 +1,1113 @@ +2011-08-08 H.J. Lu <hongjiu.lu@intel.com> + + PR middle-end/49721 + * explow.c (convert_memory_address_addr_space): Also permute + zero-extend and addition of constant. + +2011-08-08 H.J. Lu <hongjiu.lu@intel.com> + + Revert + PR middle-end/49721 + * explow.c (convert_memory_address_addr_space_1): New. + (convert_memory_address_addr_space): Use it. + + * expr.c (convert_modes_1): New. + (convert_modes): Use it. + + * expr.h (convert_modes_1): New. + + * rtl.h (convert_memory_address_addr_space_1): New. + (convert_memory_address_1): Likewise. + + * simplify-rtx.c (simplify_unary_operation_1): Call + convert_memory_address_1 instead of convert_memory_address. + +2011-08-02 H.J. Lu <hongjiu.lu@intel.com> + + Revert + PR target/49860 + * config/i386/i386.md (*movdi_internal_rex64): Only allow moving + integer constants into 64bit registers for TARGET_X32. + (*movabs<mode>_1): Only allow for TARGET_LP64. + (*movabs<mode>_2): Likewise. + + * config/i386/predicates.md (x86_64_immediate_operand): Always + allow the offsetted memory references for TARGET_X32. + (x86_64_zext_immediate_operand): Likewise. + +2011-07-29 Uros Bizjak <ubizjak@gmail.com> + + * config/i386/i386.md (*load_tp_x32): New. + (*load_tp_x32_zext): Ditto. + (*add_tp_x32): Ditto. + (*add_tp_x32_zext): Ditto. + (*load_tp_<mode>): Disable for !TARGET_X32 targets. + (*add_tp_<mode>): Ditto. + * config/i386/i386.c (get_thread_pointer): Load thread pointer in + ptr_mode and convert to Pmode if needed. + +2011-07-28 H.J. Lu <hongjiu.lu@intel.com> + + Revert + PR target/47715 + * config/i386/i386.c (get_thread_pointer): Use ptr_mode + instead of Pmode with UNSPEC_TP. + + * config/i386/i386.md (tp_seg): Removed. + (*load_tp_<mode>): Replace :P with :PTR. + (*add_tp_<mode>): Likewise. + (*load_tp_x32): New. + +2011-07-28 H.J. Lu <hongjiu.lu@intel.com> + + PR target/47715 + * config/i386/i386.md (PTR64): Removed. + (*tls_global_dynamic_64_<mode>): Rename to ... + (*tls_global_dynamic_64): This. Remove PTR64 on operand 1. + (tls_global_dynamic_64_<mode>): Rename to ... + (tls_global_dynamic_64): This. Remove PTR64 on operand 1. + * config/i386/i386.c (legitimize_tls_address): Updated. + +2011-07-26 H.J. Lu <hongjiu.lu@intel.com> + + PR target/47372 + * config/i386/i386.c (ix86_delegitimize_address): Call + simplify_gen_subreg for PIC with mode of x only if modes of + x and orig_x are different. + +2011-07-26 H.J. Lu <hongjiu.lu@intel.com> + + * config/i386/i386.c (ix86_expand_move): Don't check and convert + TLS symbol twice. + +2011-07-26 H.J. Lu <hongjiu.lu@intel.com> + + * config/i386/i386.md (A): Removed. + +2011-07-26 Uros Bizjak <ubizjak@gmail.com> + H.J. Lu <hongjiu.lu@intel.com> + + PR target/47381 + PR target/49832 + PR target/49833 + * config/i386/i386.md (i): Change SImode attribute to "e". + (g): Change SImode attribute to "rme". + (di): Change SImode attribute to "nF". + (general_operand): Change SImode attribute to x86_64_general_operand. + (general_szext_operand): Change SImode attribute to + x86_64_szext_general_operand. + (immediate_operand): Change SImode attribute to + x86_64_immediate_operand. + (nonmemory_operand): Change SImode attribute to + x86_64_nonmemory_operand. + (*movdi_internal_rex64): Remove mode from pic_32bit_operand check. + (*movsi_internal): Ditto. Use "e" constraint in alternative 2. + (*lea_1): Use SWI48 mode iterator. + (*lea_1_zext): New insn pattern. + (testsi_ccno_1): Use x86_64_nonmemory_operand predicate for operand 2. + (*bt<mode>): Ditto. + (*add<mode>1): Use x86_64_general_operand predicate for operand 2. + Update operand constraints. + (addsi_1_zext): Ditto. + (*add<mode>2): Ditto. + (*addsi_3_zext): Ditto. + (*subsi_1_zext): Ditto. + (*subsi_2_zext): Ditto. + (*subsi_3_zext): Ditto. + (*addsi3_carry_zext): Ditto. + (*<plusminus_insn>si3_zext_cc_overflow): Ditto. + (*mulsi3_1_zext): Ditto. + (*andsi_1): Ditto. + (*andsi_1_zext): Ditto. + (*andsi_2_zext): Ditto. + (*<any_or:code>si_1_zext): Ditto. + (*<any_or:code>si_2_zext): Ditto. + (*test<mode>_1): Use <general_operand> predicate for operand 1. + (*and<mode>_2): Ditto. + (mov<mode>cc): Use <general_operand> predicate for operands 1 and 2. + (add->lea splitter): Check operand modes in insn constraint. Extend + operands less than SImode wide to SImode. + (add->lea zext splitter): Do not extend input operands to DImode. + (*lea_general_1): Handle only QImode and HImode operands. + (*lea_general_2): Ditto. + (*lea_general_3): Ditto. + (*lea_general_1_zext): Remove. + (*lea_general_2_zext): Ditto. + (*lea_general_3_zext): Ditto. + (*lea_general_4): Check operand modes in insn constraint. Extend + operands less than SImode wide to SImode. + (ashift->lea splitter): Ditto. + * config/i386/i386.c (ix86_print_operand_address): Print address + registers with 'q' modifier on 64bit targets. + * config/i386/predicates.md (pic_32bit_opreand): Define as special + predicate. Reject non-SI and non-DI modes. + +2011-07-24 H.J. Lu <hongjiu.lu@intel.com> + + Revert the following changes: + * config/i386/constraints.md (Ys): Rewritten. + (Ye): Updated. + (Yl): Likewise. + + * config/i386/constraints.md (i): Replace "i" with "Ye". + (l): New. + (g): Replace "g" with "rmYe". + (general_operand): Replace general_operand with + with si_general_operand on SI. + (general_szext_operand): Likewise. + (*movsi_internal): Replace "i" with "Ys". + (*add<mode>_1): Replace <i> with <l>. + (addsi_1_zext): Replace general_operand with si_general_operand + and "g" with "rmYe". + (*addsi_2_zext): Likewise. + (*subsi_1_zext): Likewise. + (*subsi_2_zext): Likewise. + (*subsi_3_zext): Likewise. + (*addsi3_carry_zext): Likewise. + (*subsi3_carry_zext): Likewise. + (*andsi_1): Likewise. + (*andsi_1_zext): Likewise. + (*andsi_2_zext): Likewise. + (LEA split): Replace nonmemory_operand with + si_lea_nonmemory_operand and "i" with "Ye". + (*lea_general_2): Likewise. + (*lea_general_2_zext): Likewise. + (*lea_general_1): Replace immediate_operand with + si_lea_immediate_operand and "i" with "Ye". + (*lea_general_1_zext): Likewise. + (*lea_general_3): Likewise. + (*lea_general_3_zext): Likewise. + + config/i386/predicates.md (si_general_operand): New. + (si_lea_immediate_operand): Likewise. + (si_lea_nonmemory_operand): Likewise. + +2011-07-22 H.J. Lu <hongjiu.lu@intel.com> + + * config/i386/predicates.md (aligned_operand): Don't check + SUBREG_REG for parts.index and parts.base. + +2011-07-22 H.J. Lu <hongjiu.lu@intel.com> + + * config/i386/i386.md: Put back a blank line. + +2011-07-22 H.J. Lu <hongjiu.lu@intel.com> + + * config/i386/constraints.md (Ys): Rewritten. + (Ye): Updated. + (Yl): Likewise. + + * config/i386/predicates.md (x32_store_immediate_operand): Removed. + +2011-07-22 H.J. Lu <hongjiu.lu@intel.com> + + * config/i386/constraints.md (Yl): Replace + x32_lea_immediate_operand with si_lea_immediate_operand. + * config/i386/i386.md (*lea_general_1): Likewise. + (*lea_general_1_zext): Likewise. + (*lea_general_3): Likewise. + (*lea_general_3_zext): Likewise. + + * config/i386/predicates.md (x32_lea_immediate_operand): Removed. + (si_lea_immediate_operand): New. + +2011-07-22 H.J. Lu <hongjiu.lu@intel.com> + + * config/i386/i386.md (LEA split): Replace + x32_lea_nonmemory_operand with si_lea_nonmemory_operand. + (*lea_general_2): Likewise. + (*lea_general_2_zext): Likewise. + + * config/i386/predicates.md (x32_lea_nonmemory_operand): Removed. + (si_lea_nonmemory_operand): New. + +2011-07-22 H.J. Lu <hongjiu.lu@intel.com> + + * config/i386/predicates.md (pointer_register_operand): Removed. + +2011-07-22 H.J. Lu <hongjiu.lu@intel.com> + + * config/i386/i386.md (general_operand): Replace + x32_general_operand with si_general_operand. + (general_szext_operand): Likewise. + (addsi_1_zext): Likewise. + (*addsi_2_zext): Likewise. + (*subsi_1_zext): Likewise. + (*subsi_2_zext): Likewise. + (*subsi_3_zext): Likewise. + (*addsi3_carry_zext): Likewise. + (*subsi3_carry_zext): Likewise. + (*andsi_1): Likewise. + (*andsi_1_zext): Likewise. + (*andsi_2_zext): Likewise. + + * config/i386/predicates.md (x32_general_operand): Renamed to + ... + (si_general_operand): This. + +2011-07-21 H.J. Lu <hongjiu.lu@intel.com> + + * config/i386/i386.c (ix86_option_override_internal): Disallow + MS ABI in x32 mode. + (ix86_init_builtins): Call ix86_init_builtins_va_builtins_abi + only for TARGET_LP64. + (ix86_handle_abi_attribute): Check TARGET_LP64 instead of + TARGET_64BIT. + +2011-07-21 H.J. Lu <hongjiu.lu@intel.com> + + * config/i386/i386.c (ix86_expand_builtin): Use force_reg + in gen_rtx_MEM. + +2011-07-21 H.J. Lu <hongjiu.lu@intel.com> + + * config/i386/i386.c (ix86_decompose_address): Don't move + base_reg nor index_reg. + +2011-07-21 H.J. Lu <hongjiu.lu@intel.com> + + * config/i386/i386.c (ix86_expand_move): Move convert_to_mode + after force_operand. + (ix86_expand_call): Use force_reg after convert_to_mode. + (ix86_expand_special_args_builtin): Likewise. + (ix86_expand_builtin): Likewise. + +2011-07-21 H.J. Lu <hongjiu.lu@intel.com> + + * config/i386/i386.c (function_value_64): Always return pointers + in Pmode. + (ix86_promote_function_mode): Likewise. + +2011-07-20 H.J. Lu <hongjiu.lu@intel.com> + Uros Bizjak <ubizjak@gmail.com> + Richard Henderson <rth@redhat.com> + + * config/i386/constraints.md (w): New. + + * config/i386/i386.c (ix86_output_addr_vec_elt): Check + TARGET_LP64 instead of TARGET_64BIT for ASM_QUAD. + + * config/i386/i386.h (CASE_VECTOR_MODE): Check TARGET_LP64 + instead of TARGET_64BIT. + + * config/i386/i386.md (indirect_jump): Replace + nonimmediate_operand with indirect_branch_operand. + (*indirect_jump): Likewise. Replace constraint "m" with "w". + (tablejump): Replace nonimmediate_operand with + indirect_branch_operand. Convert operand 0 to Pmode for x32 if + not PIC. + (*tablejump_1): Replace nonimmediate_operand with + indirect_branch_operand. Replace constraint "m" with "w". + (*call_vzeroupper): Replace constraint "m" with "w". + (*call): Likewise. + (*call_rex64_ms_sysv_vzeroupper): Likewise. + (*call_rex64_ms_sysv): Likewise. + (*call_value_vzeroupper): Likewise. + (*call_value): Likewise. + (*call_value_rex64_ms_sysv_vzeroupper): Likewise. + (*call_value_rex64_ms_sysv): Likewise. + + * config/i386/predicates.md (indirect_branch_operand): New. + (call_insn_operand): Support x32. + +2011-07-19 H.J. Lu <hongjiu.lu@intel.com> + + * config/i386/i386.c (ix86_output_addr_vec_elt): Don't output + 64bit value for labels for TARGET_X32. + (ix86_output_addr_diff_elt): Check TARGET_64BIT instead of + TARGET_LP64. + + * config/i386/i386.h (CASE_VECTOR_MODE): Check TARGET_LP64 + instead of TARGET_64BIT. + + * config/i386/i386.md (*indirect_jump_x32): Removed. + (*call_vzeroupper_x32): Likewise. + (*call_x32): Likewise. + (*call_rex64_ms_sysv_vzeroupper_x32): Likewise. + (*call_rex64_ms_sysv_x32): Likewise. + (*call_value_vzeroupper_x32): Likewise. + (*call_value_x32): Likewise. + (*call_value_rex64_ms_sysv_vzeroupper_x32): Likewise. + (*call_value_rex64_ms_sysv_x32): Likewise. + +2011-07-19 Uros Bizjak <ubizjak@gmail.com> + + * config/i386/i386.c (ix86_legitimate_address_p): Check if base + and index registers are in SImode or DImode. + +2011-07-19 Uros Bizjak <ubizjak@gmail.com> + + PR target/49780 + * config/i386/i386.c (ix86_decompose_address): Allow only subregs + of DImode hard regs. + + * config/i386/predicates.md (no_seg_address_operand): Use + define_predicate. + +2011-07-19 Uros Bizjak <ubizjak@gmail.com> + + PR target/49780 + * config/i386/i386.c (ix86_legitimate_address_p): Remove checks + that base and index registers are in Pmode. + +2011-07-19 H.J. Lu <hongjiu.lu@intel.com> + + * config/i386/i386.c (ix86_legitimate_address_p): Don't support + 32bit address in x32 mode. + +2011-07-13 H.J. Lu <hongjiu.lu@intel.com> + + * config/i386/i386.c (x86_output_mi_thunk): Check Pmode != + ptr_mode for x32. + +2011-07-10 H.J. Lu <hongjiu.lu@intel.com> + + PR middle-end/47727 + * explow.c (convert_memory_address_addr_space): Permute the + conversion and addition if one operand is a constant and we + are zero-extending. Call convert_memory_address_addr_space_1 + instead convert_memory_address_addr_space. + +2011-07-10 H.J. Lu <hongjiu.lu@intel.com> + + * config/i386/i386.c (x86_output_mi_thunk): Properly support x32. + + * config/i386/i386.md (*addsi_1_zext): Renamed to ... + (addsi_1_zext): This. + +2011-07-10 H.J. Lu <hongjiu.lu@intel.com> + + * explow.c (convert_memory_address_addr_space_1): New. + (convert_memory_address_addr_space): Use it. + + * expr.c (convert_modes_1): New. + (convert_modes): Use it. + + * expr.h (convert_modes_1): New. + + * rtl.h (convert_memory_address_addr_space_1): New. + (convert_memory_address_1): Likewise. + + * simplify-rtx.c (simplify_unary_operation_1): Call + convert_memory_address_1 instead of convert_memory_address. + +2011-07-10 H.J. Lu <hongjiu.lu@intel.com> + + * config/i386/i386.c (ix86_promote_function_mode): Update + comments. + +2011-07-09 H.J. Lu <hongjiu.lu@intel.com> + + * config/i386/i386.c (ix86_trampoline_init): Remove TARGET_X32 + check. + +2011-07-09 H.J. Lu <hongjiu.lu@intel.com> + + * config/i386/i386.md (*movsi_internal): Add comments. + +2011-07-09 H.J. Lu <hongjiu.lu@intel.com> + + * config/i386/i386.c (ix86_simplify_base_disp): Renamed to ... + (ix86_simplify_base_index_disp): This. Handle index. + (ix86_simplify_base_disp): Updated. + + * config/i386/i386.md (*lea_1_x32): Renamed to ... + (*lea_2_x32): This. + (*lea_2_zext_x32): New. + (X32 LEA zero-extend split): Likewise. + +2011-07-06 H.J. Lu <hongjiu.lu@intel.com> + + * config.gcc: Check with_multilib_list instead of enable_x32. + + * configure.ac: Remove --enable-x32. + * configure: Regenerated. + + * doc/install.texi: Document --with-multilib-list=x32. Remove + --enable-x32. + +2011-07-05 H.J. Lu <hongjiu.lu@intel.com> + + * config.gcc: Remove --enable-ia32 support. + + * configure.ac: Remove --enable-ia32. + * configure: Regenerated. + + * config/i386/t-linux64-x32: Removed. + + * doc/install.texi: Remove --enable-ia32. + +2011-07-05 H.J. Lu <hongjiu.lu@intel.com> + + PR middle-end/47383 + * tree-ssa-address.c (addr_for_mem_ref): Use pointer_mode for + address computation and convert to address_mode if needed. + +2011-07-05 H.J. Lu <hongjiu.lu@intel.com> + + * tree-ssa-address.c (addr_for_mem_ref): Use + targetm.addr_space.address_mode. + +2011-06-30 H.J. Lu <hongjiu.lu@intel.com> + + * function.c (expand_function_start): Use proper mode for stack + save area. + +2011-06-29 H.J. Lu <hongjiu.lu@intel.com> + + PR middle-end/47715 + * calls.c (precompute_register_parameters): Promote the function + argument before checking non-legitimate constant. + +2011-06-29 H.J. Lu <hongjiu.lu@intel.com> + + * calls.c (precompute_register_parameters): Don't convert pointer + to TLS symbol. + +2011-06-28 H.J. Lu <hongjiu.lu@intel.com> + + PR target/48155 + * config/i386/i386.md (*lea_0_x32): New. + * config/i386/predicates.md (pointer_register_operand): Likewise. + +2011-06-28 Ulrich Weigand <Ulrich.Weigand@de.ibm.com> + + PR rtl-optimization/49114 + * reload.c (struct replacement): Remove SUBREG_LOC member. + (push_reload): Do not set it. + (push_replacement): Likewise. + (subst_reload): Remove dead code. + (copy_replacements): Remove assertion. + (copy_replacements_1): Do not handle SUBREG_LOC. + (move_replacements): Likewise. + (find_replacement): Remove dead code. Use reload_adjust_reg_for_mode. + Detect subregs via recursive descent instead of via SUBREG_LOC. + +2011-06-27 H.J. Lu <hongjiu.lu@intel.com> + + PR rtl-optimization/49114 + * reload1.c (gen_reload): Don't handle + (set reg:X (plus:X (subreg:X (reg:Y) 0) (const_int))). + +2011-06-27 H.J. Lu <hongjiu.lu@intel.com> + + PR rtl-optimization/48155 + * reload1.c (reload_plus_ok): Removed. + (gen_reload_chain_without_interm_reg_p): Updated. + (gen_reload): Likewise. + +2011-06-23 H.J. Lu <hongjiu.lu@intel.com> + + PR rtl-optimization/49088 + * combine.c (force_to_mode): Revert the last change. + +2011-06-22 H.J. Lu <hongjiu.lu@intel.com> + + PR rtl-optimization/49504 + * rtlanal.c (nonzero_bits1): Properly handle addition or + subtraction a pointer in Pmode if pointers extend unsigned. + +2011-06-15 H.J. Lu <hongjiu.lu@intel.com> + + PR middle-end/48016 + * explow.c (emit_stack_save): Don'ty adjust mode of stack save + area. + (update_nonlocal_goto_save_area): Use proper mode for stack save + area. + +2011-06-14 H.J. Lu <hongjiu.lu@intel.com> + + * config/i386/kfreebsd-gnu64.h (GLIBC_DYNAMIC_LINKERX32): New. + +2011-06-14 H.J. Lu <hongjiu.lu@intel.com> + + * config/i386/gnu-user64.h (LINK_SPEC): Use + GNU_USER_LINK_EMULATIONX32. + + * config/i386/kfreebsd-gnu64.h (GNU_USER_LINK_EMULATIONX32): New. + * config/i386/linux64.h (GNU_USER_LINK_EMULATIONX32): Likewise. + +2011-06-14 H.J. Lu <hongjiu.lu@intel.com> + + PR middle-end/47364 + * builtins.c (expand_builtin_strlen): Expand strlen to Pmode. + +2011-06-12 H.J. Lu <hongjiu.lu@intel.com> + + PR middle-end/47364 + * builtins.c (expand_builtin_strlen): Properly handle target + not in Pmode if POINTERS_EXTEND_UNSIGNED is defined. + +2011-06-07 H.J. Lu <hongjiu.lu@intel.com> + + * config/i386/gnu-user64.h (SPEC_64): Support x32. + (SPEC_32): Likewise. + (SPEC_X32): New. + (ASM_SPEC): Use SPEC_X32. + (LINK_SPEC): Likewise. + + * config/i386/i386.h (OPT_ARCH64): Support x32. + (OPT_ARCH32): Likewise. + +2011-06-07 H.J. Lu <hongjiu.lu@intel.com> + + * doc/invoke.texi: Use @option{} on -mx32, -m64 and -mx32. + +2011-06-07 H.J. Lu <hongjiu.lu@intel.com> + + * doc/install.texi: Document --enable-ia32 and --enable-x32. + +2011-06-06 H.J. Lu <hongjiu.lu@intel.com> + + * config.gcc: Replace i386/t-linuxx32 with i386/t-linux-x32. + + * config/i386/t-linuxx32: Renamed to ... + * config/i386/t-linux-x32: This. + +2011-06-05 H.J. Lu <hongjiu.lu@intel.com> + + * doc/invoke.texi: Document -mx32. + +2011-05-24 H.J. Lu <hongjiu.lu@intel.com> + + PR rtl-optimization/49114 + * reload1.c (gen_reload): Properly handle + (set reg:X (plus:X (subreg:X (reg:Y) 0) (const_int))) + +2011-05-21 H.J. Lu <hongjiu.lu@intel.com> + + PR rtl-optimization/49088 + * combine.c (force_to_mode): If X is narrower than MODE and we + want all the bits in X's mode, just use the operand when it + is CONST_INT. + +2011-05-20 H.J. Lu <hongjiu.lu@intel.com> + + PR target/48529 + * config/i386/i386.c (x86_output_mi_thunk): Use ptr_mode instead + of Pmode for vtable adjustment. + +2011-05-19 H.J. Lu <hongjiu.lu@intel.com> + + * config/i386/x86-64.h (SIZE_TYPE): Check TARGET_LP64 instead + of TARGET_64BIT. + (PTRDIFF_TYPE): Likewise. + +2011-05-17 H.J. Lu <hongjiu.lu@intel.com> + + * config/i386/i386.md (*call_vzeroupper): Disabled for TARGET_X32. + (*call): Likewise. + (*call_value_vzeroupper): Likewise. + (*call_value): Likewise. + (*call_rex64_ms_sysv_vzeroupper): Check TARGET_LP64 instead of + TARGET_64BIT. + (*call_rex64_ms_sysv"): Likewise. + (*call_value_rex64_ms_sysv_vzeroupper): Likewise. + (*call_value_rex64_ms_sysv): Likewise. + (*call_vzeroupper_x32): New. + (*call_x32): Likewise. + (*call_rex64_ms_sysv_vzeroupper_x32): Likewise. + (*call_rex64_ms_sysv_x32): Likewise. + (*call_value_vzeroupper_x32): Likewise. + (*call_value_x32): Likewise. + (*call_value_rex64_ms_sysv_vzeroupper_x3): Likewise. + (*call_value_rex64_ms_sysv_x32): Likewise. + (*call_1_rex64_x32): Removed. + +2011-05-13 H.J. Lu <hongjiu.lu@intel.com> + + PR target/47715 + * config/i386/i386.md (PTR64): New. + (*tls_global_dynamic_64): Rename to ... + (*tls_global_dynamic_64_<mode>): This. Put PTR64 on operand 1. + (tls_global_dynamic_64): Rename to ... + (tls_global_dynamic_64_<mode>): This. Put PTR64 on operand 1. + * config/i386/i386.c (legitimize_tls_address): Updated. + +2011-05-06 H.J. Lu <hongjiu.lu@intel.com> + + * config/i386/i386.c (ix86_promote_function_mode): Handle NULL + TYPE argument. + +2011-04-14 H.J. Lu <hongjiu.lu@intel.com> + + * config/i386/gnu-user64.h (ASM_SPEC): Support x32. + (LINK_SPEC): Likewise. + (TARGET_THREAD_SSP_OFFSET): Likewise. + (TARGET_THREAD_SPLIT_STACK_OFFSET): Likewise. + + * config/linux.h (LINUX_DYNAMIC_LINKERX32): Renamed to ... + (GNU_USER_DYNAMIC_LINKERX32): This. + +2011-04-06 H.J. Lu <hongjiu.lu@intel.com> + + PR middle-end/48440 + * expr.c (expand_expr_real_2): Get inner mode from op0 instead + of treeop0 for constant op0. + +2011-03-29 H.J. Lu <hongjiu.lu@intel.com> + + PR middle-end/47725 + PR target/48085 + * calls.c (precompute_register_parameters): Convert pointer to + TLS symbol if needed. + + * config/i386/i386.c (ix86_promote_function_mode): New. + (TARGET_PROMOTE_FUNCTION_MODE): Likewise. + +2011-03-29 H.J. Lu <hongjiu.lu@intel.com> + + PR middle-end/47725 + * combine.c (cant_combine_insn_p): Don't check zero/sign extended + hard registers. + +2011-03-28 H.J. Lu <hongjiu.lu@intel.com> + + PR target/47744 + * config/i386/i386.c (ix86_simplify_base_disp): Add symbol plus + constant support. + +2011-03-28 H.J. Lu <hongjiu.lu@intel.com> + + PR rtl-optimization/47958 + * reload.c (find_reloads): Don't put symbol reference in memory + in ptr_mode. + +2011-03-28 H.J. Lu <hongjiu.lu@intel.com> + + PR rtl-optimization/47502 + * combine.c (cant_combine_insn_p): Don't check asm statement. + +2011-03-27 H.J. Lu <hongjiu.lu@intel.com> + + PR middle-end/47364 + * config/i386/i386.md (strlen<mode>): Replace SWI48x with P. + +2011-03-21 H.J. Lu <hongjiu.lu@intel.com> + + PR target/48084 + * config/i386/i386.c (ix86_expand_builtin): Call + convert_memory_address. + +2011-03-21 H.J. Lu <hongjiu.lu@intel.com> + + PR target/48084 + * explow.c (copy_addr_to_reg): Don't convert to Pmode here. + +2011-03-17 H.J. Lu <hongjiu.lu@intel.com> + + PR target/47744 + * config/i386/i386.c (ix86_simplify_base_disp): Add ZERO_EXTEND + PLUS base support. + +2011-03-16 H.J. Lu <hongjiu.lu@intel.com> + + PR rtl-optimization/48155 + * reload1.c (reload_plus_ok): New. + (gen_reload_chain_without_interm_reg_p): Use it. + (gen_reload): Likewise. + +2011-03-16 H.J. Lu <hongjiu.lu@intel.com> + + PR middle-end/48016 + * function.c (expand_function_start): Properly store frame + pointer for non-local goto. + +2011-03-12 H.J. Lu <hongjiu.lu@intel.com> + + PR target/48084 + * explow.c (copy_addr_to_reg): Convert to Pmode if needed. + +2011-03-12 H.J. Lu <hongjiu.lu@intel.com> + + * config/i386/i386.md (*tls_global_dynamic_64): Don't generate + byte 0x66 before lea for TARGET_X32. + +2011-03-11 H.J. Lu <hongjiu.lu@intel.com> + + PR target/48084 + * config/i386/i386.c (ix86_expand_special_args_builtin): Convert + memory to Pmode if needed. + (ix86_expand_builtin): Likewise. + +2011-03-11 H.J. Lu <hongjiu.lu@intel.com> + + * config/i386/i386.md (*movabs<mode>_1): Only allow for + TARGET_LP64. + (*movabs<mode>_2): Likewise. + +2011-03-11 H.J. Lu <hongjiu.lu@intel.com> + + PR target/47446 + * config/i386/i386.md (*movdi_internal_rex64): Only allow moving + integer constants into 64bit registers for TARGET_X32. + + * config/i386/predicates.md (x86_64_immediate_operand): Always + allow the offsetted memory references for TARGET_X32. + (x86_64_zext_immediate_operand): Likewise. + +2011-03-07 H.J. Lu <hongjiu.lu@intel.com> + + PR middle-end/48016 + * explow.c (emit_stack_save): Adjust mode of stack save area. + +2011-03-06 H.J. Lu <hongjiu.lu@intel.com> + + * config/i386/predicates.md (aligned_operand): Check SUBREG_REG + for parts.index and parts.base. + +2011-03-06 H.J. Lu <hongjiu.lu@intel.com> + + * config/i386/i386.c (ix86_expand_call): Convert function address + to Pmode if needed. + +2011-03-06 H.J. Lu <hongjiu.lu@intel.com> + + PR other/48007 + * unwind-dw2.c (_Unwind_Context): Save call frame hard registers + as _Unwind_Word. + (_Unwind_GetGR): Get GR value as _Unwind_Word. + (_Unwind_SetGR): Set GR value as _Unwind_Word. + (_Unwind_SetGRValue): Likewise. + (_Unwind_GetGRPtr): Cast return to "void *". + (_Unwind_SetGRPtr): Cast pointer to _Unwind_Word. + (uw_install_context_1): Cast pointer to "void *". + +2011-03-05 H.J. Lu <hongjiu.lu@intel.com> + + * config/i386/linux-unwind.h (x86_64_fallback_frame_state): + Support x32 system call. + +2011-03-04 H.J. Lu <hongjiu.lu@intel.com> + + * config/i386/linux-unwind.h (x86_64_fallback_frame_state): Use + long long to check rt_sigreturn syscall. + +2011-03-02 H.J. Lu <hongjiu.lu@intel.com> + + PR rtl-optimization/47958 + * reload.c (find_reloads): Put symbol reference in memory + in ptr_mode. + +2011-03-01 H.J. Lu <hongjiu.lu@intel.com> + + PR target/47744 + * config/i386/i386.c (ix86_simplify_base_disp): Add PLUS base + support. + (ix86_decompose_address): Updated. + +2011-03-01 H.J. Lu <hongjiu.lu@intel.com> + + PR target/47926 + * config/i386/i386.c (ix86_trampoline_init): Use movl instead + of movabs for x32. + +2011-02-25 H.J. Lu <hongjiu.lu@intel.com> + + PR target/47715 + * config/i386/i386.c (get_thread_pointer): Use ptr_mode + instead of Pmode with UNSPEC_TP. + + * config/i386/i386.md (tp_seg): Removed. + (*load_tp_<mode>): Replace :P with :PTR. + (*add_tp_<mode>): Likewise. + (*load_tp_x32): New. + +2011-02-21 H.J. Lu <hongjiu.lu@intel.com> + + * config.gcc: Support --enable-ia32 for x86 Linux targets. + + * configure.ac: Support --enable-ia32. + * configure: Regenerated. + + * config/i386/t-linux64-x32: New. + +2011-02-20 H.J. Lu <hongjiu.lu@intel.com> + + * longlong.h (count_leading_zeros): Use long long builtin for + x86-64. + (count_trailing_zeros): Likewise. + +2011-02-19 H.J. Lu <hongjiu.lu@intel.com> + + PR middle-end/47364 + * builtins.c (expand_builtin_strlen): Properly handle target + not in Pmode. + + * config/i386/i386.c (ix86_expand_strlen): Revet the last change. + +2011-02-18 H.J. Lu <hongjiu.lu@intel.com> + + PR target/47744 + * config/i386/i386.c (ix86_simplify_base_disp): New. + (ix86_decompose_address): Use it for TARGET_X32 after reload + is completed. + +2011-02-17 H.J. Lu <hongjiu.lu@intel.com> + + PR target/47715 + * config/i386/i386.c (ix86_expand_move): Always use legitimized + plus const symbol reference. + +2011-02-16 H.J. Lu <hongjiu.lu@intel.com> + + * config/i386/linux64.h (GLIBC_DYNAMIC_LINKERX32): Update + ld.so path. + + * config/i386/t-linuxx32: Change x32 library path to libx32. + +2011-02-16 H.J. Lu <hongjiu.lu@intel.com> + + PR target/47766 + * config/i386/i386.md (PTR): New. + (stack_protect_set: Check TARGET_LP64 instead of TARGET_64BIT. + (stack_protect_test): Likewise. + (stack_protect_set_<mode>): Replace ":P" with ":PTR". + (stack_tls_protect_set_<mode>): Likewise. + (stack_tls_protect_test_<mode>): Likewise. + + * config/i386/linux64.h (TARGET_THREAD_SSP_OFFSET): Support + TARGET_X32. + (TARGET_THREAD_SPLIT_STACK_OFFSET): Likewise. + +2011-02-15 H.J. Lu <hongjiu.lu@intel.com> + + PR middle-end/47725 + * combine.c (cant_combine_insn_p): Check zero/sign extended + hard registers. + +2011-02-15 H.J. Lu <hongjiu.lu@intel.com> + + PR target/47744 + * config/i386/i386.c (ix86_decompose_address): Process + (reg + const) base for TARGET_X32. + +2011-02-14 H.J. Lu <hongjiu.lu@intel.com> + + * config/i386/i386.c (ix86_output_addr_vec_elt): Output + 64bit value for labels for TARGET_X32. + + * config/i386/i386.md (*tablejump_1): Don't disable for + TARGET_X32. + (*tablejump_1_x32): Removed. + +2011-02-14 H.J. Lu <hongjiu.lu@intel.com> + + PR middle-end/47727 + * explow.c (convert_memory_address_addr_space): Permute the + conversion and addition if one operand is a constant. + +2011-02-13 H.J. Lu <hongjiu.lu@intel.com> + + PR target/47715 + * config/i386/i386.c (ix86_expand_move): Update TLS symbol PIC + support. + +2011-02-13 H.J. Lu <hongjiu.lu@intel.com> + + PR target/47715 + * config/i386/i386.c (ix86_expand_move): Properly support TLS + symbol. + +2011-02-13 H.J. Lu <hongjiu.lu@intel.com> + + * config.gcc: Support --enable-x32 for x86 Linux targets. + + * configure.ac: Support --enable-x32. + * configure: Regenerated. + + * config/i386/t-linuxx32: New. + +2011-02-12 H.J. Lu <hongjiu.lu@intel.com> + + PR target/47715 + * config/i386/i386.md (*tls_global_dynamic_64): Remove DI on + operand 1. + (tls_global_dynamic_64): Likewise. + +2011-02-12 H.J. Lu <hongjiu.lu@intel.com> + + * config/i386/i386.md (A): Moved. + +2011-02-12 H.J. Lu <hongjiu.lu@intel.com> + + PR middle-end/47383 + * tree-ssa-address.c (addr_for_mem_ref): Use ptr_mode instead + of targetm.addr_space.address_mode. + +2011-02-11 H.J. Lu <hongjiu.lu@intel.com> + + PR middle-end/47383 + * config/i386/i386.c (ix86_decompose_address): Support 32bit + address in x32 mode. + (ix86_legitimate_address_p): Likewise. + (ix86_fixup_binary_operands): Likewise. + + * config/i386/i386.md (*lea_1_x32): New. + +2011-01-29 H.J. Lu <hongjiu.lu@intel.com> + + PR target/47537 + * config/i386/i386.c (ix86_expand_special_args_builtin): Convert + to Pmode if needed. + +2011-01-27 H.J. Lu <hongjiu.lu@intel.com> + + PR rtl-optimization/47502 + * combine.c (cant_combine_insn_p): Never combine asm statement. + +2011-01-25 H.J. Lu <hongjiu.lu@intel.com> + + PR target/47446 + * config/i386/i386.c (ix86_output_addr_diff_elt): Put back the + last TARGET_64BIT check. + +2011-01-25 H.J. Lu <hongjiu.lu@intel.com> + + PR middle-end/47449 + * fwprop.c (forward_propagate_subreg): Don't propagate hard + register. + +2011-01-24 H.J. Lu <hongjiu.lu@intel.com> + + PR middle-end/47449 + * fwprop.c (forward_propagate_subreg): Don't propagate zero/sign + extended hard register. + +2011-01-24 H.J. Lu <hongjiu.lu@intel.com> + + PR target/47446 + * config/i386/i386.c (ix86_output_addr_vec_elt): Check + TARGET_LP64 instead of TARGET_64BIT for ASM_QUAD. + (ix86_output_addr_diff_elt): Likewise. + +2011-01-21 H.J. Lu <hongjiu.lu@intel.com> + + PR target/47403 + * config/i386/i386.c (ix86_expand_move): Call convert_to_mode + on legitimize_tls_address return if needed. + +2011-01-20 H.J. Lu <hongjiu.lu@intel.com> + + PR target/47381 + * config/i386/i386.md (64bit LEA split): Replace nonmemory_operand + with x32_lea_nonmemory_operand. + +2011-01-20 H.J. Lu <hongjiu.lu@intel.com> + + PR target/47381 + * config/i386/constraints.md (Yl): New. + + * config/i386/i386.md (l): New. + (*add<mode>_1): Replace <i> with <l>. + (*addsi_1_zext): Replace "lYe" with "lYl". + +2011-01-20 H.J. Lu <hongjiu.lu@intel.com> + + PR target/47372 + * config/i386/i386.c (ix86_delegitimize_address): Call + simplify_gen_subreg for PIC with ptr_mode only if modes of + x and orig_x are different. + +2011-01-19 H.J. Lu <hongjiu.lu@intel.com> + + PR target/47369 + * config/i386/i386.c (ix86_expand_move): Allow ptr_mode for + symbolic operand with PIC. + +2011-01-19 H.J. Lu <hongjiu.lu@intel.com> + + PR target/47364 + * builtins.c (expand_builtin_strlen): Convert to Pmode if PAT + isn't in Pmode. + + * config/i386/i386.c (ix86_expand_strlen): Handle GET_MODE (out) + != Pmode. + +2011-01-19 H.J. Lu <hongjiu.lu@intel.com> + + PR target/47364 + * config/i386/i386.c (ix86_legitimize_address): Convert to + Pmode if needed. + +2011-01-19 H.J. Lu <hongjiu.lu@intel.com> + + * config/i386/i386.md (*addsi_1_zext): Replace general_operand + with x32_general_operand. Replace "i"/"g" with "Ye"/"rmYe". + (*addsi_2_zext): Likewise. + +2011-01-19 H.J. Lu <hongjiu.lu@intel.com> + + * config/i386/i386.md (i): Use "Ye" for SImode. + (g): Use "rmYe" for SImode. + (general_operand): Use x32_general_operand for SImode. + (general_szext_operand): Likewise. + (A): New. + (*movdi_internal_rex64): Use mov instead of movabs for + TARGET_X32. + (*movabs<mode>_1): Likewise. + (*movabs<mode>_2): Likewise. + (*movsi_internal): Replace 'ri' with 'rYs'. Use A instead of + DI for pic_32bit_operand. + (*lea_general_1): Replace immediate_operand and "i" with + x32_lea_immediate_operand and "Ye". + (*lea_general_1_zext): Likewise. + (*lea_general_3): Likewise. + (*lea_general_3_zext): Likewise. + (*lea_general_2): Replace nonmemory_operand and "i" with + x32_lea_nonmemory_operand and "Ye". + (*lea_general_2_zext): Likewise. + (*subsi_1_zext): Replace general_operand with x32_general_operand. + Replace "i"/"g" with "Ye"/"rmYe". + (*subsi_2_zext): Likewise. + (*subsi_3_zext): Likewise. + (*addsi3_carry_zext): Likewise. + (*subsi3_carry_zext): Likewise. + (*andsi_1): Likewise. + (*andsi_1_zext): Likewise. + (*andsi_2_zext): Likewise. + (*indirect_jump): Disabled for TARGET_X32. + (*tablejump_1): Likewise. + (*call_1_rex64): Likewise. + (set_got_offset_rex64): Likewise. + (*indirect_jump_x32): New. + (*tablejump_1_x32): Likewise. + (*call_1_rex64_x32): Likewise. + +2011-01-19 H.J. Lu <hongjiu.lu@intel.com> + + * config/i386/predicates.md (x32_lea_immediate_operand): New. + (x32_lea_nonmemory_operand): Likewise. + +2011-01-19 H.J. Lu <hongjiu.lu@intel.com> + + * config/i386/constraints.md (Ys): New. + (Ye): Likewise. + + * config/i386/predicates.md (x86_64_movabs_operand): Don't + allow nonmemory_operand for TARGET_X32. + (x32_store_immediate_operand): New. + (x32_general_operand): Likewise. + +2011-01-19 H.J. Lu <hongjiu.lu@intel.com> + + * config/linux.h (UCLIBC_DYNAMIC_LINKERX32): New. + (BIONIC_DYNAMIC_LINKERX32): Likewise. + (LINUX_DYNAMIC_LINKERX32): Likewise. + + * config/i386/linux64.h (GLIBC_DYNAMIC_LINKERX32): New. + (ASM_SPEC): Support -mx32. + (LINK_SPEC): Likewise. + + * config/i386/i386.c (override_options): Turn on + OPTION_MASK_ISA_64BIT for TARGET_X32. Only allow small and + small PIC models for TARGET_X32. + + * config/i386/i386.h (TARGET_X32): New. + (TARGET_LP64): Likewise. + (LONG_TYPE_SIZE): Likewise. + (POINTER_SIZE): Likewise. + (POINTERS_EXTEND_UNSIGNED): Likewise. + + * config/i386/i386.opt (m64): Negate -mx32. + (mx32): New. diff --git a/gcc/explow.c b/gcc/explow.c index beeab44e8ac..ecf29f2186c 100644 --- a/gcc/explow.c +++ b/gcc/explow.c @@ -384,18 +384,23 @@ convert_memory_address_addr_space (enum machine_mode to_mode ATTRIBUTE_UNUSED, case PLUS: case MULT: - /* For addition we can safely permute the conversion and addition - operation if one operand is a constant and converting the constant - does not change it or if one operand is a constant and we are - using a ptr_extend instruction (POINTERS_EXTEND_UNSIGNED < 0). + /* FIXME: For addition, we used to permute the conversion and + * addition operation only if one operand is a constant and + converting the constant does not change it or if one operand + is a constant and we are using a ptr_extend instruction + (POINTERS_EXTEND_UNSIGNED < 0) even if the resulting address + may overflow/underflow. We relax the condition to include + zero-extend (POINTERS_EXTEND_UNSIGNED > 0) since the other + parts of the compiler depend on it. See PR 49721. + We can always safely permute them if we are making the address narrower. */ if (GET_MODE_SIZE (to_mode) < GET_MODE_SIZE (from_mode) || (GET_CODE (x) == PLUS && CONST_INT_P (XEXP (x, 1)) - && (XEXP (x, 1) == convert_memory_address_addr_space - (to_mode, XEXP (x, 1), as) - || POINTERS_EXTEND_UNSIGNED < 0))) + && (POINTERS_EXTEND_UNSIGNED != 0 + || XEXP (x, 1) == convert_memory_address_addr_space + (to_mode, XEXP (x, 1), as)))) return gen_rtx_fmt_ee (GET_CODE (x), to_mode, convert_memory_address_addr_space (to_mode, XEXP (x, 0), as), diff --git a/gcc/testsuite/ChangeLog.x32 b/gcc/testsuite/ChangeLog.x32 new file mode 100644 index 00000000000..2ffba9142c8 --- /dev/null +++ b/gcc/testsuite/ChangeLog.x32 @@ -0,0 +1,851 @@ +2011-08-08 H.J. Lu <hongjiu.lu@intel.com> + + PR middle-end/49721 + * gfortran.dg/pr49721.f: New. + +2011-08-06 H.J. Lu <hongjiu.lu@intel.com> + + * gcc.target/i386/pr47381-[12].c: Moved to ... + * gcc.dg/pr47381-[12].c: Here. + + * gcc.target/i386/pr47381-3.c: Moved to ... + * gcc.target/i386/pr47381.c: Here. + +2011-08-06 H.J. Lu <hongjiu.lu@intel.com> + + * gcc.target/i386/pr47403-1.c: Moved to ... + * gcc.dg/tls/pr47715-5.c: This. + +2011-08-06 H.J. Lu <hongjiu.lu@intel.com> + + * gcc.target/i386/pr47372-[12].c: Moved to ... + * gcc.dg/pr47372-[12].c: Here. + +2011-08-06 H.J. Lu <hongjiu.lu@intel.com> + + * gcc.target/i386/pr47446-[12].c: Moved to ... + * gcc.dg/pr47446-[12].c: Here. + +2011-08-06 H.J. Lu <hongjiu.lu@intel.com> + + * gcc.target/i386/pr47715-[1234].c: Moved to ... + * gcc.dg/tls/pr47715-[1234].c.: Here. + +2011-08-06 H.J. Lu <hongjiu.lu@intel.com> + + * gcc.target/i386/pr47766.c: Moved to ... + * gcc.dg/pr47766.c: Here. + +2011-08-06 H.J. Lu <hongjiu.lu@intel.com> + + * gcc.target/i386/pr49860-1.c: Moved to ... + * gcc.dg/pr49860.c: This. + +2011-08-05 H.J. Lu <hongjiu.lu@intel.com> + + * gcc.target/i386/pr47369-1.c: Moved to ... + * gcc.dg/pr47369-1.c: Here. + +2011-08-05 H.J. Lu <hongjiu.lu@intel.com> + + * gcc.target/i386/pr47364-1.c: Moved to ... + * gcc.c-torture/compile/pr47364-1.c: Here. + + * gcc.target/i386/pr47364-2.c: Moved to ... + * gcc.c-torture/compile/pr47364-2.c: Here. + +2011-07-26 H.J. Lu <hongjiu.lu@intel.com> + + PR target/49860 + * gcc.target/i386/pr47446-3.c: Renamed to ... + * gcc.target/i386/pr49860-1.c: This. + +2011-07-21 H.J. Lu <hongjiu.lu@intel.com> + + * gcc/testsuite/gcc.target/i386/avx-vzeroupper-16.c: Only run + on lp64 targets. + * gcc/testsuite/gcc.target/i386/avx-vzeroupper-17.c: Likewise. + * gcc/testsuite/gcc.target/i386/avx-vzeroupper-18.c: Likewise. + * gcc/testsuite/gcc.target/i386/pr43662.c: Likewise. + * gcc/testsuite/gcc.target/i386/pr43869.c: Likewise. + + * gcc.target/x86_64/abi/callabi/callabi.exp: Check ilp32 + instead of ia32. + +2011-07-09 H.J. Lu <hongjiu.lu@intel.com> + + * gcc.dg/vect/costmodel/x86_64/x86_64-costmodel-vect.exp: Check + ia32. + * go.test/go-test.exp (go-set-goarch): Likewise. + +2011-07-09 H.J. Lu <hongjiu.lu@intel.com> + + * g++.dg/abi/bitfield3.C: Use { { i?86-*-* x86_64-*-* } && ia32 }. + * g++.dg/ext/attrib8.C: Likewise. + * g++.dg/ext/tmplattr1.C: Likewise. + * g++.dg/inherit/override-attribs.C: Likewise. + * g++.dg/opt/life1.C: Likewise. + * g++.dg/opt/nrv12.C: Likewise. + * g++.old-deja/g++.ext/attrib1.C: Likewise. + * g++.old-deja/g++.ext/attrib2.C: Likewise. + * g++.old-deja/g++.ext/attrib3.C: Likewise. + * g++.old-deja/g++.pt/asm2.C: Likewise. + * gcc.dg/tree-ssa/loop-28.c: Likewise. + * gcc.dg/tree-ssa/prefetch-3.c: Likewise. + * gcc.dg/tree-ssa/prefetch-4.c: Likewise. + * gcc.dg/tree-ssa/prefetch-5.c: Likewise. + * gcc.dg/tree-ssa/prefetch-6.c: Likewise. + * gcc.dg/tree-ssa/prefetch-7.c: Likewise. + * gcc.dg/tree-ssa/prefetch-8.c: Likewise. + * gcc.dg/tree-ssa/prefetch-9.c: Likewise. + * gcc.dg/tree-ssa/update-unroll-1.c: Likewise. + * gcc.misc-tests/i386-pf-3dnow-1.c: Likewise. + * gcc.misc-tests/i386-pf-athlon-1.c: Likewise. + * gcc.misc-tests/i386-pf-none-1.c: Likewise. + * gcc.misc-tests/i386-pf-sse-1.c: Likewise. + * gfortran.dg/compiler-directive_2.f: Likewise. + +2011-07-09 H.J. Lu <hongjiu.lu@intel.com> + + * gcc.dg/pr25023.c: Remove ||. + +2011-07-09 H.J. Lu <hongjiu.lu@intel.com> + + * gcc.dg/lower-subreg-1.c: Use dg-skip-if for x32. + +2011-07-09 H.J. Lu <hongjiu.lu@intel.com> + + * gcc.c-torture/compile/pr16566-2.c: Replace "x32 || lp64" with + "! { ia32 }". + * gcc.dg/torture/pr20314-2.c: Likewise. + * gcc.dg/tree-ssa/stdarg-2.c: Likewise. + * gcc.dg/tree-ssa/stdarg-3.c: Likewise. + * gcc.dg/tree-ssa/stdarg-4.c: Likewise. + * gcc.dg/tree-ssa/stdarg-5.c: Likewise. + * gcc.target/i386/amd64-abi-1.c: Likewise. + * gcc.target/i386/amd64-abi-2.c: Likewise. + * gcc.target/i386/amd64-abi-4.c: Likewise. + * gcc.target/i386/amd64-abi-5.c: Likewise. + * gcc.target/i386/amd64-abi-6.c: Likewise. + * gcc.target/i386/avx-vcvtsd2si-2.c: Likewise. + * gcc.target/i386/avx-vcvtsi2sd-2.c: Likewise. + * gcc.target/i386/avx-vcvtsi2ss-2.c: Likewise. + * gcc.target/i386/avx-vcvtss2si-2.c: Likewise. + * gcc.target/i386/avx-vcvttsd2si-2.c: Likewise. + * gcc.target/i386/avx-vcvttss2si-2.c: Likewise. + * gcc.target/i386/avx-vmovq-2.c: Likewise. + * gcc.target/i386/avx-vmovq-3.c: Likewise. + * gcc.target/i386/avx-vpextrq-1.c: Likewise. + * gcc.target/i386/avx-vpinsrq-1.c: Likewise. + * gcc.target/i386/avx-vzeroupper-16.c: Likewise. + * gcc.target/i386/avx-vzeroupper-17.c: Likewise. + * gcc.target/i386/avx-vzeroupper-18.c: Likewise. + * gcc.target/i386/bmi-2.c: Likewise. + * gcc.target/i386/bmi-5.c: Likewise. + * gcc.target/i386/cleanup-2.c: Likewise. + * gcc.target/i386/cmpxchg16b-1.c: Likewise. + * gcc.target/i386/crc32-2.c: Likewise. + * gcc.target/i386/divmod-7.c: Likewise. + * gcc.target/i386/divmod-8.c: Likewise. + * gcc.target/i386/fma3-builtin.c: Likewise. + * gcc.target/i386/fma3-fma.c: Likewise. + * gcc.target/i386/fma4-256-vector.c: Likewise. + * gcc.target/i386/fma4-builtin.c: Likewise. + * gcc.target/i386/fma4-fma-2.c: Likewise. + * gcc.target/i386/fma4-fma.c: Likewise. + * gcc.target/i386/fma4-vector-2.c: Likewise. + * gcc.target/i386/fma4-vector.c: Likewise. + * gcc.target/i386/funcspec-2.c: Likewise. + * gcc.target/i386/funcspec-6.c: Likewise. + * gcc.target/i386/gcc-have-sync-compare-and-swap-4.c: Likewise. + * gcc.target/i386/local.c: Likewise. + * gcc.target/i386/max-stack-align.c: Likewise. + * gcc.target/i386/movbe-2.c: Likewise. + * gcc.target/i386/pad-5b.c: Likewise. + * gcc.target/i386/pad-6b.c: Likewise. + * gcc.target/i386/pad-9.c: Likewise. + * gcc.target/i386/pr30961-1.c: Likewise. + * gcc.target/i386/pr32661-1.c: Likewise. + * gcc.target/i386/pr32708-2.c: Likewise. + * gcc.target/i386/pr32708-3.c: Likewise. + * gcc.target/i386/pr34256.c: Likewise. + * gcc.target/i386/pr36246.c: Likewise. + * gcc.target/i386/pr36786.c: Likewise. + * gcc.target/i386/pr39082-1.c: Likewise. + * gcc.target/i386/pr43662.c: Likewise. + * gcc.target/i386/pr43869.c: Likewise. + * gcc.target/i386/pr44942.c: Likewise. + * gcc.target/i386/pr45336-2.c: Likewise. + * gcc.target/i386/pr45336-4.c: Likewise. + * gcc.target/i386/pr45852.c: Likewise. + * gcc.target/i386/pr48037-1.c: Likewise. + * gcc.target/i386/rdfsbase-1.c: Likewise. + * gcc.target/i386/rdfsbase-2.c: Likewise. + * gcc.target/i386/rdgsbase-1.c: Likewise. + * gcc.target/i386/rdgsbase-2.c: Likewise. + * gcc.target/i386/rdrand-3.c: Likewise. + * gcc.target/i386/rotate-2.c: Likewise. + * gcc.target/i386/sse-cvtsi2ss-2.c: Likewise. + * gcc.target/i386/sse-cvtss2si-2.c: Likewise. + * gcc.target/i386/sse-cvttss2si-2.c: Likewise. + * gcc.target/i386/sse2-cvtsd2si-2.c: Likewise. + * gcc.target/i386/sse2-cvtsi2sd-2.c: Likewise. + * gcc.target/i386/sse2-cvttsd2si-2.c: Likewise. + * gcc.target/i386/sse2-init-v2di-2.c: Likewise. + * gcc.target/i386/sse2-movq-2.c: Likewise. + * gcc.target/i386/sse2-movq-3.c: Likewise. + * gcc.target/i386/sse4_1-pextrq.c: Likewise. + * gcc.target/i386/sse4_1-pinsrq.c: Likewise. + * gcc.target/i386/sse4_2-crc32q.c: Likewise. + * gcc.target/i386/sse4_2-popcntq.c: Likewise. + * gcc.target/i386/tbm-2.c: Likewise. + * gcc.target/i386/udivmod-7.c: Likewise. + * gcc.target/i386/udivmod-8.c: Likewise. + * gcc.target/i386/vararg-1.c: Likewise. + * gcc.target/i386/vararg-2.c: Likewise. + * gcc.target/i386/vectorize5.c: Likewise. + * gcc.target/i386/wrfsbase-1.c: Likewise. + * gcc.target/i386/wrfsbase-2.c: Likewise. + * gcc.target/i386/wrgsbase-1.c: Likewise. + * gcc.target/i386/wrgsbase-2.c: Likewise. + * gcc.target/i386/xop-pcmov.c: Likewise. + * gcc.target/i386/xop-pcmov2.c: Likewise. + * gcc.target/i386/xop-rotate1-vector.c: Likewise. + * gcc.target/i386/xop-rotate2-vector.c: Likewise. + * gcc.target/i386/xop-rotate3-vector.c: Likewise. + * gcc.target/i386/xop-shift1-vector.c: Likewise. + * gcc.target/i386/xop-shift2-vector.c: Likewise. + * gcc.target/i386/xop-shift3-vector.c: Likewise. + * gcc.target/i386/zee.c: Likewise. + * gfortran.dg/pr33794.f90: Likewise. + +2011-07-07 H.J. Lu <hongjiu.lu@intel.com> + + * gcc.dg/lower-subreg-1.c: Add i?86-*-* x86_64-*-* to x32 check. + * gcc.dg/pr44194-1.c: Likewise. + +2011-07-07 H.J. Lu <hongjiu.lu@intel.com> + + * gcc.dg/20020219-1.c: Use dg-skip-if for x32. + +2011-07-07 H.J. Lu <hongjiu.lu@intel.com> + + * gcc.dg/20020103-1.c: Don't check ia32. + +2011-07-05 H.J. Lu <hongjiu.lu@intel.com> + + PR middle-end/47383 + * gcc.dg/pr47383.c: New. + +2011-06-23 H.J. Lu <hongjiu.lu@intel.com> + + * gcc.target/i386/pr49504.c (main): Check correct return value. + +2011-06-22 H.J. Lu <hongjiu.lu@intel.com> + + PR rtl-optimization/49504 + * gcc.target/i386/pr49504.c: New. + +2011-06-15 H.J. Lu <hongjiu.lu@intel.com> + + * gcc.dg/pr44194-1.c: Also allow x32. + +2011-05-30 H.J. Lu <hongjiu.lu@intel.com> + + * gcc.target/i386/pr49095.c: Require ia32 instead of ilp32. + +2011-05-27 H.J. Lu <hongjiu.lu@intel.com> + + * objc.dg/torture/forward-1.m: Require ia32 instead of ilp32. + +2011-05-20 H.J. Lu <hongjiu.lu@intel.com> + + PR target/48529 + * gcc.dg/20020219-1.c: Disabled for x32. + +2011-04-16 H.J. Lu <hongjiu.lu@intel.com> + + * gcc.target/i386/avx-vinsertps-3.c: Require ia32 instead of + ilp32. + * gcc.target/i386/sse4_1-insertps-3.c: Likewise. + +2011-04-09 H.J. Lu <hongjiu.lu@intel.com> + + * gcc.target/i386/pr48389.c: Require ia32 instead of ilp32. + +2011-03-16 H.J. Lu <hongjiu.lu@intel.com> + + * g++.dg/opt/nrv12.C: Require ia32 instead of ilp32. + + * gcc.c-torture/compile/pr16566-2.c: Also allow x32. + * gcc.dg/torture/pr20314-2.c: Likewise. + * gfortran.dg/pr33794.f90: Likewise. + + * gcc.dg/lower-subreg-1.c: Don't allow x32. + + * gcc.dg/lto/pr47259_0.c: Don't require lp64. + + * gcc.dg/vect/costmodel/x86_64/x86_64-costmodel-vect.exp: Also + check x32. + +2011-03-15 H.J. Lu <hongjiu.lu@intel.com> + + * lib/target-supports.exp (check_effective_target_vect_cmdline_needed): + Also check x32. + +2011-03-15 H.J. Lu <hongjiu.lu@intel.com> + + * gcc.dg/20050503-1.c: Check ia32 instead of ilp32. + * gcc.dg/builtin-apply4.c: Likewise. + * gcc.dg/pr35045.c: Likewise. + * gcc.dg/pr36584.c: Likewise. + * gcc.dg/torture/fp-int-convert-float80-timode.c: Likewise. + * gcc.dg/torture/pr36891.c: Likewise. + * gcc.dg/tree-ssa/loop-28.c: Likewise. + +2011-03-15 H.J. Lu <hongjiu.lu@intel.com> + + * gcc.dg/tree-ssa/stdarg-2.c: Properly check ilp32, ia32 and x32. + * gcc.dg/tree-ssa/stdarg-3.c: Likewise. + * gcc.dg/tree-ssa/stdarg-4.c: Likewise. + * gcc.dg/tree-ssa/stdarg-5.c: Likewise. + +2011-03-15 H.J. Lu <hongjiu.lu@intel.com> + + * gcc.target/i386/pr48037-1.c: Also allow x32. + +2011-03-15 H.J. Lu <hongjiu.lu@intel.com> + + * c-c++-common/dfp/func-vararg-alternate-d128-2.c: Require ia32 + instead of ilp32. + * c-c++-common/dfp/func-vararg-mixed-2.c: Likewise. + * g++.dg/abi/bitfield3.C: Likewise. + * g++.dg/eh/pr38662.C: Likewise. + * g++.dg/ext/attrib36.C: Likewise. + * g++.dg/ext/attrib37.C: Likewise. + * g++.dg/ext/attrib8.C: Likewise. + * g++.dg/ext/tmplattr1.C: Likewise. + * g++.dg/inherit/override-attribs.C: Likewise. + * g++.dg/opt/inline9.C: Likewise. + * g++.dg/opt/life1.C: Likewise. + * g++.dg/opt/longbranch2.C: Likewise. + * g++.dg/opt/reg-stack4.C: Likewise. + * g++.dg/other/pr35504.C: Likewise. + * g++.dg/other/pr39496.C: Likewise. + * g++.dg/warn/pr15774-1.C: Likewise. + * g++.dg/warn/pr15774-2.C: Likewise. + * g++.old-deja/g++.ext/attrib1.C: Likewise. + * g++.old-deja/g++.ext/attrib2.C: Likewise. + * g++.old-deja/g++.ext/attrib3.C: Likewise. + * g++.old-deja/g++.pt/asm2.C: Likewise. + * gcc.c-torture/compile/20000804-1.c: Likewise. + * gcc.dg/20020103-1.c: Likewise. + * gcc.dg/20020108-1.c: Likewise. + * gcc.dg/20020122-2.c: Likewise. + * gcc.dg/20020122-3.c: Likewise. + * gcc.dg/20020206-1.c: Likewise. + * gcc.dg/20020310-1.c: Likewise. + * gcc.dg/20020411-1.c: Likewise. + * gcc.dg/20020418-2.c: Likewise. + * gcc.dg/20020426-2.c: Likewise. + * gcc.dg/20020517-1.c: Likewise. + * gcc.dg/20030204-1.c: Likewise. + * gcc.dg/20030826-2.c: Likewise. + * gcc.dg/20031102-1.c: Likewise. + * gcc.dg/20031202-1.c: Likewise. + * gcc.dg/20050111-1.c: Likewise. + * gcc.dg/array-init-1.c: Likewise. + * gcc.dg/dfp/pr31344.c: Likewise. + * gcc.dg/gomp/atomic-11.c: Likewise. + * gcc.dg/graphite/pr40281.c: Likewise. + * gcc.dg/ia64-sync-1.c: Likewise. + * gcc.dg/ia64-sync-2.c: Likewise. + * gcc.dg/ia64-sync-3.c: Likewise. + * gcc.dg/ia64-sync-4.c: Likewise. + * gcc.dg/ifcvt-fabs-1.c: Likewise. + * gcc.dg/invalid-call-1.c: Likewise. + * gcc.dg/loop-3.c: Likewise. + * gcc.dg/nested-calls-1.c: Likewise. + * gcc.dg/pr20017.c: Likewise. + * gcc.dg/pr25023.c: Likewise. + * gcc.dg/pr27671-2.c: Likewise. + * gcc.dg/pr32176.c: Likewise. + * gcc.dg/pr33676.c: Likewise. + * gcc.dg/pr36015.c: Likewise. + * gcc.dg/pr36998.c: Likewise. + * gcc.dg/pr37438.c: Likewise. + * gcc.dg/pr37908.c: Likewise. + * gcc.dg/pr41241.c: Likewise. + * gcc.dg/pr41340.c: Likewise. + * gcc.dg/pr44136.c: Likewise. + * gcc.dg/pr46212.c: Likewise. + * gcc.dg/prefetch-loop-arrays-1.c: Likewise. + * gcc.dg/setjmp-2.c: Likewise. + * gcc.dg/short-compare-1.c: Likewise. + * gcc.dg/short-compare-2.c: Likewise. + * gcc.dg/smod-1.c: Likewise. + * gcc.dg/sync-2.c: Likewise. + * gcc.dg/sync-3.c: Likewise. + * gcc.dg/tls/opt-1.c: Likewise. + * gcc.dg/tls/opt-2.c: Likewise. + * gcc.dg/tls/opt-3.c: Likewise. + * gcc.dg/torture/badshift.c: Likewise. + * gcc.dg/torture/pr38774.c: Likewise. + * gcc.dg/tree-ssa/prefetch-3.c: Likewise. + * gcc.dg/tree-ssa/prefetch-4.c: Likewise. + * gcc.dg/tree-ssa/prefetch-5.c: Likewise. + * gcc.dg/tree-ssa/prefetch-6.c: Likewise. + * gcc.dg/tree-ssa/prefetch-7.c: Likewise. + * gcc.dg/tree-ssa/prefetch-8.c: Likewise. + * gcc.dg/tree-ssa/prefetch-9.c: Likewise. + * gcc.dg/tree-ssa/stdarg-2.c: Likewise. + * gcc.dg/tree-ssa/stdarg-4.c: Likewise. + * gcc.dg/tree-ssa/update-unroll-1.c: Likewise. + * gcc.dg/unroll-1.c: Likewise. + * gcc.misc-tests/i386-pf-3dnow-1.c: Likewise. + * gcc.misc-tests/i386-pf-athlon-1.c: Likewise. + * gcc.misc-tests/i386-pf-none-1.c: Likewise. + * gcc.misc-tests/i386-pf-sse-1.c: Likewise. + * gfortran.dg/compiler-directive_2.f: Likewise. + * gfortran.dg/g77/20010216-1.f: Likewise. + * gfortran.dg/gomp/pr39152.f9: Likewise. + + * gcc.c-torture/execute/ieee/ieee.exp: Check ia32 instead of + ilp32. + * gcc.target/x86_64/abi/callabi/callabi.exp: Likewise. + +2011-03-12 H.J. Lu <hongjiu.lu@intel.com> + + * g++.dg/torture/stackalign/eh-fastcall-1.C: Require ia32 + instead of ilp32. + * g++.dg/torture/stackalign/eh-thiscall-1.C: Likewise. + * g++.dg/torture/stackalign/stdcall-1.C: Likewise. + * g++.dg/torture/stackalign/unwind-0.C: Likewise. + * g++.dg/torture/stackalign/unwind-1.C: Likewise. + * g++.dg/torture/stackalign/unwind-2.C: Likewise. + * g++.dg/torture/stackalign/unwind-3.C: Likewise. + * g++.dg/torture/stackalign/unwind-4.C: Likewise. + * g++.dg/torture/stackalign/unwind-5.C: Likewise. + * g++.dg/torture/stackalign/unwind-6.C: Likewise. + * gcc.dg/torture/stackalign/alloca-2.c: Likewise. + * gcc.dg/torture/stackalign/alloca-4.c: Likewise. + * gcc.dg/torture/stackalign/alloca-5.c: Likewise. + * gcc.dg/torture/stackalign/alloca-6.c: Likewise. + * gcc.dg/torture/stackalign/fastcall-1.c: Likewise. + * gcc.dg/torture/stackalign/push-1.c: Likewise. + * gcc.dg/torture/stackalign/regparm-1.c: Likewise. + * gcc.dg/torture/stackalign/thiscall-1.c: Likewise. + +2011-03-12 H.J. Lu <hongjiu.lu@intel.com> + + * gcc.target/i386/builtin-copysign.c: Remove __LP64__ check. + +2011-03-12 H.J. Lu <hongjiu.lu@intel.com> + + * gcc.target/i386/20000609-1.c: Require ia32 instead of ilp32. + * gcc.target/i386/20000720-1.c: Likewise. + * gcc.target/i386/20000724-1.c: Likewise. + * gcc.target/i386/20011107-1.c: Likewise. + * gcc.target/i386/20011119-1.c: Likewise. + * gcc.target/i386/20020201-3.c: Likewise. + * gcc.target/i386/20020218-1.c: Likewise. + * gcc.target/i386/20020729-1.c: Likewise. + * gcc.target/i386/20030926-1.c: Likewise. + * gcc.target/i386/20060125-1.c: Likewise. + * gcc.target/i386/20060125-2.c: Likewise. + * gcc.target/i386/20060512-1.c: Likewise. + * gcc.target/i386/20060512-2.c: Likewise. + * gcc.target/i386/20060512-3.c: Likewise. + * gcc.target/i386/20060512-4.c: Likewise. + * gcc.target/i386/387-1.c: Likewise. + * gcc.target/i386/387-2.c: Likewise. + * gcc.target/i386/387-5.c: Likewise. + * gcc.target/i386/387-6.c: Likewise. + * gcc.target/i386/980312-1.c: Likewise. + * gcc.target/i386/980313-1.c: Likewise. + * gcc.target/i386/990117-1.c: Likewise. + * gcc.target/i386/990424-1.c: Likewise. + * gcc.target/i386/990524-1.c: Likewise. + * gcc.target/i386/991129-1.c: Likewise. + * gcc.target/i386/991214-1.c: Likewise. + * gcc.target/i386/991230-1.c: Likewise. + * gcc.target/i386/addr-sel-1.c: Likewise. + * gcc.target/i386/aggregate-ret1.c: Likewise. + * gcc.target/i386/aggregate-ret2.c: Likewise. + * gcc.target/i386/align-main-3.c: Likewise. + * gcc.target/i386/asm-1.c: Likewise. + * gcc.target/i386/asm-3.c: Likewise. + * gcc.target/i386/asm-5.c: Likewise. + * gcc.target/i386/bitfield1.c: Likewise. + * gcc.target/i386/bitfield2.c: Likewise. + * gcc.target/i386/builtin-unreachable.c: Likewise. + * gcc.target/i386/cleanup-2.c: Likewise. + * gcc.target/i386/cmov8.c: Likewise. + * gcc.target/i386/compress-float-387-pic.c: Likewise. + * gcc.target/i386/compress-float-387.c: Likewise. + * gcc.target/i386/compress-float-sse-pic.c: Likewise. + * gcc.target/i386/compress-float-sse.c: Likewise. + * gcc.target/i386/crc32-3.c: Likewise. + * gcc.target/i386/fastcall-sseregparm.c: Likewise. + * gcc.target/i386/funcspec-1.c: Likewise. + * gcc.target/i386/funcspec-10.c: Likewise. + * gcc.target/i386/funcspec-11.c: Likewise. + * gcc.target/i386/funcspec-5.c: Likewise. + * gcc.target/i386/gcc-have-sync-compare-and-swap-1.c: Likewise. + * gcc.target/i386/gcc-have-sync-compare-and-swap-2.c: Likewise. + * gcc.target/i386/gcc-have-sync-compare-and-swap-3.c: Likewise. + * gcc.target/i386/incoming-1.c: Likewise. + * gcc.target/i386/incoming-10.c: Likewise. + * gcc.target/i386/incoming-11.c: Likewise. + * gcc.target/i386/incoming-12.c: Likewise. + * gcc.target/i386/incoming-13.c: Likewise. + * gcc.target/i386/incoming-14.c: Likewise. + * gcc.target/i386/incoming-15.c: Likewise. + * gcc.target/i386/incoming-2.c: Likewise. + * gcc.target/i386/incoming-3.c: Likewise. + * gcc.target/i386/incoming-4.c: Likewise. + * gcc.target/i386/incoming-5.c: Likewise. + * gcc.target/i386/incoming-6.c: Likewise. + * gcc.target/i386/incoming-7.c: Likewise. + * gcc.target/i386/incoming-8.c: Likewise. + * gcc.target/i386/incoming-9.c: Likewise. + * gcc.target/i386/lea.c: Likewise. + * gcc.target/i386/local.c: Likewise. + * gcc.target/i386/loop-1.c: Likewise. + * gcc.target/i386/loop-2.c: Likewise. + * gcc.target/i386/loop-3.c: Likewise. + * gcc.target/i386/memcpy-1.c: Likewise. + * gcc.target/i386/movbe-2.c: Likewise. + * gcc.target/i386/movq-2.c: Likewise. + * gcc.target/i386/movq.c: Likewise. + * gcc.target/i386/nrv1.c: Likewise. + * gcc.target/i386/pad-4.c: Likewise. + * gcc.target/i386/pad-5a.c: Likewise. + * gcc.target/i386/pad-6a.c: Likewise. + * gcc.target/i386/pad-7.c: Likewise. + * gcc.target/i386/pentium4-not-mull.c: Likewise. + * gcc.target/i386/pic-1.c: Likewise. + * gcc.target/i386/pr12092-1.c: Likewise. + * gcc.target/i386/pr12329.c: Likewise. + * gcc.target/i386/pr21518.: Likewise. + * gcc.target/i386/pr22362.c: Likewise. + * gcc.target/i386/pr22585.c: Likewise. + * gcc.target/i386/pr23098.c: Likewise. + * gcc.target/i386/pr25196.c: Likewise. + * gcc.target/i386/pr25293.c: Likewise. + * gcc.target/i386/pr25654.c: Likewise. + * gcc.target/i386/pr26449.c: Likewise. + * gcc.target/i386/pr26778.c: Likewise. + * gcc.target/i386/pr26826.c: Likewise. + * gcc.target/i386/pr27266.c: Likewise. + * gcc.target/i386/pr29978.c: Likewise. + * gcc.target/i386/pr30505.c: Likewise. + * gcc.target/i386/pr31628.c: Likewise. + * gcc.target/i386/pr32000-2.: Likewise. + * gcc.target/i386/pr34312.c: Likewise. + * gcc.target/i386/pr34522.c: Likewise. + * gcc.target/i386/pr35160.c: Likewise. + * gcc.target/i386/pr35281.c: Likewise. + * gcc.target/i386/pr37275.c: Likewise. + * gcc.target/i386/pr37843-3.c: Likewise. + * gcc.target/i386/pr37843-4.c: Likewise. + * gcc.target/i386/pr39431.c: Likewise. + * gcc.target/i386/pr39496.c: Likewise. + * gcc.target/i386/pr39543-2.c: Likewise. + * gcc.target/i386/pr40718.c: Likewise. + * gcc.target/i386/pr40906-1.c: Likewise. + * gcc.target/i386/pr40906-2.c: Likewise. + * gcc.target/i386/pr40906-3.c: Likewise. + * gcc.target/i386/pr40934.c: Likewise. + * gcc.target/i386/pr41900.c: Likewise. + * gcc.target/i386/pr42589.: Likewise. + * gcc.target/i386/pr43671.c: Likewise. + * gcc.target/i386/pr43766.: Likewise. + * gcc.target/i386/pr44948-2a.c: Likewise. + * gcc.target/i386/pr45234.c: Likewise. + * gcc.target/i386/pr46470.c: Likewise. + * gcc.target/i386/pr9771-1.c: Likewise. + * gcc.target/i386/regparm-stdcall.c: Likewise. + * gcc.target/i386/regparm.c: Likewise. + * gcc.target/i386/reload-1.c: Likewise. + * gcc.target/i386/sibcall-5.c: Likewise. + * gcc.target/i386/signbit-1.c: Likewise. + * gcc.target/i386/signbit-2.c: Likewise. + * gcc.target/i386/signbit-3.c: Likewise. + * gcc.target/i386/sse-5.c: Likewise. + * gcc.target/i386/sse-8.c: Likewise. + * gcc.target/i386/ssefn-1.c: Likewise. + * gcc.target/i386/ssefn-2.c: Likewise. + * gcc.target/i386/sseregparm-1.c: Likewise. + * gcc.target/i386/sseregparm-2.c: Likewise. + * gcc.target/i386/sseregparm-3.c: Likewise. + * gcc.target/i386/sseregparm-4.c: Likewise. + * gcc.target/i386/sseregparm-5.c: Likewise. + * gcc.target/i386/sseregparm-6.c: Likewise. + * gcc.target/i386/sseregparm-7.c: Likewise. + * gcc.target/i386/sseregparm-8.c: Likewise. + * gcc.target/i386/stack-realign.c: Likewise. + * gcc.target/i386/stack-usage-realign.c: Likewise. + * gcc.target/i386/stackalign/asm-1.c: Likewise. + * gcc.target/i386/stackalign/longlong-1.c: Likewise. + * gcc.target/i386/stackalign/longlong-2.c: Likewise. + * gcc.target/i386/stackalign/return-1.c: Likewise. + * gcc.target/i386/stackalign/return-2.c: Likewise. + * gcc.target/i386/tailcall-1.c: Likewise. + * gcc.target/i386/unroll-1.c: Likewise. + * gcc.target/i386/vararg-1.c: Likewise. + * gcc.target/i386/vararg-2.c: Likewise. + * gcc.target/i386/vect8-ret.c: Likewise. + * gcc.target/i386/wmul-1.c: Likewise. + * gcc.target/i386/wmul-2.c: Likewise. + + * gcc.target/i386/amd64-abi-1.c: Also allow x32. + * gcc.target/i386/amd64-abi-2.c: Likewise. + * gcc.target/i386/amd64-abi-4.c: Likewise. + * gcc.target/i386/amd64-abi-5.c: Likewise. + * gcc.target/i386/amd64-abi-6.c: Likewise. + * gcc.target/i386/avx-vcvtsd2si-2.c: Likewise. + * gcc.target/i386/avx-vcvtsi2sd-2.c: Likewise. + * gcc.target/i386/avx-vcvtsi2ss-2.c: Likewise. + * gcc.target/i386/avx-vcvtss2si-2.c: Likewise. + * gcc.target/i386/avx-vcvttsd2si-2.c: Likewise. + * gcc.target/i386/avx-vcvttss2si-2.c: Likewise. + * gcc.target/i386/avx-vmovd-2.c: Likewise. + * gcc.target/i386/avx-vmovq-2.c: Likewise. + * gcc.target/i386/avx-vmov3-2.c: Likewise. + * gcc.target/i386/avx-vpextrq-1.c: Likewise. + * gcc.target/i386/avx-vpinsrq-1.c: Likewise. + * gcc.target/i386/avx-vzeroupper-16.c: Likewise. + * gcc.target/i386/avx-vzeroupper-17.c: Likewise. + * gcc.target/i386/avx-vzeroupper-18.c: Likewise. + * gcc.target/i386/bmi-2.c: Likewise. + * gcc.target/i386/bmi-5.c: Likewise. + * gcc.target/i386/cmpxchg16b-1.c: Likewise. + * gcc.target/i386/crc32-2.c: Likewise. + * gcc.target/i386/divmod-7.c: Likewise. + * gcc.target/i386/divmod-8.c: Likewise. + * gcc.target/i386/fma3-builtin.c: Likewise. + * gcc.target/i386/fma3-fma.c: Likewise. + * gcc.target/i386/fma4-256-vector.c: Likewise. + * gcc.target/i386/fma4-builtin.c: Likewise. + * gcc.target/i386/fma4-fma-2.c: Likewise. + * gcc.target/i386/fma4-fma.c: Likewise. + * gcc.target/i386/fma4-vector-2.c: Likewise. + * gcc.target/i386/fma4-vector.c: Likewise. + * gcc.target/i386/funcspec-2.c: Likewise. + * gcc.target/i386/funcspec-6.c: Likewise. + * gcc.target/i386/gcc-have-sync-compare-and-swap-4.c: Likewise. + * gcc.target/i386/max-stack-align.c: Likewise. + * gcc.target/i386/pad-5b.c: Likewise. + * gcc.target/i386/pad-6b.c: Likewise. + * gcc.target/i386/pad-9.c: Likewise. + * gcc.target/i386/pr30961-1.c: Likewise. + * gcc.target/i386/pr32661-1.c: Likewise. + * gcc.target/i386/pr32708-2.c: Likewise. + * gcc.target/i386/pr32708-3.c: Likewise. + * gcc.target/i386/pr34256.c: Likewise. + * gcc.target/i386/pr36246.c: Likewise. + * gcc.target/i386/pr36786.c: Likewise. + * gcc.target/i386/pr39082-1.c: Likewise. + * gcc.target/i386/pr43662.c: Likewise. + * gcc.target/i386/pr43869.c: Likewise. + * gcc.target/i386/pr44942.c: Likewise. + * gcc.target/i386/pr45336-2.c: Likewise. + * gcc.target/i386/pr45336-4.c: Likewise. + * gcc.target/i386/pr45852.c: Likewise. + * gcc.target/i386/rdfsbase-1.c: Likewise. + * gcc.target/i386/rdfsbase-2.c: Likewise. + * gcc.target/i386/rdgsbase-1.c: Likewise. + * gcc.target/i386/rdgsbase-2.c: Likewise. + * gcc.target/i386/rdrand-3.c: Likewise. + * gcc.target/i386/rotate-2.c: Likewise. + * gcc.target/i386/sse-cvtsi2ss-2.c: Likewise. + * gcc.target/i386/sse-cvtss2si-2.c: Likewise. + * gcc.target/i386/sse-cvttss2si-2.c: Likewise. + * gcc.target/i386/sse2-cvtsd2si-2.c: Likewise. + * gcc.target/i386/sse2-cvtsi2sd-2.c: Likewise. + * gcc.target/i386/sse2-cvttsd2si-2.c: Likewise. + * gcc.target/i386/sse2-init-v2di-2.c: Likewise. + * gcc.target/i386/sse2-movq-2.c: Likewise. + * gcc.target/i386/sse2-movq-3.c: Likewise. + * gcc.target/i386/sse4_1-pextrq.c: Likewise. + * gcc.target/i386/sse4_1-pinsrq.c: Likewise. + * gcc.target/i386/sse4_2-crc32q.c: Likewise. + * gcc.target/i386/sse4_2-popcntq.c: Likewise. + * gcc.target/i386/tbm-2.c: Likewise. + * gcc.target/i386/udivmod-7.c: Likewise. + * gcc.target/i386/udivmod-8.c: Likewise. + * gcc.target/i386/vectorize5.: Likewise. + * gcc.target/i386/wrfsbase-1.c: Likewise. + * gcc.target/i386/wrfsbase-2.c: Likewise. + * gcc.target/i386/wrgsbase-1.c: Likewise. + * gcc.target/i386/wrgsbase-2.c: Likewise. + * gcc.target/i386/xop-pcmov.c: Likewise. + * gcc.target/i386/xop-pcmov2.c: Likewise. + * gcc.target/i386/xop-rotate1-vector.c: Likewise. + * gcc.target/i386/xop-rotate2-vector.c: Likewise. + * gcc.target/i386/xop-rotate3-vector.c: Likewise. + * gcc.target/i386/xop-shift1-vector.c: Likewise. + * gcc.target/i386/xop-shift2-vector.c: Likewise. + * gcc.target/i386/xop-shift3-vector.: Likewise. + * gcc.target/i386/zee.c: Likewise. + + * gcc.target/i386/clobbers.c: Check __x86_64__ instead of + __LP64__. + + * gcc.target/i386/pr39911.c (bar3): Avoid invalid pop on x32. + +2011-03-12 H.J. Lu <hongjiu.lu@intel.com> + + PR target/48084 + * gcc.target/i386/pr48084-5.c: New. + +2011-03-11 H.J. Lu <hongjiu.lu@intel.com> + + PR target/48084 + * gcc.target/i386/pr48084-1.c: New. + * gcc.target/i386/pr48084-2.c: Likewise. + * gcc.target/i386/pr48084-3.c: Likewise. + * gcc.target/i386/pr48084-4.c: Likewise. + +2011-03-11 H.J. Lu <hongjiu.lu@intel.com> + + * gcc.target/i386/stackalign/return-3.c: Require ia32 instead + of ilp32. + + * lib/target-supports.exp (check_effective_target_ia32): New. + +2011-03-11 H.J. Lu <hongjiu.lu@intel.com> + + PR target/47446 + * gcc.target/i386/pr47446-3.c: New. + +2011-03-06 H.J. Lu <hongjiu.lu@intel.com> + + * go.test/go-test.exp (go-set-goarch): Check x32. + + * lib/target-supports.exp (check_effective_target_x32): New. + +2011-03-02 H.J. Lu <hongjiu.lu@intel.com> + + PR rtl-optimization/47958 + * gcc.dg/torture/pr47958-1.c: New. + +2011-03-01 H.J. Lu <hongjiu.lu@intel.com> + + PR target/47744 + * gcc.dg/torture/pr47744-3.c: New. + +2011-02-19 H.J. Lu <hongjiu.lu@intel.com> + + PR middle-end/47364 + * gcc.dg/torture/pr47364-1.c: New. + +2011-02-18 H.J. Lu <hongjiu.lu@intel.com> + + PR target/47744 + * gcc.dg/torture/pr47744-2.c: New. + +2011-02-17 H.J. Lu <hongjiu.lu@intel.com> + + PR target/47715 + * gcc.target/i386/pr47715-4.c: New. + +2011-02-16 H.J. Lu <hongjiu.lu@intel.com> + + PR target/47766 + * gcc.target/i386/pr47766.c: New. + +2011-02-15 H.J. Lu <hongjiu.lu@intel.com> + + PR target/47744 + * gcc.dg/torture/pr47744-1.c: New. + +2011-02-14 H.J. Lu <hongjiu.lu@intel.com> + + PR middle-end/47727 + * gcc.dg/pr47727.c: New. + +2011-02-13 H.J. Lu <hongjiu.lu@intel.com> + + PR middle-end/47725 + * gcc.dg/torture/pr47725.c: New. + +2011-02-13 H.J. Lu <hongjiu.lu@intel.com> + + PR target/47715 + * gcc.target/i386/pr47715-3.c: New. + +2011-02-12 H.J. Lu <hongjiu.lu@intel.com> + + PR target/47715 + * gcc.target/i386/pr47715-1.c: New. + * gcc.target/i386/pr47715-2.c: Likewise. + +2011-02-08 H.J. Lu <hongjiu.lu@intel.com> + + PR middle-end/47383 + * gcc.dg/torture/pr47383.c: New. + +2011-01-27 H.J. Lu <hongjiu.lu@intel.com> + + PR rtl-optimization/47502 + * gcc.target/i386/pr47502-1.c: New. + * gcc.target/i386/pr47502-2.c: Likewise. + +2011-01-25 H.J. Lu <hongjiu.lu@intel.com> + + PR target/47446 + * gcc.target/i386/pr47446-2.c: New. + +2011-01-24 H.J. Lu <hongjiu.lu@intel.com> + + PR middle-end/47449 + * gcc.target/i386/pr47449.c: New. + +2011-01-24 H.J. Lu <hongjiu.lu@intel.com> + + PR target/47446 + * gcc.target/i386/pr47446-1.c: New. + +2011-01-21 H.J. Lu <hongjiu.lu@intel.com> + + PR target/47403 + * gcc.target/i386/pr47403-1.c: New. + +2011-01-20 H.J. Lu <hongjiu.lu@intel.com> + + PR target/47381 + * gcc.target/i386/pr47381-3.c: New. + +2011-01-20 H.J. Lu <hongjiu.lu@intel.com> + + PR target/47381 + * gcc.target/i386/pr47381-1.c: New. + * gcc.target/i386/pr47381-2.c: Likewise. + +2011-01-20 H.J. Lu <hongjiu.lu@intel.com> + + PR target/47372 + * gcc.target/i386/pr47372-1.c: New. + * gcc.target/i386/pr47372-2.c: Likewise. + +2011-01-19 H.J. Lu <hongjiu.lu@intel.com> + + PR target/47369 + * gcc.target/i386/pr47369-1.c: New. + +2011-01-19 H.J. Lu <hongjiu.lu@intel.com> + + PR target/47364 + * gcc.target/i386/pr47364-2.c: New. + +2011-01-19 H.J. Lu <hongjiu.lu@intel.com> + + * gcc.target/i386/pr47364.c: Moved to ... + * gcc.target/i386/pr47364-1.c: This. + +2011-01-19 H.J. Lu <hongjiu.lu@intel.com> + + PR target/47364 + * gcc.target/i386/pr47364.c: New. diff --git a/gcc/testsuite/gfortran.dg/pr49721.f b/gcc/testsuite/gfortran.dg/pr49721.f new file mode 100644 index 00000000000..39e2ed74ef7 --- /dev/null +++ b/gcc/testsuite/gfortran.dg/pr49721.f @@ -0,0 +1,35 @@ +! PR middle-end/49721 +! { dg-do compile } +! { dg-options "-O3 -funroll-loops" } + + subroutine midbloc6(c,a2,a2i,q) + parameter (ndim2=6) + parameter (ndim=3) + dimension ri(ndim2),cr(ndim2,ndim2),xj(ndim2,ndim2),q(*) + @,sai(ndim2,ndim2),cm(ndim2,ndim2),w(ndim2,ndim2) + dimension vr(ndim2,ndim2),vi(ndim2,ndim2),s1(ndim2,ndim2),p(ndim) + dimension xq(6),qb(2),qc(2),ifl(6),iplane(3) + save + call eig66(cr,rr,ri,vr,vi) + xq(i)=asin(ri(i))/x2pi + i9=6 + qb(1)=q(1)/x2pi + do 180 i=1,2 + do 170 j=1,6 + 120 if(xq(j)) 130,190,140 + 130 if(qb(i)-0.5d0) 160,150,150 + 140 if(qb(i)-0.5d0) 150,150,160 + 150 continue + tst=abs(abs(qb(i))-abs(xq(j))) + 160 continue + 170 continue + iplane(i)=k + 180 continue + 190 continue + n1=iplane(3) + if(i9.eq.6) then + z=vr(1,n1)*vi(2,n1)-vr(2,n1)*vi(1,n1)+vr(3,n1)*vi(4,n1)-vr(4,n1) + endif + sai(6,i)=vi(i,n1)/z + call dacond6(a2,zero) + end diff --git a/libgcc/ChangeLog.unwind b/libgcc/ChangeLog.unwind new file mode 100644 index 00000000000..23e5df77031 --- /dev/null +++ b/libgcc/ChangeLog.unwind @@ -0,0 +1,11 @@ +2011-06-28 H.J. Lu <hongjiu.lu@intel.com> + + * config/i386/value-unwind.h: New. + +2011-06-28 H.J. Lu <hongjiu.lu@intel.com> + + * config/i386/unique-unwind.h: Removed. + +2011-06-25 H.J. Lu <hongjiu.lu@intel.com> + + * config/i386/unique-unwind.h: New. diff --git a/libgcc/ChangeLog.x32 b/libgcc/ChangeLog.x32 new file mode 100644 index 00000000000..ce13cbe4893 --- /dev/null +++ b/libgcc/ChangeLog.x32 @@ -0,0 +1,31 @@ +2011-08-02 H.J. Lu <hongjiu.lu@intel.com> + + * config/i386/linux-unwind.h (RT_SIGRETURN_SYSCALL): Update x32 + system call number. + +2011-07-28 H.J. Lu <hongjiu.lu@intel.com> + + * config/i386/morestack.S (X86_64_SAVE_NEW_STACK_BOUNDARY): New. + Use X86_64_SAVE_NEW_STACK_BOUNDARY to save the new stack boundary + for x86-64. + +2011-03-15 H.J. Lu <hongjiu.lu@intel.com> + + * config/i386/morestack.S: Properly save the x32 new stack + boundary. + +2011-02-14 H.J. Lu <hongjiu.lu@intel.com> + + * config/i386/morestack.S: Replace __LP64___ with __LP64__. + +2011-02-13 H.J. Lu <hongjiu.lu@intel.com> + + * config/i386/morestack.S: Properly check __x86_64__ and + __LP64__. + +2010-01-19 H.J. Lu <hongjiu.lu@intel.com> + + * config/i386/64/sfp-machine.h (_FP_W_TYPE): Always use _WIN64 + version. + (_FP_WS_TYPE): Likewise. + (_FP_I_TYPE): Likewise. diff --git a/libgomp/ChangeLog.x32 b/libgomp/ChangeLog.x32 new file mode 100644 index 00000000000..6d83f1e2197 --- /dev/null +++ b/libgomp/ChangeLog.x32 @@ -0,0 +1,19 @@ +2011-07-28 H.J. Lu <hongjiu.lu@intel.com> + + * testsuite/lib/libgomp.exp (libgomp_init): Check ia32 instead of + x32. + +2011-03-15 H.J. Lu <hongjiu.lu@intel.com> + + * testsuite/libgomp.c/atomic-1.c: Require ia32 instead of ilp32. + * testsuite/libgomp.c/atomic-6.c: Likewise. + +2011-03-06 H.J. Lu <hongjiu.lu@intel.com> + + * testsuite/lib/libgomp.exp (libgomp_init): Don't add -march=i486 + for x32. + +2011-02-17 H.J. Lu <hongjiu.lu@intel.com> + + * config/linux/x86/futex.h: Check __x86_64__ instead of + __LP64__. diff --git a/libstdc++-v3/ChangeLog.x32 b/libstdc++-v3/ChangeLog.x32 new file mode 100644 index 00000000000..acedb3d34fe --- /dev/null +++ b/libstdc++-v3/ChangeLog.x32 @@ -0,0 +1,3 @@ +2011-05-20 H.J. Lu <hongjiu.lu@intel.com> + + * config/abi/post/x86_64-linux-gnu/x32/baseline_symbols.txt: Generated. |