diff options
| -rw-r--r-- | gcc/ChangeLog | 11 | ||||
| -rw-r--r-- | gcc/config.gcc | 2 | ||||
| -rw-r--r-- | gcc/config/rs6000/rs6000.c | 38 | ||||
| -rw-r--r-- | gcc/config/rs6000/rs6000.md | 3 | ||||
| -rw-r--r-- | gcc/config/rs6000/titan.md | 171 | ||||
| -rw-r--r-- | gcc/doc/invoke.texi | 2 |
6 files changed, 222 insertions, 5 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index d6fab50d08f..3c34fe9d180 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,14 @@ +2010-06-28 Philipp Tomsich <philipp.tomsich@theobroma-systems.com> + + * config.gcc (powerpc*-*-*): Handle titan. + * config/rs6000/rs6000.c (titan_cost): New costs. + (rs6000_override_options): Add "titan" to processor_target_table. + Add Titan to branch alignment logic. + Correctly set rs6000_cost for titan. + * config/rs6000/rs6000.md (cpu): Add titan. Include "titan.md". + * config/rs6000/titan.md: New file. + * doc/invoke.texi (RS/6000 and PowerPC Options): Document -mcpu=titan. + 2010-06-28 Nathan Froyd <froydnj@codesourcery.com> * tree-browser.c (TB_history_stack): Convert to a VEC. diff --git a/gcc/config.gcc b/gcc/config.gcc index 7ae54cca5fc..6dc074d8a88 100644 --- a/gcc/config.gcc +++ b/gcc/config.gcc @@ -3286,7 +3286,7 @@ case "${target}" in | 401 | 403 | 405 | 405fp | 440 | 440fp | 464 | 464fp \ | 476 | 476fp | 505 | 601 | 602 | 603 | 603e | ec603e \ | 604 | 604e | 620 | 630 | 740 | 750 | 7400 | 7450 \ - | a2 | e300c[23] | 854[08] | e500mc | e500mc64 \ + | a2 | e300c[23] | 854[08] | e500mc | e500mc64 | titan\ | 801 | 821 | 823 | 860 | 970 | G3 | G4 | G5 | cell) # OK ;; diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c index 485b077e89f..a09374079ca 100644 --- a/gcc/config/rs6000/rs6000.c +++ b/gcc/config/rs6000/rs6000.c @@ -838,6 +838,25 @@ struct processor_costs ppce500mc64_cost = { 1, /* prefetch streams /*/ }; +/* Instruction costs on AppliedMicro Titan processors. */ +static const +struct processor_costs titan_cost = { + COSTS_N_INSNS (5), /* mulsi */ + COSTS_N_INSNS (5), /* mulsi_const */ + COSTS_N_INSNS (5), /* mulsi_const9 */ + COSTS_N_INSNS (5), /* muldi */ + COSTS_N_INSNS (18), /* divsi */ + COSTS_N_INSNS (18), /* divdi */ + COSTS_N_INSNS (10), /* fp */ + COSTS_N_INSNS (10), /* dmul */ + COSTS_N_INSNS (46), /* sdiv */ + COSTS_N_INSNS (72), /* ddiv */ + 32, /* cache line size */ + 32, /* l1 cache */ + 512, /* l2 cache */ + 1, /* prefetch streams /*/ +}; + /* Instruction costs on POWER4 and POWER5 processors. */ static const struct processor_costs power4_cost = { @@ -2439,6 +2458,8 @@ rs6000_override_options (const char *default_cpu) {"G4", PROCESSOR_PPC7450, POWERPC_7400_MASK}, {"G5", PROCESSOR_POWER4, POWERPC_7400_MASK | MASK_PPC_GPOPT | MASK_MFCRF | MASK_POWERPC64}, + {"titan", PROCESSOR_TITAN, + POWERPC_BASE_MASK | MASK_MULHW | MASK_DLMZB}, {"power", PROCESSOR_POWER, MASK_POWER | MASK_MULTIPLE | MASK_STRING}, {"power2", PROCESSOR_POWER, MASK_POWER | MASK_POWER2 | MASK_MULTIPLE | MASK_STRING}, @@ -2882,6 +2903,12 @@ rs6000_override_options (const char *default_cpu) if (!rs6000_explicit_options.aix_struct_ret) aix_struct_return = (DEFAULT_ABI != ABI_V4 || DRAFT_V4_STRUCT_RET); +#if 0 + /* IBM XL compiler defaults to unsigned bitfields. */ + if (TARGET_XL_COMPAT) + flag_signed_bitfields = 0; +#endif + if (TARGET_LONG_DOUBLE_128 && !TARGET_IEEEQUAD) REAL_MODE_FORMAT (TFmode) = &ibm_extended_format; @@ -2899,8 +2926,10 @@ rs6000_override_options (const char *default_cpu) /* Set branch target alignment, if not optimizing for size. */ if (!optimize_size) { - /* Cell wants to be aligned 8byte for dual issue. */ - if (rs6000_cpu == PROCESSOR_CELL) + /* Cell wants to be aligned 8byte for dual issue. Titan wants to be + aligned 8byte to avoid misprediction by the branch predictor. */ + if (rs6000_cpu == PROCESSOR_TITAN + || rs6000_cpu == PROCESSOR_CELL) { if (align_functions <= 0) align_functions = 8; @@ -3024,6 +3053,10 @@ rs6000_override_options (const char *default_cpu) rs6000_cost = &ppce500mc64_cost; break; + case PROCESSOR_TITAN: + rs6000_cost = &titan_cost; + break; + case PROCESSOR_POWER4: case PROCESSOR_POWER5: rs6000_cost = &power4_cost; @@ -22514,6 +22547,7 @@ rs6000_issue_rate (void) case CPU_PPCE300C3: case CPU_PPCE500MC: case CPU_PPCE500MC64: + case CPU_TITAN: return 2; case CPU_RIOS2: case CPU_PPC476: diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md index b3faab8375d..02602a1f661 100644 --- a/gcc/config/rs6000/rs6000.md +++ b/gcc/config/rs6000/rs6000.md @@ -140,7 +140,7 @@ ;; Processor type -- this attribute must exactly match the processor_type ;; enumeration in rs6000.h. -(define_attr "cpu" "rios1,rios2,rs64a,mpccore,ppc403,ppc405,ppc440,ppc476,ppc601,ppc603,ppc604,ppc604e,ppc620,ppc630,ppc750,ppc7400,ppc7450,ppc8540,ppce300c2,ppce300c3,ppce500mc,ppce500mc64,power4,power5,power6,power7,cell,ppca2" +(define_attr "cpu" "rios1,rios2,rs64a,mpccore,ppc403,ppc405,ppc440,ppc476,ppc601,ppc603,ppc604,ppc604e,ppc620,ppc630,ppc750,ppc7400,ppc7450,ppc8540,ppce300c2,ppce300c3,ppce500mc,ppce500mc64,power4,power5,power6,power7,cell,ppca2,titan" (const (symbol_ref "rs6000_cpu_attr"))) @@ -175,6 +175,7 @@ (include "cell.md") (include "xfpu.md") (include "a2.md") +(include "titan.md") (include "predicates.md") (include "constraints.md") diff --git a/gcc/config/rs6000/titan.md b/gcc/config/rs6000/titan.md new file mode 100644 index 00000000000..744d7770f28 --- /dev/null +++ b/gcc/config/rs6000/titan.md @@ -0,0 +1,171 @@ +;; Pipeline description for the AppliedMicro Titan core. +;; Copyright (C) 2010 Free Software Foundation, Inc. +;; Contributed by Theobroma Systems Design und Consulting GmbH +;; +;; This file is part of GCC. +;; +;; GCC is free software; you can redistribute it and/or modify it +;; under the terms of the GNU General Public License as published +;; by the Free Software Foundation; either version 3, or (at your +;; option) any later version. +;; +;; GCC is distributed in the hope that it will be useful, but WITHOUT +;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY +;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public +;; License for more details. +;; +;; You should have received a copy of the GNU General Public License +;; along with GCC; see the file COPYING3. If not see +;; <http://www.gnu.org/licenses/>. + +;; AppliedMicro Titan core complex + +(automata_option "progress") + +(define_automaton "titan_core,titan_fpu,titan_fxu,titan_bpu,titan_lsu") +(define_cpu_unit "titan_issue_0,titan_issue_1" "titan_core") + +;; Some useful abbreviations. +(define_reservation "titan_issue" "titan_issue_0|titan_issue_1") + +;; === FXU scheduling === + +(define_cpu_unit "titan_fxu_sh,titan_fxu_wb" "titan_fxu") + +;; The 1-cycle adder executes add, addi, subf, neg, compare and trap +;; instructions. It provides its own, dedicated result-bus, so we +;; don't need the titan_fxu_wb reservation to complete. +(define_insn_reservation "titan_fxu_adder" 1 + (and (eq_attr "type" "cmp,fast_compare,trap") + (eq_attr "cpu" "titan")) + "titan_issue,titan_fxu_sh") + +;; Keep the titan_imul and titan_mulhw (half-word) rules in order, to +;; ensure the proper match: the half-word instructions are tagged as +;; imul3 only, whereas regular multiplys will always carry a imul tag. + +(define_insn_reservation "titan_imul" 5 + (and (eq_attr "type" "imul,imul2,imul_compare") + (eq_attr "cpu" "titan")) + "titan_issue,titan_fxu_sh,nothing*5,titan_fxu_wb") + +(define_insn_reservation "titan_mulhw" 4 + (and (eq_attr "type" "imul3") + (eq_attr "cpu" "titan")) + "titan_issue,titan_fxu_sh,nothing*4,titan_fxu_wb") + +(define_bypass 2 "titan_mulhw" "titan_mulhw") + +(define_insn_reservation "titan_fxu_shift_and_rotate" 2 + (and (eq_attr "type" "insert_word,shift,var_shift_rotate,cntlz") + (eq_attr "cpu" "titan")) + "titan_issue,titan_fxu_sh,nothing*2,titan_fxu_wb") + +;; We model the divider for the worst-case (i.e. a full 32-bit +;; divide). To model the bypass for byte-wise completion, a +;; define_bypass with a guard-function could be used... however, this +;; would be an optimization of doubtful value, as a large number of +;; divides will operate on 32-bit variables. + +;; To avoid an unmanagably large automata (generating the automata +;; would require well over 2GB in memory), we don't model the shared +;; result bus on this one. The divider-pipeline is thus modeled +;; through its latency and initial disptach bottlenecks (i.e. issue +;; slots and fxu scheduler availability) +(define_insn_reservation "titan_fxu_div" 34 + (and (eq_attr "type" "idiv") + (eq_attr "cpu" "titan")) + "titan_issue,titan_fxu_sh") + +(define_insn_reservation "titan_fxu_alu" 1 + (and (eq_attr "type" "integer,exts") + (eq_attr "cpu" "titan")) + "titan_issue,titan_fxu_sh,nothing,titan_fxu_wb") + +;; === BPU scheduling === + +(define_cpu_unit "titan_bpu_sh" "titan_bpu") + +(define_insn_reservation "titan_bpu" 2 + (and (eq_attr "type" "branch,jmpreg,cr_logical,delayed_cr") + (eq_attr "cpu" "titan")) + "titan_issue,titan_bpu_sh") + +;; === LSU scheduling === + +(define_cpu_unit "titan_lsu_sh" "titan_lsu") + +;; Loads. +(define_insn_reservation "titan_lsu_load" 3 + (and (eq_attr "type" "load,load_ext,load_ext_u,load_ext_ux,load_ux,load_u,\ + load_l,sync") + (eq_attr "cpu" "titan")) + "titan_issue,titan_lsu_sh") + +(define_insn_reservation "titan_lsu_fpload" 12 + (and (eq_attr "type" "fpload,fpload_ux,fpload_u") + (eq_attr "cpu" "titan")) + "titan_issue,titan_lsu_sh") + +;; Note that the isync is not clearly placed within any execution +;; unit. We've made the assumption that it will be running out of the +;; LSU, as msync is also executed within the LSU. +(define_insn_reservation "titan_lsu_sync" 20 + (and (eq_attr "type" "sync") + (eq_attr "cpu" "titan")) + "titan_issue,titan_lsu_sh*20") + +;; Stores. +(define_insn_reservation "titan_lsu_store" 12 + (and (eq_attr "type" "store,store_ux,store_u,store_c") + (eq_attr "cpu" "titan")) + "titan_issue,titan_lsu_sh") + +(define_insn_reservation "titan_lsu_fpstore" 12 + (and (eq_attr "type" "fpstore,fpstore_ux,fpstore_u") + (eq_attr "cpu" "titan")) + "titan_issue,titan_lsu_sh") + +;; === FPU scheduling === + +;; In order to keep the automaton for the Titan FPU efficient and +;; maintainable, we've kept in as concise as possible and created a +;; mapping for the main "choke points" only instead of modelling the +;; overall flow of instructions through the FP-pipeline(s). + +;; The key elements modelled are: +;; * each FP-instruction takes up one of the two issue slots +;; * the FPU runs at half the core frequency +;; * divides are not pipelined (but execute in a separate unit) +;; * the FPU has a shared result bus for all its units + +(define_cpu_unit "titan_fp0,titan_fpdiv,titan_fpwb" "titan_fpu") + +(define_insn_reservation "titan_fp_div_double" 72 + (and (eq_attr "type" "ddiv") + (eq_attr "cpu" "titan")) + "titan_issue,titan_fpdiv*72,titan_fpwb") + +(define_insn_reservation "titan_fp_div_single" 46 + (and (eq_attr "type" "sdiv") + (eq_attr "cpu" "titan")) + "titan_issue,titan_fpdiv*46,titan_fpwb") + +(define_insn_reservation "titan_fp_single" 12 + (and (eq_attr "fp_type" "fp_addsub_s,fp_mul_s,fp_maddsub_s") + (eq_attr "cpu" "titan")) + "titan_issue,titan_fp0*2,nothing*10,titan_fpwb") + +;; Make sure the "titan_fp" rule stays last, as it's a catch all for +;; double-precision and unclassified (e.g. fsel) FP-instructions +(define_insn_reservation "titan_fp" 10 + (and (eq_attr "type" "fpcompare,fp,dmul") + (eq_attr "cpu" "titan")) + "titan_issue,titan_fp0*2,nothing*8,titan_fpwb") + +;; Please note, that the non-pipelined FP-instructions "mcrfs", +;; "mtfsb0[.]", "mtfsb1[.]", "mtfsf[.]", "mtfsfi[.]" are not +;; accessible from regular language constructs (i.e. they are not used +;; by the code generator, except for special purpose sequences defined +;; in rs6000.md), no special provisions are made for these. + diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi index 48716c5283e..21740c1523c 100644 --- a/gcc/doc/invoke.texi +++ b/gcc/doc/invoke.texi @@ -14940,7 +14940,7 @@ Supported values for @var{cpu_type} are @samp{401}, @samp{403}, @samp{7400}, @samp{7450}, @samp{750}, @samp{801}, @samp{821}, @samp{823}, @samp{860}, @samp{970}, @samp{8540}, @samp{a2}, @samp{e300c2}, @samp{e300c3}, @samp{e500mc}, @samp{e500mc64}, @samp{ec603e}, @samp{G3}, -@samp{G4}, @samp{G5}, @samp{power}, @samp{power2}, @samp{power3}, +@samp{G4}, @samp{G5}, @samp{titan}, @samp{power}, @samp{power2}, @samp{power3}, @samp{power4}, @samp{power5}, @samp{power5+}, @samp{power6}, @samp{power6x}, @samp{power7}, @samp{common}, @samp{powerpc}, @samp{powerpc64}, @samp{rios}, @samp{rios1}, @samp{rios2}, @samp{rsc}, and @samp{rs64}. |