diff options
| -rw-r--r-- | gcc/ChangeLog.addr32 | 10 | ||||
| -rw-r--r-- | gcc/config/i386/i386.c | 10 | ||||
| -rw-r--r-- | gcc/config/i386/i386.md | 17 |
3 files changed, 14 insertions, 23 deletions
diff --git a/gcc/ChangeLog.addr32 b/gcc/ChangeLog.addr32 index af823665378..a1a758c4ba8 100644 --- a/gcc/ChangeLog.addr32 +++ b/gcc/ChangeLog.addr32 @@ -1,3 +1,13 @@ +2012-04-03 H.J. Lu <hongjiu.lu@intel.com> + + PR target/52848 + * config/i386/i386.c (legitimize_pic_address): Load UNSPEC_TP + into tp_mode register directly. + + * config/i386/i386.md (*load_tp_x32): Removed. + (*load_tp_x32_zext): Likewise. + (*load_tp_x32_<mode>): New. + 2012-03-12 H.J. Lu <hongjiu.lu@intel.com> * config/i386/i386.c (ix86_gen_tls_global_dynamic_64): New. diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c index 18172a10825..f37eb54a184 100644 --- a/gcc/config/i386/i386.c +++ b/gcc/config/i386/i386.c @@ -12550,15 +12550,7 @@ legitimize_pic_address (rtx orig, rtx reg) static rtx get_thread_pointer (enum machine_mode tp_mode, bool to_reg) { - rtx tp = gen_rtx_UNSPEC (ptr_mode, gen_rtvec (1, const0_rtx), UNSPEC_TP); - - if (GET_MODE (tp) != tp_mode) - { - gcc_assert (GET_MODE (tp) == SImode); - gcc_assert (tp_mode == DImode); - - tp = gen_rtx_ZERO_EXTEND (tp_mode, tp); - } + rtx tp = gen_rtx_UNSPEC (tp_mode, gen_rtvec (1, const0_rtx), UNSPEC_TP); if (to_reg) tp = copy_to_mode_reg (tp_mode, tp); diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md index 2d20a52bc06..ac6124ea8c3 100644 --- a/gcc/config/i386/i386.md +++ b/gcc/config/i386/i386.md @@ -12748,20 +12748,9 @@ (define_mode_attr tp_seg [(SI "gs") (DI "fs")]) ;; Load and add the thread base pointer from %<tp_seg>:0. -(define_insn "*load_tp_x32" - [(set (match_operand:SI 0 "register_operand" "=r") - (unspec:SI [(const_int 0)] UNSPEC_TP))] - "TARGET_X32" - "mov{l}\t{%%fs:0, %0|%0, DWORD PTR fs:0}" - [(set_attr "type" "imov") - (set_attr "modrm" "0") - (set_attr "length" "7") - (set_attr "memory" "load") - (set_attr "imm_disp" "false")]) - -(define_insn "*load_tp_x32_zext" - [(set (match_operand:DI 0 "register_operand" "=r") - (zero_extend:DI (unspec:SI [(const_int 0)] UNSPEC_TP)))] +(define_insn "*load_tp_x32_<mode>" + [(set (match_operand:SWI48x 0 "register_operand" "=r") + (unspec:SWI48x [(const_int 0)] UNSPEC_TP))] "TARGET_X32" "mov{l}\t{%%fs:0, %k0|%k0, DWORD PTR fs:0}" [(set_attr "type" "imov") |