diff options
| -rw-r--r-- | gcc/testsuite/ChangeLog | 5 | ||||
| -rw-r--r-- | gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvt_f16.c | 6 |
2 files changed, 9 insertions, 2 deletions
diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index c1282b357a8..3cb201ea59c 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,8 @@ +2015-10-05 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com> + + * gcc.target/aarch64/advsimd-intrinsics/vcvt_f16.c (TEST_MSG): Fix typo. + (exec_vcvt): Add comments. + 2015-10-04 Uros Bizjak <ubizjak@gmail.com> PR rtl-optimization/67447 diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvt_f16.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvt_f16.c index 48e50e18263..c3e4d4f6e16 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvt_f16.c +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvt_f16.c @@ -21,7 +21,7 @@ exec_vcvt (void) { clean_results (); -#define TEST_MSG vcvt_f32_f16 +#define TEST_MSG "vcvt_f32_f16" { VECT_VAR_DECL (buffer_src, float, 16, 4) [] = { 16.0, 15.0, 14.0, 13.0 }; @@ -39,7 +39,7 @@ exec_vcvt (void) clean_results (); -#define TEST_MSG vcvt_f16_f32 +#define TEST_MSG "vcvt_f16_f32" { VECT_VAR_DECL (buffer_src, float, 32, 4) [] = { 1.5, 2.5, 3.5, 4.5 }; DECL_VARIABLE (vector_src, float, 32, 4); @@ -54,6 +54,8 @@ exec_vcvt (void) } #undef TEST_MSG + /* We run more tests for AArch64 as the relevant intrinsics + do not exist on AArch32. */ #if defined (__aarch64__) clean_results (); |