diff options
| -rw-r--r-- | gcc/ChangeLog | 18 | ||||
| -rw-r--r-- | gcc/config/rx/rx-protos.h | 3 | ||||
| -rw-r--r-- | gcc/config/rx/rx.c | 184 | ||||
| -rw-r--r-- | gcc/config/rx/rx.h | 45 | ||||
| -rw-r--r-- | gcc/config/rx/rx.opt | 35 | ||||
| -rw-r--r-- | gcc/config/rx/t-rx | 10 | ||||
| -rw-r--r-- | gcc/doc/invoke.texi | 52 |
7 files changed, 195 insertions, 152 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index bb99a9fea27..a8b61a34540 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,21 @@ +2010-01-06 Nick Clifton <nickc@redhat.com> + + * config/rx/rx.h (enum rx_cpu_type): Add RX200. + (CC1_SPEC): Issue an error message if -mcpu=rx200 and -fpu are + used together. + (OVERRIDE_OPTIONS): Delete. + (OPTIMIZATION_OPTIONS): Define. + (ALLOW_RX_FPU_INSNS): Define only in terms of -fpu option. + * config/rx/rx.c (rx_handle_option): Issue an error message if + -mcpu=rx200 and -fpu are used together. + (rx_set_optimization_options): New function. Issue an error + message if an optimization attribute attempts to reset the FPU/ + math optimization pairing. + * config/rx/rx-protos.h (rx_set_optimization_options): Prototype. + * config/rx/rx.opt: Set the default to 32-bit doubles. + * config/rx/t-rx: Add multilibs for -nofpu option. + * doc/invoke.texi: Update documentation of RX options. + 2010-01-06 Richard Guenther <rguenther@suse.de> * tree-ssa-pre.c (name_to_id): New global. diff --git a/gcc/config/rx/rx-protos.h b/gcc/config/rx/rx-protos.h index 5c37fe0a83c..f5ef51108e1 100644 --- a/gcc/config/rx/rx-protos.h +++ b/gcc/config/rx/rx-protos.h @@ -1,5 +1,5 @@ /* Exported function prototypes from the Renesas RX backend. - Copyright (C) 2008, 2009 Free Software Foundation, Inc. + Copyright (C) 2008, 2009, 2010 Free Software Foundation, Inc. Contributed by Red Hat. This file is part of GCC. @@ -28,6 +28,7 @@ extern void rx_conditional_register_usage (void); extern void rx_expand_prologue (void); extern int rx_initial_elimination_offset (int, int); +extern void rx_set_optimization_options (void); #ifdef RTX_CODE extern void rx_emit_stack_popm (rtx *, bool); diff --git a/gcc/config/rx/rx.c b/gcc/config/rx/rx.c index ce13217df11..b8d4619427b 100644 --- a/gcc/config/rx/rx.c +++ b/gcc/config/rx/rx.c @@ -1,5 +1,5 @@ /* Subroutines used for code generation on Renesas RX processors. - Copyright (C) 2008, 2009 Free Software Foundation, Inc. + Copyright (C) 2008, 2009, 2010 Free Software Foundation, Inc. Contributed by Red Hat. This file is part of GCC. @@ -422,7 +422,10 @@ rx_print_operand (FILE * file, rtx op, int letter) case 0xb: fprintf (file, "fintv"); break; case 0xc: fprintf (file, "intb"); break; default: - gcc_unreachable (); + warning (0, "unreocgnized control register number: %d - using 'psw'", + INTVAL (op)); + fprintf (file, "psw"); + break; } break; @@ -2115,6 +2118,101 @@ const struct attribute_spec rx_attribute_table[] = { NULL, 0, 0, false, false, false, NULL } }; +/* Extra processing for target specific command line options. */ + +static bool +rx_handle_option (size_t code, const char * arg ATTRIBUTE_UNUSED, int value) +{ + switch (code) + { + case OPT_mint_register_: + switch (value) + { + case 4: + fixed_regs[10] = call_used_regs [10] = 1; + /* Fall through. */ + case 3: + fixed_regs[11] = call_used_regs [11] = 1; + /* Fall through. */ + case 2: + fixed_regs[12] = call_used_regs [12] = 1; + /* Fall through. */ + case 1: + fixed_regs[13] = call_used_regs [13] = 1; + /* Fall through. */ + case 0: + return true; + default: + return false; + } + break; + + case OPT_mmax_constant_size_: + /* Make sure that the -mmax-constant_size option is in range. */ + return value >= 0 && value <= 4; + + case OPT_mcpu_: + case OPT_patch_: + if (strcasecmp (arg, "RX610") == 0) + rx_cpu_type = RX610; + else if (strcasecmp (arg, "RX200") == 0) + { + target_flags |= MASK_NO_USE_FPU; + rx_cpu_type = RX200; + } + else if (strcasecmp (arg, "RX600") != 0) + warning (0, "unrecognized argument '%s' to -mcpu= option", arg); + break; + + case OPT_fpu: + if (rx_cpu_type == RX200) + error ("The RX200 cpu does not have FPU hardware"); + break; + + default: + break; + } + + return true; +} + +void +rx_set_optimization_options (void) +{ + static bool first_time = TRUE; + static bool saved_allow_rx_fpu = TRUE; + + if (first_time) + { + /* If this is the first time through and the user has not disabled + the use of RX FPU hardware then enable unsafe math optimizations, + since the FPU instructions themselves are unsafe. */ + if (TARGET_USE_FPU) + set_fast_math_flags (true); + + /* FIXME: For some unknown reason LTO compression is not working, + at least on my local system. So set the default compression + level to none, for now. */ + if (flag_lto_compression_level == -1) + flag_lto_compression_level = 0; + + saved_allow_rx_fpu = ALLOW_RX_FPU_INSNS; + first_time = FALSE; + } + else + { + /* Alert the user if they are changing the optimization options + to use IEEE compliant floating point arithmetic with RX FPU insns. */ + if (TARGET_USE_FPU + && ! fast_math_flags_set_p ()) + warning (0, "RX FPU instructions are not IEEE compliant"); + + if (saved_allow_rx_fpu != ALLOW_RX_FPU_INSNS) + error ("Changing the FPU insns/math optimizations pairing is not supported"); + } +} + + static bool rx_allocate_stack_slots_for_args (void) { @@ -2268,88 +2366,6 @@ rx_is_legitimate_constant (rtx x) ( 1 << (rx_max_constant_size * 8))); } -/* This is a tri-state variable. The default value of 0 means that the user - has specified neither -mfpu nor -mnofpu on the command line. In this case - the selection of RX FPU instructions is entirely based upon the size of - the floating point object and whether unsafe math optimizations were - enabled. If 32-bit doubles have been enabled then both floats and doubles - can make use of FPU instructions, otherwise only floats may do so. - - If the value is 1 then the user has specified -mfpu and the FPU - instructions should be used. Unsafe math optimizations will automatically - be enabled and doubles set to 32-bits. If the value is -1 then -mnofpu - has been specified and FPU instructions will not be used, even if unsafe - math optimizations have been enabled. */ -int rx_enable_fpu = 0; - -/* Extra processing for target specific command line options. */ - -static bool -rx_handle_option (size_t code, const char * arg ATTRIBUTE_UNUSED, int value) -{ - switch (code) - { - /* -mfpu enables the use of RX FPU instructions. This implies the use - of 32-bit doubles and also the enabling of fast math optimizations. - (Since the RX FPU instructions are not IEEE compliant). The -mnofpu - option disables the use of RX FPU instructions, but does not make - place any constraints on the size of doubles or the use of fast math - optimizations. - - The selection of 32-bit vs 64-bit doubles is handled by the setting - of the 32BIT_DOUBLES mask in the rx.opt file. Enabling fast math - optimizations is performed in OVERRIDE_OPTIONS since if it was done - here it could be overridden by a -fno-fast-math option specified - *earlier* on the command line. (Target specific options are - processed before generic ones). */ - case OPT_fpu: - rx_enable_fpu = 1; - break; - - case OPT_nofpu: - rx_enable_fpu = -1; - break; - - case OPT_mint_register_: - switch (value) - { - case 4: - fixed_regs[10] = call_used_regs [10] = 1; - /* Fall through. */ - case 3: - fixed_regs[11] = call_used_regs [11] = 1; - /* Fall through. */ - case 2: - fixed_regs[12] = call_used_regs [12] = 1; - /* Fall through. */ - case 1: - fixed_regs[13] = call_used_regs [13] = 1; - /* Fall through. */ - case 0: - return true; - default: - return false; - } - break; - - case OPT_mmax_constant_size_: - /* Make sure that the -mmax-constant_size option is in range. */ - return IN_RANGE (value, 0, 4); - - case OPT_mcpu_: - case OPT_patch_: - if (strcasecmp (arg, "RX610") == 0) - rx_cpu_type = RX610; - /* FIXME: Should we check for non-RX cpu names here ? */ - break; - - default: - break; - } - - return true; -} - static int rx_address_cost (rtx addr, bool speed) { diff --git a/gcc/config/rx/rx.h b/gcc/config/rx/rx.h index bb7cf7f1e3e..a053340c48a 100644 --- a/gcc/config/rx/rx.h +++ b/gcc/config/rx/rx.h @@ -1,5 +1,5 @@ /* GCC backend definitions for the Renesas RX processor. - Copyright (C) 2008, 2009 Free Software Foundation, Inc. + Copyright (C) 2008, 2009, 2010 Free Software Foundation, Inc. Contributed by Red Hat. This file is part of GCC. @@ -34,10 +34,10 @@ else \ builtin_define ("__RX_LITTLE_ENDIAN__");\ \ - if (TARGET_32BIT_DOUBLES) \ - builtin_define ("__RX_32BIT_DOUBLES__");\ - else \ + if (TARGET_64BIT_DOUBLES) \ builtin_define ("__RX_64BIT_DOUBLES__");\ + else \ + builtin_define ("__RX_32BIT_DOUBLES__");\ \ if (ALLOW_RX_FPU_INSNS) \ builtin_define ("__RX_FPU_INSNS__"); \ @@ -52,13 +52,16 @@ enum rx_cpu_types { RX600, - RX610 + RX610, + RX200 }; extern enum rx_cpu_types rx_cpu_type; #undef CC1_SPEC -#define CC1_SPEC "%{mas100-syntax:%{gdwarf*:%e-mas100-syntax is incompatible with -gdwarf}}" +#define CC1_SPEC "\ + %{mas100-syntax:%{gdwarf*:%e-mas100-syntax is incompatible with -gdwarf}} \ + %{mcpu=rx200:%{fpu:%erx200 cpu does not have FPU hardware}}" #undef STARTFILE_SPEC #define STARTFILE_SPEC "%{pg:gcrt0.o%s}%{!pg:crt0.o%s} crtbegin.o%s" @@ -69,8 +72,8 @@ extern enum rx_cpu_types rx_cpu_type; #undef ASM_SPEC #define ASM_SPEC "\ %{mbig-endian-data:-mbig-endian-data} \ -%{m32bit-doubles:-m32bit-doubles} \ -%{!m32bit-doubles:-m64bit-doubles} \ +%{m64bit-doubles:-m64bit-doubles} \ +%{!m64bit-doubles:-m32bit-doubles} \ %{msmall-data-limit*:-msmall-data-limit} \ %{mrelax:-relax} \ " @@ -106,7 +109,7 @@ extern enum rx_cpu_types rx_cpu_type; #define LONG_LONG_TYPE_SIZE 64 #define FLOAT_TYPE_SIZE 32 -#define DOUBLE_TYPE_SIZE (TARGET_32BIT_DOUBLES ? 32 : 64) +#define DOUBLE_TYPE_SIZE (TARGET_64BIT_DOUBLES ? 64 : 32) #define LONG_DOUBLE_TYPE_SIZE DOUBLE_TYPE_SIZE #ifdef __RX_32BIT_DOUBLES__ @@ -636,24 +639,14 @@ extern int rx_float_compare_mode; #define ARG_POINTER_CFA_OFFSET(FNDECL) 4 #define FRAME_POINTER_CFA_OFFSET(FNDECL) 4 -extern int rx_enable_fpu; +/* Translate -nofpu into -mnofpu so that it gets passed from gcc to cc1. */ +#define TARGET_OPTION_TRANSLATE_TABLE \ + {"-nofpu", "-mnofpu" } -/* For some unknown reason LTO compression is not working, at - least on my local system. So set the default compression - level to none, for now. +#define OPTIMIZATION_OPTIONS(LEVEL,SIZE) \ + rx_set_optimization_options () - For an explanation of rx_flag_no_fpu see rx_handle_option(). */ -#define OVERRIDE_OPTIONS \ - do \ - { \ - if (flag_lto_compression_level == -1) \ - flag_lto_compression_level = 0; \ - \ - if (rx_enable_fpu == 1) \ - set_fast_math_flags (true); \ - } \ - while (0) +#define TARGET_USE_FPU (! TARGET_NO_USE_FPU) /* This macro is used to decide when RX FPU instructions can be used. */ -#define ALLOW_RX_FPU_INSNS ((rx_enable_fpu != -1) \ - && flag_unsafe_math_optimizations) +#define ALLOW_RX_FPU_INSNS (TARGET_USE_FPU) diff --git a/gcc/config/rx/rx.opt b/gcc/config/rx/rx.opt index 768d565b478..9615556576d 100644 --- a/gcc/config/rx/rx.opt +++ b/gcc/config/rx/rx.opt @@ -1,5 +1,5 @@ ; Command line options for the Renesas RX port of GCC. -; Copyright (C) 2008, 2009 Free Software Foundation, Inc. +; Copyright (C) 2008, 2009, 2010 Free Software Foundation, Inc. ; Contributed by Red Hat. ; ; This file is part of GCC. @@ -19,26 +19,31 @@ ; <http://www.gnu.org/licenses/>. ;--------------------------------------------------- -m32bit-doubles -Target RejectNegative Mask(32BIT_DOUBLES) -Stores doubles in 32 bits. +; The default is -fpu -m32bit-doubles. m64bit-doubles -Target RejectNegative InverseMask(32BIT_DOUBLES) -Store doubles in 64 bits. This is the default. +Target RejectNegative Mask(64BIT_DOUBLES) Report +Store doubles in 64 bits. -fpu -Target RejectNegative Mask(32BIT_DOUBLES) MaskExists -Enable the use of RX FPU instructions. +m32bit-doubles +Target RejectNegative InverseMask(64BIT_DOUBLES) Report +Stores doubles in 32 bits. This is the default. nofpu -Target RejectNegative InverseMask(32BIT_DOUBLES) MaskExists -Disable the use of RX FPU instructions. +Target RejectNegative Mask(NO_USE_FPU) Report +Disable the use of RX FPU instructions. + +mnofpu +Target RejectNegative Mask(NO_USE_FPU) MaskExists Undocumented + +fpu +Target RejectNegative InverseMask(NO_USE_FPU) Report +Enable the use of RX FPU instructions. This is the default. ;--------------------------------------------------- mcpu= -Target RejectNegative Joined Var(rx_cpu_name) +Target RejectNegative Joined Var(rx_cpu_name) Report Specify the target RX cpu type. patch= @@ -48,11 +53,11 @@ Alias for -mcpu. ;--------------------------------------------------- mbig-endian-data -Target RejectNegative Mask(BIG_ENDIAN_DATA) +Target RejectNegative Mask(BIG_ENDIAN_DATA) Report Data is stored in big-endian format. mlittle-endian-data -Target RejectNegative InverseMask(BIG_ENDIAN_DATA) +Target RejectNegative InverseMask(BIG_ENDIAN_DATA) Report Data is stored in little-endian format. (Default). ;--------------------------------------------------- @@ -70,7 +75,7 @@ Use the simulator runtime. ;--------------------------------------------------- mas100-syntax -Target Mask(AS100_SYNTAX) +Target Mask(AS100_SYNTAX) Report Generate assembler output that is compatible with the Renesas AS100 assembler. This may restrict some of the compiler's capabilities. The default is to generate GAS compatable syntax. ;--------------------------------------------------- diff --git a/gcc/config/rx/t-rx b/gcc/config/rx/t-rx index eb1ca48d3a3..7990bcfaa47 100644 --- a/gcc/config/rx/t-rx +++ b/gcc/config/rx/t-rx @@ -1,5 +1,5 @@ # Makefile fragment for building GCC for the Renesas RX target. -# Copyright (C) 2008, 2009 Free Software Foundation, Inc. +# Copyright (C) 2008, 2009, 2010 Free Software Foundation, Inc. # Contributed by Red Hat. # # This file is part of GCC. @@ -20,9 +20,11 @@ # Enable multilibs: -MULTILIB_OPTIONS = m32bit-doubles mbig-endian-data -MULTILIB_DIRNAMES = 32fp big-endian-data -MULTILIB_MATCHES = m32bit-doubles=fpu +MULTILIB_OPTIONS = m64bit-doubles nofpu mbig-endian-data +MULTILIB_DIRNAMES = 64-bit-double no-fpu-libs big-endian-data + +MULTILIB_MATCHES = nofpu=mnofpu nofpu=mcpu?rx200 nofpu=mcpu?RX200 + MULTILIB_EXCEPTIONS = MULTILIB_EXTRA_OPTS = diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi index 5022c4a80db..44bbd4a7794 100644 --- a/gcc/doc/invoke.texi +++ b/gcc/doc/invoke.texi @@ -15453,41 +15453,49 @@ This option sets flags for both the preprocessor and linker. @subsection RX Options @cindex RX Options -These @option{-m} options are defined for RX implementations: +These command line options are defined for RX targets: @table @gcctabopt @item -m64bit-doubles @itemx -m32bit-doubles -@itemx -fpu -@itemx -nofpu @opindex m64bit-doubles @opindex m32bit-doubles -@opindex fpu -@opindex nofpu Make the @code{double} data type be 64-bits (@option{-m64bit-doubles}) or 32-bits (@option{-m32bit-doubles}) in size. The default is -@option{-m64bit-doubles}. @emph{Note} the RX's hardware floating -point instructions are only used for 32-bit floating point values, and -then only if @option{-ffast-math} has been specified on the command -line. This is because the RX FPU instructions do not properly support -denormal (or sub-normal) values. - -The options @option{-fpu} and @option{-nofpu} have been provided at -the request of Rensas for compatibility with their toolchain. The -@option{-mfpu} option enables the use of RX FPU instructions by -selecting 32-bit doubles and enabling unsafe math optimizations. The -@option{-mnofpu} option disables the use of RX FPU instructions, even -if @option{-m32bit-doubles} is active and unsafe math optimizations -have been enabled. +@option{-m32bit-doubles}. @emph{Note} RX floating point hardware only +works on 32-bit values, which is why the default is +@option{-m32bit-doubles}. + +@item -fpu +@itemx -nofpu +@opindex fpu +@opindex nofpu +Enables (@option{-fpu}) or disables (@option{-nofpu}) the use of RX +floating point hardware. The default is enabled for the @var{RX600} +series and disabled for the @var{RX200} series. + +Floating point instructions will only be generated for 32-bit floating +point values however, so if the @option{-m64bit-doubles} option is in +use then the FPU hardware will not be used for doubles. + +@emph{Note} If the @option{-fpu} option is enabled then +@option{-funsafe-math-optimizations} is also enabled automatically. +This is because the RX FPU instructions are themselves unsafe. @item -mcpu=@var{name} @itemx -patch=@var{name} @opindex -mcpu @opindex -patch -Selects the type of RX CPU to be targeted. Currently on two types are -supported, the generic @var{RX600} and the specific @var{RX610}. The -only difference between them is that the @var{RX610} does not support -the @code{MVTIPL} instruction. +Selects the type of RX CPU to be targeted. Currently three types are +supported, the generic @var{RX600} and @var{RX200} series hardware and +the specific @var{RX610} cpu. The default is @var{RX600}. + +The only difference between @var{RX600} and @var{RX610} is that the +@var{RX610} does not support the @code{MVTIPL} instruction. + +The @var{RX200} series does not have a hardware floating point unit +and so @option{-nofpu} is enabled by default when this type is +selected. @item -mbig-endian-data @itemx -mlittle-endian-data |