diff options
| -rw-r--r-- | gcc/config/i386/i386.c | 8 | ||||
| -rw-r--r-- | gcc/testsuite/gcc.target/i386/pr82267.c | 14 |
2 files changed, 22 insertions, 0 deletions
diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c index 4f036ba9e20..4cf981fe981 100644 --- a/gcc/config/i386/i386.c +++ b/gcc/config/i386/i386.c @@ -18678,6 +18678,14 @@ ix86_print_operand_address_as (FILE *file, rtx addr, code = 'k'; } + /* Since the upper 32 bits of RSP are always zero for x32, we can + encode %esp as %rsp to avoid 0x67 prefix if there is no index or + base register. */ + if (TARGET_X32 && Pmode == SImode + && ((!index && base && REGNO (base) == SP_REG) + || (!base && index && REGNO (index) == SP_REG))) + code = 'q'; + if (ASSEMBLER_DIALECT == ASM_ATT) { if (disp) diff --git a/gcc/testsuite/gcc.target/i386/pr82267.c b/gcc/testsuite/gcc.target/i386/pr82267.c new file mode 100644 index 00000000000..5e4b271d41d --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr82267.c @@ -0,0 +1,14 @@ +/* { dg-do compile { target { ! ia32 } } } */ +/* { dg-require-effective-target maybe_x32 } */ +/* { dg-options "-O2 -mx32 -maddress-mode=short" } */ + +int +stackuse (void) +{ + volatile int foo = 2; + return foo * 3; +} + +/* Verify we that use %rsp to access stack. */ +/* { dg-final { scan-assembler-not "%esp" } } */ +/* { dg-final { scan-assembler "%rsp" } } */ |