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-rw-r--r--gcc/ChangeLog21
-rw-r--r--gcc/config/arm/arm.h4
-rw-r--r--gcc/config/c6x/c6x.c4
-rw-r--r--gcc/config/frv/frv.c4
-rw-r--r--gcc/config/sh/sh.c11
-rw-r--r--gcc/config/xtensa/xtensa.c4
-rw-r--r--gcc/expmed.c3
-rw-r--r--gcc/ree.c5
8 files changed, 40 insertions, 16 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 87f5885342f..0c021aeb48b 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,5 +1,26 @@
2017-09-12 Richard Sandiford <richard.sandiford@linaro.org>
+ * config/arm/arm.h (THUMB_SECONDARY_INPUT_RELOAD_CLASS): Use
+ hard_regno_nregs instead of HARD_REGNO_NREGS.
+ (THUMB_SECONDARY_OUTPUT_RELOAD_CLASS): Likewise.
+ * config/c6x/c6x.c (c6x_expand_prologue): Likewise.
+ (c6x_expand_epilogue): Likewise.
+ * config/frv/frv.c (frv_alloc_temp_reg): Likewise.
+ (frv_read_iacc_argument): Likewise.
+ * config/sh/sh.c: Include regs.h.
+ (sh_print_operand): Use hard_regno_nregs instead of HARD_REGNO_NREGS.
+ (regs_used): Likewise.
+ (output_stack_adjust): Likewise.
+ * config/xtensa/xtensa.c (xtensa_copy_incoming_a7): Likewise.
+ * expmed.c: Include regs.h.
+ (store_bit_field_1): Use hard_regno_nregs instead of HARD_REGNO_NREGS.
+ * ree.c: Include regs.h.
+ (combine_reaching_defs): Use hard_regno_nregs instead of
+ HARD_REGNO_NREGS.
+ (add_removable_extension): Likewise.
+
+2017-09-12 Richard Sandiford <richard.sandiford@linaro.org>
+
* regs.h (hard_regno_nregs): Turn into a function.
(end_hard_regno): Update accordingly.
* caller-save.c (setup_save_areas): Likewise.
diff --git a/gcc/config/arm/arm.h b/gcc/config/arm/arm.h
index bef66027687..8a40b43f61e 100644
--- a/gcc/config/arm/arm.h
+++ b/gcc/config/arm/arm.h
@@ -1211,7 +1211,7 @@ enum reg_class
(lra_in_progress ? NO_REGS \
: ((CLASS) != LO_REGS && (CLASS) != BASE_REGS \
? ((true_regnum (X) == -1 ? LO_REGS \
- : (true_regnum (X) + HARD_REGNO_NREGS (0, MODE) > 8) ? LO_REGS \
+ : (true_regnum (X) + hard_regno_nregs (0, MODE) > 8) ? LO_REGS \
: NO_REGS)) \
: NO_REGS))
@@ -1219,7 +1219,7 @@ enum reg_class
(lra_in_progress ? NO_REGS \
: (CLASS) != LO_REGS && (CLASS) != BASE_REGS \
? ((true_regnum (X) == -1 ? LO_REGS \
- : (true_regnum (X) + HARD_REGNO_NREGS (0, MODE) > 8) ? LO_REGS \
+ : (true_regnum (X) + hard_regno_nregs (0, MODE) > 8) ? LO_REGS \
: NO_REGS)) \
: NO_REGS)
diff --git a/gcc/config/c6x/c6x.c b/gcc/config/c6x/c6x.c
index e7f68414328..cbc44ecf0ff 100644
--- a/gcc/config/c6x/c6x.c
+++ b/gcc/config/c6x/c6x.c
@@ -2834,7 +2834,7 @@ c6x_expand_prologue (void)
reg);
RTX_FRAME_RELATED_P (insn) = 1;
- nsaved += HARD_REGNO_NREGS (regno, save_mode);
+ nsaved += hard_regno_nregs (regno, save_mode);
}
}
gcc_assert (nsaved == frame.nregs);
@@ -2922,7 +2922,7 @@ c6x_expand_epilogue (bool sibcall)
emit_move_insn (reg, adjust_address (mem, save_mode, off));
off += GET_MODE_SIZE (save_mode);
- nsaved += HARD_REGNO_NREGS (regno, save_mode);
+ nsaved += hard_regno_nregs (regno, save_mode);
}
}
if (!frame_pointer_needed)
diff --git a/gcc/config/frv/frv.c b/gcc/config/frv/frv.c
index add19e5cb14..83da2f15d6d 100644
--- a/gcc/config/frv/frv.c
+++ b/gcc/config/frv/frv.c
@@ -1509,7 +1509,7 @@ frv_alloc_temp_reg (
}
}
- nr = HARD_REGNO_NREGS (regno, mode);
+ nr = hard_regno_nregs (regno, mode);
info->next_reg[ (int)rclass ] = regno + nr;
if (mark_as_used)
@@ -8650,7 +8650,7 @@ frv_read_iacc_argument (machine_mode mode, tree call,
avoid creating lots of unnecessary call_insn rtl when IACCs aren't
being used. */
regno = INTVAL (op) + IACC_FIRST;
- for (i = 0; i < HARD_REGNO_NREGS (regno, mode); i++)
+ for (i = 0; i < hard_regno_nregs (regno, mode); i++)
global_regs[regno + i] = 1;
return gen_rtx_REG (mode, regno);
diff --git a/gcc/config/sh/sh.c b/gcc/config/sh/sh.c
index 22d1bf76802..01836893b77 100644
--- a/gcc/config/sh/sh.c
+++ b/gcc/config/sh/sh.c
@@ -63,6 +63,7 @@ along with GCC; see the file COPYING3. If not see
#include "context.h"
#include "builtins.h"
#include "rtl-iter.h"
+#include "regs.h"
/* This file should be included last. */
#include "target-def.h"
@@ -1392,8 +1393,8 @@ sh_print_operand (FILE *stream, rtx x, int code)
/* Floating point register pairs are always big endian;
general purpose registers are 64 bit wide. */
regno = REGNO (inner);
- regno = (HARD_REGNO_NREGS (regno, inner_mode)
- - HARD_REGNO_NREGS (regno, mode))
+ regno = (hard_regno_nregs (regno, inner_mode)
+ - hard_regno_nregs (regno, mode))
+ offset;
x = inner;
goto reg;
@@ -5371,7 +5372,7 @@ regs_used (rtx x, int is_dest)
{
case REG:
if (REGNO (x) < 16)
- return (((1 << HARD_REGNO_NREGS (0, GET_MODE (x))) - 1)
+ return (((1 << hard_regno_nregs (0, GET_MODE (x))) - 1)
<< (REGNO (x) + is_dest));
return 0;
case SUBREG:
@@ -5381,7 +5382,7 @@ regs_used (rtx x, int is_dest)
if (!REG_P (y))
break;
if (REGNO (y) < 16)
- return (((1 << HARD_REGNO_NREGS (0, GET_MODE (x))) - 1)
+ return (((1 << hard_regno_nregs (0, GET_MODE (x))) - 1)
<< (REGNO (y) +
subreg_regno_offset (REGNO (y),
GET_MODE (y),
@@ -6687,7 +6688,7 @@ output_stack_adjust (int size, rtx reg, int epilogue_p,
machine_mode mode;
mode = GET_MODE (crtl->return_rtx);
if (BASE_RETURN_VALUE_REG (mode) == FIRST_RET_REG)
- nreg = HARD_REGNO_NREGS (FIRST_RET_REG, mode);
+ nreg = hard_regno_nregs (FIRST_RET_REG, mode);
}
for (i = 0; i < nreg; i++)
CLEAR_HARD_REG_BIT (temps, FIRST_RET_REG + i);
diff --git a/gcc/config/xtensa/xtensa.c b/gcc/config/xtensa/xtensa.c
index 0f84cf3a7a0..0a4c441a4e0 100644
--- a/gcc/config/xtensa/xtensa.c
+++ b/gcc/config/xtensa/xtensa.c
@@ -1155,11 +1155,11 @@ xtensa_copy_incoming_a7 (rtx opnd)
}
if (GET_CODE (reg) != REG
|| REGNO (reg) > A7_REG
- || REGNO (reg) + HARD_REGNO_NREGS (A7_REG, mode) <= A7_REG)
+ || REGNO (reg) + hard_regno_nregs (A7_REG, mode) <= A7_REG)
return opnd;
/* 1-word args will always be in a7; 2-word args in a6/a7. */
- gcc_assert (REGNO (reg) + HARD_REGNO_NREGS (A7_REG, mode) - 1 == A7_REG);
+ gcc_assert (REGNO (reg) + hard_regno_nregs (A7_REG, mode) - 1 == A7_REG);
cfun->machine->need_a7_copy = false;
diff --git a/gcc/expmed.c b/gcc/expmed.c
index c61a8db43e1..f81163e15a5 100644
--- a/gcc/expmed.c
+++ b/gcc/expmed.c
@@ -31,6 +31,7 @@ along with GCC; see the file COPYING3. If not see
#include "tm_p.h"
#include "expmed.h"
#include "optabs.h"
+#include "regs.h"
#include "emit-rtl.h"
#include "diagnostic-core.h"
#include "fold-const.h"
@@ -952,7 +953,7 @@ store_bit_field_1 (rtx str_rtx, unsigned HOST_WIDE_INT bitsize,
&& GET_MODE_SIZE (op0_mode.require ()) > UNITS_PER_WORD
&& (!REG_P (op0)
|| !HARD_REGISTER_P (op0)
- || HARD_REGNO_NREGS (REGNO (op0), op0_mode.require ()) != 1))
+ || hard_regno_nregs (REGNO (op0), op0_mode.require ()) != 1))
{
if (bitnum % BITS_PER_WORD + bitsize > BITS_PER_WORD)
{
diff --git a/gcc/ree.c b/gcc/ree.c
index 9e04954d35b..19225d5833b 100644
--- a/gcc/ree.c
+++ b/gcc/ree.c
@@ -226,6 +226,7 @@ along with GCC; see the file COPYING3. If not see
#include "memmodel.h"
#include "tm_p.h"
#include "optabs.h"
+#include "regs.h"
#include "emit-rtl.h"
#include "recog.h"
#include "cfgrtl.h"
@@ -823,7 +824,7 @@ combine_reaching_defs (ext_cand *cand, const_rtx set_pat, ext_state *state)
return false;
/* Ensure the number of hard registers of the copy match. */
- if (HARD_REGNO_NREGS (REGNO (src_reg), dst_mode) != REG_NREGS (src_reg))
+ if (hard_regno_nregs (REGNO (src_reg), dst_mode) != REG_NREGS (src_reg))
return false;
/* There's only one reaching def. */
@@ -1135,7 +1136,7 @@ add_removable_extension (const_rtx expr, rtx_insn *insn,
We allow this when the registers are different because the
code in combine_reaching_defs will handle that case correctly. */
- if (HARD_REGNO_NREGS (REGNO (dest), mode) != REG_NREGS (reg)
+ if (hard_regno_nregs (REGNO (dest), mode) != REG_NREGS (reg)
&& reg_overlap_mentioned_p (dest, reg))
return;
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