libjava:

	Hashtable synchronization for PowerPC.
	* configure.in: Define SLOW_PTHREAD_SELF if configure.host set
	slow_pthread_self. Set up symlink for sysdeps directory.
	* configure: Rebuild.
	* configure.host: Document more shell variables. Set sysdeps_dir
	for most platforms. Set slow_pthread_self for i686. Set
	enable_hash_synchronization_default and slow_pthread_self for PowerPC.
	* posix-threads.cc (_Jv_ThreadSelf_out_of_line): Use release_set so
	that memory barrier is emitted where required.
	* prims.cc: 64-bit align static primitive class instances.
	* include/posix-threads.h (_Jv_ThreadSelf for SLOW_PTHREAD_SELF): Add
	read_barrier() to enforce ordering of reads.
	* sysdep/powerpc/locks.h: New file. Implementation of synchronization
	primitives for PowerPC.
	* sysdep/i386/locks.h: New file. Synchronization primitives for i386
	moved from natObject.cc.
	* sysdep/alpha/locks.h: Likewise.
	* sysdep/ia64/locks.h: Likewise.
	* sysdep/generic/locks.h: Likewise.
	* java/lang/natObject.cc: Move thread synchronization primitives to
	system-dependent headers.
gcc/java:
	* decl.c (java_init_decl_processing): Make sure class_type_node
	alignment is not less than 64 bits if hash synchronization isenabled.

boehm-gc:
	* include/gc_priv.h: Define ALIGN_DOUBLE on 32 bit targets if GCJ
	support is enabled, for hash synchronization.


git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@50523 138bc75d-0d04-0410-961f-82ee72b054a4

1 files changed, 3 insertions, 5 deletions

diff --git a/libjava/posix-threads.cc b/libjava/posix-threads.cc
index f068fbab53d..6442eaffb2f 100644
--- a/libjava/posix-threads.cc
+++ b/libjava/posix-threads.cc
@@ -438,19 +438,17 @@ _Jv_ThreadWait (void)
 
 #if defined(SLOW_PTHREAD_SELF)
 
-// Support for pthread_self() lookup cache.
+#include "sysdep/locks.h"
 
+// Support for pthread_self() lookup cache.
 volatile self_cache_entry _Jv_self_cache[SELF_CACHE_SIZE];
 
-
 _Jv_ThreadId_t
 _Jv_ThreadSelf_out_of_line(volatile self_cache_entry *sce, size_t high_sp_bits)
 {
   pthread_t self = pthread_self();
-  // The ordering between the following writes matters.
-  // On Alpha, we probably need a memory barrier in the middle.
   sce -> high_sp_bits = high_sp_bits;
-  sce -> self = self;
+  release_set ((obj_addr_t *) &(sce -> self), self);
   return self;
 }