diff options
| author | torvald <torvald@138bc75d-0d04-0410-961f-82ee72b054a4> | 2017-01-18 20:22:02 +0000 |
|---|---|---|
| committer | torvald <torvald@138bc75d-0d04-0410-961f-82ee72b054a4> | 2017-01-18 20:22:02 +0000 |
| commit | e617f12e3324517e1dc744fba1f9fe081794ab29 (patch) | |
| tree | a570e6248bee46a42e3612e3408cef9a3d26518a /libitm | |
| parent | 288e4639cf6dec9c33f9336c7ee1213576396c9a (diff) | |
| download | gcc-e617f12e3324517e1dc744fba1f9fe081794ab29.tar.gz | |
libitm: Disable TSX on processors on which it may be broken.
libitm/ChangeLog
* config/x86/target.h (htm_available): Add check for some processors
on which TSX is broken.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@244594 138bc75d-0d04-0410-961f-82ee72b054a4
Diffstat (limited to 'libitm')
| -rw-r--r-- | libitm/ChangeLog | 5 | ||||
| -rw-r--r-- | libitm/config/x86/target.h | 22 |
2 files changed, 27 insertions, 0 deletions
diff --git a/libitm/ChangeLog b/libitm/ChangeLog index 13e5e91a54e..d50005f4d91 100644 --- a/libitm/ChangeLog +++ b/libitm/ChangeLog @@ -1,3 +1,8 @@ +2017-01-18 Torvald Riegel <triegel@redhat.com> + + * config/x86/target.h (htm_available): Add check for some processors + on which TSX is broken. + 2017-01-17 Jakub Jelinek <jakub@redhat.com> PR other/79046 diff --git a/libitm/config/x86/target.h b/libitm/config/x86/target.h index 8d0a0da58aa..665c7d6e986 100644 --- a/libitm/config/x86/target.h +++ b/libitm/config/x86/target.h @@ -78,6 +78,28 @@ htm_available () if (__get_cpuid_max (0, NULL) >= 7) { unsigned a, b, c, d; + /* TSX is broken on some processors. This can be fixed by microcode, + but we cannot reliably detect whether the microcode has been + updated. Therefore, do not report availability of TSX on these + processors. We use the same approach here as in glibc (see + https://sourceware.org/ml/libc-alpha/2016-12/msg00470.html). */ + __cpuid (0, a, b, c, d); + if (b == 0x756e6547 && c == 0x6c65746e && d == 0x49656e69) + { + __cpuid (1, a, b, c, d); + if (((a >> 8) & 0x0f) == 0x06) // Family. + { + unsigned model = ((a >> 4) & 0x0f) // Model. + + ((a >> 12) & 0xf0); // Extended model. + unsigned stepping = a & 0x0f; + if ((model == 0x3c) + || (model == 0x45) + || (model == 0x46) + /* Xeon E7 v3 has correct TSX if stepping >= 4. */ + || ((model == 0x3f) && (stepping < 4))) + return false; + } + } __cpuid_count (7, 0, a, b, c, d); if (b & cpuid_rtm) return true; |