Minor BRIG/HSAIL frontend updates and bug fixes:

* brig-builtins.def: Added a builtin for class_f64.
* builtin-types.def: Added a builtin type needed by class_f64.
* brigfrontend/brig-code-entry-handler.cc
 (brig_code_entry_handler::build_address_operand): Fix a bug
 with reg+offset addressing on 32b segments. In large mode,
 the offset is treated as 32bits unless it's global, readonly or
 kernarg address space.
* rt/workitems.c: Removed a leftover comment.
* rt/arithmetic.c (__hsail_class_f32, __hsail_class_f64): Fix the
 check for signaling/non-signalling NaN. Add class_f64 default
 implementation.

From-SVN: r247576

3 files changed, 33 insertions, 14 deletions

diff --git a/libhsail-rt/ChangeLog b/libhsail-rt/ChangeLog
index 70aecf364bf..31ffff694c7 100644
--- a/libhsail-rt/ChangeLog
+++ b/libhsail-rt/ChangeLog
@@ -1,3 +1,10 @@
+2017-05-03  Pekka Jääskeläinen  <pekka.jaaskelainen@parmance.com>
+
+	* rt/workitems.c: Removed a leftover comment.
+	* rt/arithmetic.c (__hsail_class_f32, __hsail_class_f64): Fix the
+	check for signaling/non-signalling NaN. Add class_f64 default
+	implementation.
+
 2017-02-01  Jakub Jelinek  <jakub@redhat.com>
 
 	* configure.tgt: Fix i?86-*-linux* entry.
diff --git a/libhsail-rt/rt/arithmetic.c b/libhsail-rt/rt/arithmetic.c
index 3d8e62c7741..80852d58833 100644
--- a/libhsail-rt/rt/arithmetic.c
+++ b/libhsail-rt/rt/arithmetic.c
@@ -424,18 +424,34 @@ __hsail_fract_f64 (double a)
 uint32_t
 __hsail_class_f32 (float a, uint32_t flags)
 {
-  return (flags & 0x0001 && isnan (a) && !(*(uint32_t *) &a & 0x40000000))
-	 || (flags & 0x0002 && isnan (a) && (*(uint32_t *) &a & 0x40000000))
-	 || (flags & 0x0004 && isinf (a) && a < 0.0f)
-	 || (flags & 0x0008 && isnormal (a) && signbit (a))
-	 || (flags & 0x0010 && a < 0.0f && a > -FLT_MIN)
-	 || (flags & 0x0020 && a == 0.0f && signbit (a))
-	 || (flags & 0x0040 && a == 0.0f && !signbit (a))
-	 || (flags & 0x0080 && a > 0.0f && a < FLT_MIN)
-	 || (flags & 0x0100 && isnormal (a) && !signbit (a))
-	 || (flags & 0x0200 && isinf (a) && a >= 0.0f);
+  return (flags & 0x0001 && isnan (a) && !(*(uint32_t *) &a & (1ul << 22)))
+    || (flags & 0x0002 && isnan (a) && (*(uint32_t *) &a & (1ul << 22)))
+    || (flags & 0x0004 && isinf (a) && a < 0.0f)
+    || (flags & 0x0008 && isnormal (a) && signbit (a))
+    || (flags & 0x0010 && a < 0.0f && a > -FLT_MIN)
+    || (flags & 0x0020 && a == 0.0f && signbit (a))
+    || (flags & 0x0040 && a == 0.0f && !signbit (a))
+    || (flags & 0x0080 && a > 0.0f && a < FLT_MIN)
+    || (flags & 0x0100 && isnormal (a) && !signbit (a))
+    || (flags & 0x0200 && isinf (a) && a >= 0.0f);
 }
 
+uint32_t
+__hsail_class_f64 (double a, uint32_t flags)
+{
+  return (flags & 0x0001 && isnan (a) && !(*(uint64_t *) &a & (1ul << 51)))
+    || (flags & 0x0002 && isnan (a) && (*(uint64_t *) &a & (1ul << 51)))
+    || (flags & 0x0004 && isinf (a) && a < 0.0f)
+    || (flags & 0x0008 && isnormal (a) && signbit (a))
+    || (flags & 0x0010 && a < 0.0f && a > -FLT_MIN)
+    || (flags & 0x0020 && a == 0.0f && signbit (a))
+    || (flags & 0x0040 && a == 0.0f && !signbit (a))
+    || (flags & 0x0080 && a > 0.0f && a < FLT_MIN)
+    || (flags & 0x0100 && isnormal (a) && !signbit (a))
+    || (flags & 0x0200 && isinf (a) && a >= 0.0f);
+}
+
+
 /* 'class' for a f32-converted f16 which should otherwise be treated like f32
  except for its limits.  */
 
diff --git a/libhsail-rt/rt/workitems.c b/libhsail-rt/rt/workitems.c
index 1114e595556..e2c2373757a 100644
--- a/libhsail-rt/rt/workitems.c
+++ b/libhsail-rt/rt/workitems.c
@@ -63,10 +63,6 @@ static clock_t start_time;
 #define FIBER_STACK_SIZE (64*1024)
 #define GROUP_SEGMENT_ALIGN 256
 
-/* HSA requires WGs to be executed in flat work-group id order.  Enabling
-   the following macro can reveal test cases that rely on the ordering,
-   but is not useful for much else.  */
-
 uint32_t __hsail_workitemabsid (uint32_t dim, PHSAWorkItem *context);
 
 uint32_t __hsail_workitemid (uint32_t dim, PHSAWorkItem *context);