2012-12-05 Basile Starynkevitch <basile@starynkevitch.net>

	MELT branch merged with trunk rev 194222 using svnmerge.py



git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/branches/melt-branch@194223 138bc75d-0d04-0410-961f-82ee72b054a4

7 files changed, 105 insertions, 161 deletions

diff --git a/libgcc/config/aarch64/sfp-exceptions.c b/libgcc/config/aarch64/sfp-exceptions.c
new file mode 100644
index 00000000000..878cf8f95cd
--- /dev/null
+++ b/libgcc/config/aarch64/sfp-exceptions.c
@@ -0,0 +1,76 @@
+/*
+ * Copyright (C) 2012 Free Software Foundation, Inc.
+ *
+ * This file is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 3, or (at your option) any
+ * later version.
+ *
+ * This file is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * General Public License for more details.
+ *
+ * Under Section 7 of GPL version 3, you are granted additional
+ * permissions described in the GCC Runtime Library Exception, version
+ * 3.1, as published by the Free Software Foundation.
+ *
+ * You should have received a copy of the GNU General Public License and
+ * a copy of the GCC Runtime Library Exception along with this program;
+ * see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
+ * <http://www.gnu.org/licenses/>.
+ */
+
+#include "sfp-machine.h"
+
+void
+__sfp_handle_exceptions (int _fex)
+{
+  const float fp_max = __FLT_MAX__;
+  const float fp_min = __FLT_MIN__;
+  const float fp_1e32 = 1.0e32f;
+  const float fp_zero = 0.0;
+  const float fp_one = 1.0;
+  unsigned fpsr;
+
+  if (_fex & FP_EX_INVALID)
+    {
+      __asm__ __volatile__ ("fdiv\ts0, %s0, %s0"
+			    :
+			    : "w" (fp_zero)
+			    : "s0");
+      __asm__ __volatile__ ("mrs\t%0, fpsr" : "=r" (fpsr));
+    }
+  if (_fex & FP_EX_DIVZERO)
+    {
+      __asm__ __volatile__ ("fdiv\ts0, %s0, %s1"
+			    :
+			    : "w" (fp_one), "w" (fp_zero)
+			    : "s0");
+      __asm__ __volatile__ ("mrs\t%0, fpsr" : "=r" (fpsr));
+    }
+  if (_fex & FP_EX_OVERFLOW)
+    {
+      __asm__ __volatile__ ("fadd\ts0, %s0, %s1"
+			    :
+			    : "w" (fp_max), "w" (fp_1e32)
+			    : "s0");
+      __asm__ __volatile__ ("mrs\t%0, fpsr" : "=r" (fpsr));
+    }
+  if (_fex & FP_EX_UNDERFLOW)
+    {
+      __asm__ __volatile__ ("fmul\ts0, %s0, %s0"
+			    :
+			    : "w" (fp_min)
+			    : "s0");
+      __asm__ __volatile__ ("mrs\t%0, fpsr" : "=r" (fpsr));
+    }
+  if (_fex & FP_EX_INEXACT)
+    {
+      __asm__ __volatile__ ("fsub\ts0, %s0, %s1"
+			    :
+			    : "w" (fp_max), "w" (fp_one)
+			    : "s0");
+      __asm__ __volatile__ ("mrs\t%0, fpsr" : "=r" (fpsr));
+    }
+}
diff --git a/libgcc/config/aarch64/sfp-machine.h b/libgcc/config/aarch64/sfp-machine.h
index 3a09ae7605f..52b6fb2c446 100644
--- a/libgcc/config/aarch64/sfp-machine.h
+++ b/libgcc/config/aarch64/sfp-machine.h
@@ -69,62 +69,26 @@ typedef int __gcc_CMPtype __attribute__ ((mode (__libgcc_cmp_return__)));
 #define FP_EX_OVERFLOW	0x04
 #define FP_EX_UNDERFLOW	0x08
 #define FP_EX_INEXACT	0x10
+#define FP_EX_SHIFT 8
+#define FP_EX_ALL \
+	(FP_EX_INVALID | FP_EX_DIVZERO | FP_EX_OVERFLOW | FP_EX_UNDERFLOW \
+	 | FP_EX_INEXACT)
 
-#define FP_HANDLE_EXCEPTIONS						\
-  do {									\
-    const float fp_max = __FLT_MAX__;					\
-    const float fp_min = __FLT_MIN__;					\
-    const float fp_1e32 = 1.0e32f;					\
-    const float fp_zero = 0.0;						\
-    const float fp_one = 1.0;						\
-    unsigned fpsr;							\
-    if (_fex & FP_EX_INVALID)						\
-      {									\
-        __asm__ __volatile__ ("fdiv\ts0, %s0, %s0"			\
-			      :						\
-			      : "w" (fp_zero)				\
-			      : "s0");					\
-	__asm__ __volatile__ ("mrs\t%0, fpsr" : "=r" (fpsr));		\
-      }									\
-    if (_fex & FP_EX_DIVZERO)						\
-      {									\
-	__asm__ __volatile__ ("fdiv\ts0, %s0, %s1"			\
-			      :						\
-			      : "w" (fp_one), "w" (fp_zero)		\
-			      : "s0");					\
-	__asm__ __volatile__ ("mrs\t%0, fpsr" : "=r" (fpsr));		\
-      }									\
-    if (_fex & FP_EX_OVERFLOW)						\
-      {									\
-        __asm__ __volatile__ ("fadd\ts0, %s0, %s1"			\
-			      :						\
-			      : "w" (fp_max), "w" (fp_1e32)		\
-			      : "s0");					\
-        __asm__ __volatile__ ("mrs\t%0, fpsr" : "=r" (fpsr));		\
-      }									\
-    if (_fex & FP_EX_UNDERFLOW)						\
-      {									\
-	__asm__ __volatile__ ("fmul\ts0, %s0, %s0"			\
-			      :						\
-			      : "w" (fp_min)				\
-			      : "s0");					\
-	__asm__ __volatile__ ("mrs\t%0, fpsr" : "=r" (fpsr));		\
-      }									\
-    if (_fex & FP_EX_INEXACT)						\
-      {									\
-	__asm__ __volatile__ ("fsub\ts0, %s0, %s1"			\
-			      :						\
-			      : "w" (fp_max), "w" (fp_one)		\
-			      : "s0");					\
-	__asm__ __volatile__ ("mrs\t%0, fpsr" : "=r" (fpsr));		\
-      }									\
-  } while (0)
+void __sfp_handle_exceptions (int);
 
+#define FP_HANDLE_EXCEPTIONS			\
+  do {						\
+    if (__builtin_expect (_fex, 0))		\
+      __sfp_handle_exceptions (_fex);		\
+  } while (0);
 
-#define FP_RND_NEAREST		0
-#define FP_RND_ZERO		0xc00000
+#define FP_TRAPPING_EXCEPTIONS ((_fpcr >> FP_EX_SHIFT) & FP_EX_ALL)
+
+#define FP_RND_NEAREST		0x000000
 #define FP_RND_PINF		0x400000
 #define FP_RND_MINF		0x800000
+#define FP_RND_ZERO		0xc00000
+#define FP_RND_MASK		0xc00000
 
 #define _FP_DECL_EX \
   unsigned long int _fpcr __attribute__ ((unused)) = FP_RND_NEAREST
@@ -135,7 +99,7 @@ typedef int __gcc_CMPtype __attribute__ ((mode (__libgcc_cmp_return__)));
 			  : "=r" (_fpcr));	\
   } while (0)
 
-#define FP_ROUNDMODE (_fpcr & 0xc00000)
+#define FP_ROUNDMODE (_fpcr & FP_RND_MASK)
 
 #define	__LITTLE_ENDIAN	1234
 #define	__BIG_ENDIAN	4321
diff --git a/libgcc/config/aarch64/t-softfp b/libgcc/config/aarch64/t-softfp
index 6500b5243e4..586dca22469 100644
--- a/libgcc/config/aarch64/t-softfp
+++ b/libgcc/config/aarch64/t-softfp
@@ -5,3 +5,5 @@ softfp_truncations := tfsf tfdf
 softfp_exclude_libgcc2 := n
 
 TARGET_LIBGCC2_CFLAGS += -Wno-missing-prototypes
+
+LIB2ADD += $(srcdir)/config/aarch64/sfp-exceptions.c
diff --git a/libgcc/config/arm/ieee754-df.S b/libgcc/config/arm/ieee754-df.S
index 99f1ebb796f..676f7c9d4ce 100644
--- a/libgcc/config/arm/ieee754-df.S
+++ b/libgcc/config/arm/ieee754-df.S
@@ -1,6 +1,7 @@
 /* ieee754-df.S double-precision floating point support for ARM
 
-   Copyright (C) 2003, 2004, 2005, 2007, 2008, 2009  Free Software Foundation, Inc.
+   Copyright (C) 2003, 2004, 2005, 2007, 2008, 2009, 2012
+   Free Software Foundation, Inc.
    Contributed by Nicolas Pitre (nico@cam.org)
 
    This file is free software; you can redistribute it and/or modify it
@@ -36,9 +37,7 @@
  */
 
 
-@ For FPA, float words are always big-endian.
-@ For VFP, floats words follow the memory system mode.
-#if defined(__VFP_FP__) && !defined(__ARMEB__)
+#ifndef __ARMEB__
 #define xl r0
 #define xh r1
 #define yl r2
@@ -494,24 +493,10 @@ ARM_FUNC_START floatundidf
 ARM_FUNC_ALIAS aeabi_ul2d floatundidf
 
 	orrs	r2, r0, r1
-#if !defined (__VFP_FP__) && !defined(__SOFTFP__)
-	do_it	eq, t
-	mvfeqd	f0, #0.0
-#else
 	do_it	eq
-#endif
 	RETc(eq)
 
-#if !defined (__VFP_FP__) && !defined(__SOFTFP__)
-	@ For hard FPA code we want to return via the tail below so that
-	@ we can return the result in f0 as well as in r0/r1 for backwards
-	@ compatibility.
-	adr	ip, LSYM(f0_ret)
-	@ Push pc as well so that RETLDM works correctly.
-	do_push	{r4, r5, ip, lr, pc}
-#else
 	do_push	{r4, r5, lr}
-#endif
 
 	mov	r5, #0
 	b	2f
@@ -520,24 +505,10 @@ ARM_FUNC_START floatdidf
 ARM_FUNC_ALIAS aeabi_l2d floatdidf
 
 	orrs	r2, r0, r1
-#if !defined (__VFP_FP__) && !defined(__SOFTFP__)
-	do_it	eq, t
-	mvfeqd	f0, #0.0
-#else
 	do_it	eq
-#endif
 	RETc(eq)
 
-#if !defined (__VFP_FP__) && !defined(__SOFTFP__)
-	@ For hard FPA code we want to return via the tail below so that
-	@ we can return the result in f0 as well as in r0/r1 for backwards
-	@ compatibility.
-	adr	ip, LSYM(f0_ret)
-	@ Push pc as well so that RETLDM works correctly.
-	do_push	{r4, r5, ip, lr, pc}
-#else
 	do_push	{r4, r5, lr}
-#endif
 
 	ands	r5, ah, #0x80000000	@ sign bit in r5
 	bpl	2f
@@ -552,7 +523,7 @@ ARM_FUNC_ALIAS aeabi_l2d floatdidf
 	mov	r4, #0x400		@ initial exponent
 	add	r4, r4, #(52-1 - 1)
 
-	@ FPA little-endian: must swap the word order.
+	@ If FP word order does not match integer word order, swap the words.
 	.ifnc	xh, ah
 	mov	ip, al
 	mov	xh, ah
@@ -580,17 +551,6 @@ ARM_FUNC_ALIAS aeabi_l2d floatdidf
 	add	r4, r4, r2
 	b	LSYM(Lad_p)
 
-#if !defined (__VFP_FP__) && !defined(__SOFTFP__)
-
-	@ Legacy code expects the result to be returned in f0.  Copy it
-	@ there as well.
-LSYM(f0_ret):
-	do_push	{r0, r1}
-	ldfd	f0, [sp], #8
-	RETLDM
-
-#endif
-
 	FUNC_END floatdidf
 	FUNC_END aeabi_l2d
 	FUNC_END floatundidf
diff --git a/libgcc/config/arm/ieee754-sf.S b/libgcc/config/arm/ieee754-sf.S
index cf4ff0e144f..397a4c16b7b 100644
--- a/libgcc/config/arm/ieee754-sf.S
+++ b/libgcc/config/arm/ieee754-sf.S
@@ -1,6 +1,7 @@
 /* ieee754-sf.S single-precision floating point support for ARM
 
-   Copyright (C) 2003, 2004, 2005, 2007, 2008, 2009  Free Software Foundation, Inc.
+   Copyright (C) 2003, 2004, 2005, 2007, 2008, 2009, 2012
+   Free Software Foundation, Inc.
    Contributed by Nicolas Pitre (nico@cam.org)
 
    This file is free software; you can redistribute it and/or modify it
@@ -325,12 +326,7 @@ ARM_FUNC_START floatundisf
 ARM_FUNC_ALIAS aeabi_ul2f floatundisf
 
 	orrs	r2, r0, r1
-#if !defined (__VFP_FP__) && !defined(__SOFTFP__)
-	do_it	eq, t
-	mvfeqs	f0, #0.0
-#else
 	do_it	eq
-#endif
 	RETc(eq)
 
 	mov	r3, #0
@@ -340,12 +336,7 @@ ARM_FUNC_START floatdisf
 ARM_FUNC_ALIAS aeabi_l2f floatdisf
 
 	orrs	r2, r0, r1
-#if !defined (__VFP_FP__) && !defined(__SOFTFP__)
-	do_it	eq, t
-	mvfeqs	f0, #0.0
-#else
 	do_it	eq
-#endif
 	RETc(eq)
 
 	ands	r3, ah, #0x80000000	@ sign bit in r3
@@ -358,14 +349,6 @@ ARM_FUNC_ALIAS aeabi_l2f floatdisf
 	rsc	ah, ah, #0
 #endif
 1:
-#if !defined (__VFP_FP__) && !defined(__SOFTFP__)
-	@ For hard FPA code we want to return via the tail below so that
-	@ we can return the result in f0 as well as in r0 for backwards
-	@ compatibility.
-	str	lr, [sp, #-8]!
-	adr	lr, LSYM(f0_ret)
-#endif
-
 	movs	ip, ah
 	do_it	eq, tt
 	moveq	ip, al
@@ -427,15 +410,6 @@ ARM_FUNC_ALIAS aeabi_l2f floatdisf
 	biceq	r0, r0, ip, lsr #31
 	RET
 
-#if !defined (__VFP_FP__) && !defined(__SOFTFP__)
-
-LSYM(f0_ret):
-	str	r0, [sp, #-4]!
-	ldfs	f0, [sp], #4
-	RETLDM
-
-#endif
-
 	FUNC_END floatdisf
 	FUNC_END aeabi_l2f
 	FUNC_END floatundisf
diff --git a/libgcc/config/arm/pr-support.c b/libgcc/config/arm/pr-support.c
index deee661e264..e0973b51971 100644
--- a/libgcc/config/arm/pr-support.c
+++ b/libgcc/config/arm/pr-support.c
@@ -1,5 +1,5 @@
 /* ARM EABI compliant unwinding routines
-   Copyright (C) 2004, 2005, 2009 Free Software Foundation, Inc.
+   Copyright (C) 2004, 2005, 2009, 2012 Free Software Foundation, Inc.
    Contributed by Paul Brook
  
    This file is free software; you can redistribute it and/or modify it
@@ -226,15 +226,9 @@ __gnu_unwind_execute (_Unwind_Context * context, __gnu_unwind_state * uws)
 		return _URC_FAILURE;
 	      continue;
 	    }
-	  if ((op & 0xfc) == 0xb4)
-	    {
-	      /* Pop FPA E[4]-E[4+nn].  */
-	      op = 0x40000 | ((op & 3) + 1);
-	      if (_Unwind_VRS_Pop (context, _UVRSC_FPA, op, _UVRSD_FPAX)
-		  != _UVRSR_OK)
-		return _URC_FAILURE;
-	      continue;
-	    }
+	  if ((op & 0xfc) == 0xb4)  /* Obsolete FPA.  */
+	    return _URC_FAILURE;
+
 	  /* op & 0xf8 == 0xb8.  */
 	  /* Pop VFP D[8]-D[8+nnn] with fldmx.  */
 	  op = 0x80000 | ((op & 7) + 1);
@@ -278,15 +272,6 @@ __gnu_unwind_execute (_Unwind_Context * context, __gnu_unwind_state * uws)
 	    }
 	  if (op == 0xc8)
 	    {
-#ifndef __VFP_FP__
- 	      /* Pop FPA registers.  */
- 	      op = next_unwind_byte (uws);
-	      op = ((op & 0xf0) << 12) | ((op & 0xf) + 1);
- 	      if (_Unwind_VRS_Pop (context, _UVRSC_FPA, op, _UVRSD_FPAX)
- 		  != _UVRSR_OK)
- 		return _URC_FAILURE;
- 	      continue;
-#else
               /* Pop VFPv3 registers D[16+ssss]-D[16+ssss+cccc] with vldm.  */
               op = next_unwind_byte (uws);
               op = (((op & 0xf0) + 16) << 12) | ((op & 0xf) + 1);
@@ -294,7 +279,6 @@ __gnu_unwind_execute (_Unwind_Context * context, __gnu_unwind_state * uws)
                   != _UVRSR_OK)
                 return _URC_FAILURE;
               continue;
-#endif
 	    }
 	  if (op == 0xc9)
 	    {
diff --git a/libgcc/config/arm/unwind-arm.c b/libgcc/config/arm/unwind-arm.c
index 1e8ca619ae2..27d68f992ba 100644
--- a/libgcc/config/arm/unwind-arm.c
+++ b/libgcc/config/arm/unwind-arm.c
@@ -1,5 +1,5 @@
 /* ARM EABI compliant unwinding routines.
-   Copyright (C) 2004, 2005, 2009 Free Software Foundation, Inc.
+   Copyright (C) 2004, 2005, 2009, 2012 Free Software Foundation, Inc.
    Contributed by Paul Brook
 
    This file is free software; you can redistribute it and/or modify it
@@ -53,16 +53,6 @@ struct vfpv3_regs
   _uw64 d[16];
 };
 
-struct fpa_reg
-{
-  _uw w[3];
-};
-
-struct fpa_regs
-{
-  struct fpa_reg f[8];
-};
-
 struct wmmxd_regs
 {
   _uw64 wd[16];
@@ -90,7 +80,6 @@ typedef struct
   _uw prev_sp; /* Only valid during forced unwinding.  */
   struct vfp_regs vfp;
   struct vfpv3_regs vfp_regs_16_to_31;
-  struct fpa_regs fpa;
   struct wmmxd_regs wmmxd;
   struct wmmxc_regs wmmxc;
 } phase1_vrs;
@@ -181,7 +170,6 @@ _Unwind_VRS_Result _Unwind_VRS_Get (_Unwind_Context *context,
       return _UVRSR_OK;
 
     case _UVRSC_VFP:
-    case _UVRSC_FPA:
     case _UVRSC_WMMXD:
     case _UVRSC_WMMXC:
       return _UVRSR_NOT_IMPLEMENTED;
@@ -213,7 +201,6 @@ _Unwind_VRS_Result _Unwind_VRS_Set (_Unwind_Context *context,
       return _UVRSR_OK;
 
     case _UVRSC_VFP:
-    case _UVRSC_FPA:
     case _UVRSC_WMMXD:
     case _UVRSC_WMMXC:
       return _UVRSR_NOT_IMPLEMENTED;
@@ -380,9 +367,6 @@ _Unwind_VRS_Result _Unwind_VRS_Pop (_Unwind_Context *context,
       }
       return _UVRSR_OK;
 
-    case _UVRSC_FPA:
-      return _UVRSR_NOT_IMPLEMENTED;
-
     case _UVRSC_WMMXD:
       {
 	_uw start = discriminator >> 16;